JPH0542831B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular to a thin film field effect transistor ( onwards
Abbreviated as TFT. ) This relates to thin film semiconductor devices such as arrays.

Taking a TFT array as an example, the present invention prevents film deterioration of the gate insulator and filler insulator of the TFT, ensures interlayer insulation, and connects the gate and gate bus metal layer to the source layer over a large area. The purpose is to eliminate electrical short circuits with the drain, source bus, and drain bus. Furthermore, it is an object of the present invention to reduce reflected light from gate and gate bus wiring metals and to improve the dynamic range of an image display element.

It is manufactured using plasma deposition method, sputtering method, thermal CVD, etc. at a relatively low temperature of 600℃ or less.
Semiconductors composed of amorphous or polycrystalline silicon or silicon compound semiconductor group elements whose atomic bonding pair instability is compensated for by hydrogen, fluorine, etc. have electron and hole mobilities of 0.01. ~ ^10cm2 /V・
Advantages include relatively large sec, good stability, non-polluting, easy expansion into large areas, and the ability to use low-cost substrates such as glass plates regardless of the substrate. . Furthermore, compared to single-crystal silicon, etc., it has a higher specific resistance in the film surface direction, and has the advantage of being able to have a larger ON-OFF ratio when used as a TFT.

For the above reasons, these semiconductor thin films are promising for application to switching arrays of thin film field effect transistors that constitute image display devices and the like by being combined with liquid crystals and the like.

Figures 1 and 2 are a plan view of the main parts of a thin film electrolytic transistor/switching array for a translucent image display device such as a liquid crystal cell, and a process cross-sectional view taken along line A-A' in Figure 1. be. In Figure 1, 1
is a transparent electrode for driving the liquid crystal, 2 is a gate electrode,
2' is a gate bus wiring connected to the gate electrode 2. 3 is a source electrode, 3' is a source bus line connected to the source electrode 3, and 4 is a drain electrode. Between the gate electrode 2 and gate bus 2' and the source electrode 2, source bus 2' and drain electrode 4, an insulating film layer of silicon nitride, silicon oxide, etc. is provided over the entire surface, and the contact hole 5 An electrical ohmic contact is formed between the drain 4 and the transparent electrode 1.

A conventional manufacturing method for the above-mentioned device will be sequentially explained using process cross-sectional views shown in FIG.
First, as shown in FIG. 2a, a transparent insulating substrate 20
A transparent electrode 1 for driving the liquid crystal and displaying an image is selectively deposited on each picture element, and a gate made of a metal film layer such as Mo is formed on the same surface so as not to overlap with the transparent electrode 1. They are selectively deposited as electrodes 2 and gate buses 2'. Next, a gate insulating film layer 6 and an interlayer insulating film 6' made of silicon nitride, silicon oxide, alumina, etc. are deposited over the entire surface by plasma deposition, sputtering, thermal CVD, etc.
Furthermore, a non-single crystal semiconductor 7 containing silicon as a main component is deposited by a plasma deposition method, a sputtering method, a thermal CVD method, or the like.

Next, as shown in FIG. 2b, the amorphous semiconductor layer 7 is selectively left only in the region 8 that will become the channel portion of the transistor. To selectively leave this non-single crystal semiconductor layer 7 mainly composed of silicon and remove other parts, a mixture of FH and HNO ₃ (CH ₃ COOH, NH ₄ F) is used using a mask 21 such as a photoresist pattern.
), etching with NaOH aqueous solution, etc. It is preferable not to use a NaOH aqueous solution since Na, a component thereof, has an adverse effect on transistor characteristics. By the way, the etching rate of the insulating film 6', such as silicon nitride or silicon oxide, which is deposited by plasma deposition or the like and exposed to an etching solution mainly composed of FH or HNO ₃ is lower than that of the amorphous semiconductor layer 7. The gate bus 2' is etched as shown by the broken line, and if the etching is poorly controlled, the gate bus 2' may be exposed as shown in FIG. 2b. That is, even if the insulating film 6' on the gate bus 2' is not completely removed, the etching solution etches the gate bus 2' through the pinball 10 of the insulating film 6', causing disconnection of the gate bus 2'. In addition, the insulating film 6' at the stepped portion of the bus 2' often has microcrack, which weakens this area, causing abnormal etching as shown in Figure 2b, exposing the bus 2'. .

Under these circumstances, a metal layer that will become the source, drain, and source bus is deposited, and the source, drain electrodes 3, 4, and source bus 3' are selectively patterned by etching or the like to complete the TFT.
Note that the image display device includes the substrate 20 and another transparent substrate 2.
d. 23 is a transparent electrode. TFT made in this way
The array is connected to source bus 3' as shown in Figure 2c.
The electrical short circuit rate of the gate bus 2' and the disconnection rate of the gate bus are high, and a large number of complete
It has been difficult to fabricate a TFT array that forms TFTs.

Therefore, the present invention was developed in view of this situation, and eliminates the above drawbacks by leaving the non-single crystal semiconductor layer not only on the channel portion of the TFT but also on the entire gate electrode and gate bus without being etched. This is what I am trying to do. Furthermore, the present invention suppresses reflected light from the gate and gate bus surfaces made of metal layers by leaving an amorphous semiconductor layer in areas other than the area necessary for image display (channel portion of TFT), thereby reducing the dynamics during image display. It improves honey cleansing.

For example, a non-single-crystal semiconductor layer whose main component is silicon and which is fabricated by a plasma deposition method used in TFTs has a high specific resistance of 10 ⁹ to 10 ¹⁴ Ωcm, and the iso-resistivity in the film thickness direction is large. The structure can withstand the use of TFT arrays even if the non-single-crystal semiconductor layer does not become an island.

The present invention will be explained in detail below with reference to Examples.
The basic structure of the TFT according to the present invention is the same as that of the conventional one, and can be explained by an array having the structure shown in FIG. A method according to an embodiment of the present invention will be explained in detail with reference to FIG. 3 in the cross-sectional manufacturing step corresponding to the section taken along the line A-A' in FIG. 1. Components with common functions in FIG. 3 are given the same numbers as in FIGS. 1 and 2.

First, as shown in FIG. 3a, a light-transmitting insulating substrate 2
A transparent electrode 1 with a thickness of about 1000 Å is selectively deposited on the substrate 20, and Mo metal with a thickness of about 3000 Å is deposited on the same surface of the substrate 20 as a gate electrode, gate bus 2,
2' is selectively deposited. Next, a mixed gas of silane and ammonia (H ₂ ,
Ar, _N2, etc. may also be included. ) etc., empty silicon is deposited to a thickness of about 4000 Å as a gate insulating film 6 and an interlayer insulating film 6'. The insulating films 6, 6' may be deposited by a sputtering method or a thermal CVD method, or may be a silicon oxide or other insulating layer. Next, an amorphous silicon layer is formed by a plasma discharge using silane as a raw material gas or a reactive sputtering method in which a single crystal or polycrystalline silicon target is sputtered in a mixed gas of H ₂ and Ar.
A non-single crystal semiconductor layer 7 for forming a channel portion of a TFT is deposited to a thickness of about 5000 Å.

Next, as shown in FIG. 3b, the amorphous silicon 7 and 7 are left in a region 11 which is larger than the overlapping region 8 of the gate electrode 2 and the gate bus 2' and the source bus 3'. etching. Then, a metal such as Al is formed and selectively etched to form a source electrode 2, a drain electrode 4, and a source bus 3' as shown in FIG. 3c.

As is clear from FIG. 3, if amorphous silicon 7 is left between the source bus 3' and gate bus 2' in addition to the silicon layer 7 in the portion that becomes the channel of the TFT, the silicon layer 7 Since the underlying insulating film 6' is not etched, it is possible to prevent short circuits between the source bus 3' and the gate bus 2' as shown in FIG. 2.

Next, in the present invention, a region where an amorphous semiconductor layer mainly composed of silicon is left will be explained using an enlarged view of a TFT array pixel.

As a first specific example of the present invention, as shown in FIG. 4, an amorphous silicon layer is etched in a region larger than the alignment accuracy of the gate electrode and gate bus photomask, convex BB′D′D″C″CD. This is to leave it as is. Originally, when a metal film such as Mo is used for the gate and gate bus, light does not pass through that part, and electrodes for driving the liquid crystal are not usually installed in that part, so the part does not contribute to image display and is amorphous. Even if the silicone remains, it does not affect the image display in any way. If the amorphous silicon layer is left in this way,
Since amorphous silicon is always left on the gate and gate bus together with the insulating film, the insulating film on the gate electrode and gate bus is not etched during selective etching of the amorphous silicon layer, and therefore the gate electrode and gate bus are not etched. Etching of the gate bus, etc. does not occur, and disconnection of the gate bus, etc. does not occur at all.

Furthermore, when gates, gate buses, etc. are made of metal films, it is possible to suppress the reflection of light from the gates and gate films as much as possible, so the background light relative to image display can be reduced and the dynamic range can be increased. I can do it.

In the second embodiment of the present invention, only the amorphous layer silicon in the region contributing to the image display shown in FIG. This part will remain. That is, Fig. 6 E ₁ ~
The amorphous silicon layer is left in the area surrounded by E ₄ and F ₁ to F ₆ . If this is done, the insulating film and amorphous silicon layer will remain on all the stepped portions, resulting in the maximum effect.

The specific resistance of an amorphous semiconductor whose dangling bonds are compensated for by hydrogen, fluorine, etc. whose main components are group elements is 10 ⁹ to 10 ¹⁴ Ω・cm (when irradiated with light, for example, under 100 mW of sunlight) 10 ⁵ to 10 ⁶ Ω・
cm, so even if the semiconductor layers of each picture element are connected as shown in Figure 6, each picture element can be electrically isolated, and there are no problems with isolation. does not occur.

As described above, the present invention uses a non-single crystal semiconductor layer containing a group element such as silicon as a main component.
In manufacturing TFT arrays, for example, not only the amorphous semiconductor layer of the TFT channel part but also the TFT
In addition to the channel portions of the gates, they are also actively installed on the entire surface of the gate electrodes and gate buses. According to the present invention, in a switching array of thin film electromagnetic effect transistors which constitute an image display device etc. by combining with liquid crystal cells etc.,
Actively placing an amorphous semiconductor layer between conductor wirings located through an insulating layer, for example, on the gate electrode and gate bus, or over the overlapping part between the gate electrode and gate bus and the source, drain electrode, or source bus. By doing so, the disconnection rate of gate electrodes and gate buses, and the rate of electrical short circuits between gate electrodes or gate buses and sources, drains, or source buses can be minimized, and products can be completely economized over a large area of TFT arrays. This is something that can be provided in a good manner. Furthermore, it is possible to suppress the reflection of light from the gate electrode and gate bus made of a metal film, etc., and it also has the effect of improving the dynamic lens of image display. Furthermore, a gate electrode, a gate bus and a source,
It is also possible to reduce the stray capacitance generated between the drain electrode and the source bus.

As is clear from the above description, the present invention is preferably a non-single crystal semiconductor whose main component is a group element such as silicon containing hydrogen or fluorine, and integration with a TF etc. using this semiconductor is preferred. It is particularly convenient for In addition, the insulating layer between the wiring is made of silicon nitride.
In addition to silicon oxide, silicon carbide, alumina, and the like may be used as appropriate. There is no problem even if the terms source and drain are interchanged, and as long as the films used for the gate electrode, gate bus, source, drain electrode, source bus, and image signal application electrode are conductive, Mo ,Al,
Various other materials such as transparent electrodes can be used.

Furthermore, although the present invention was explained in detail regarding TFT,
It goes without saying that the present invention is effective for all other thin film semiconductor devices in which there are two or more conductor layers with an insulating layer interposed therebetween and interlayer insulation between these conductor layers is important.

As described above, the present invention can eliminate disconnections of gate electrodes and gate buses, that is, gate wiring, and short circuits between source and drain wiring and gate wiring in a thin film semiconductor device, and the manufacturing method thereof is easy. This also greatly contributes to improving the performance of image display devices.

[Brief explanation of the drawing]

FIG. 1 is a partial plan view of a switching array for TFT image display using an amorphous semiconductor whose main component is silicon, and FIGS. The cross-sectional views of the manufacturing process along line A′, and FIGS. 3a to 3c show an embodiment of the present invention.
4 and 5 are partial plan views of a TFT array according to an embodiment of the present invention. 1...Transparent electrode, 2...Gate electrode, 2'...
Gate bus, 3... Source electrode, 3'... Source bus, 4... Drain electrode, 6, 6'... Insulating film,
7, 7〓, 7〓...Amorphous semiconductor film mainly composed of silicon, 20...Transparent insulating substrate, 22...Liquid crystal.

Claims (1)

[Claims] 1. A step of selectively depositing a first conductor layer that will become a gate electrode and a gate bus on an area other than a transparent image display area of an insulating substrate, and a step of depositing an insulating layer and a non-single crystal semiconductor on the entire surface. a step of selectively removing the non-single crystal semiconductor layer; and a step of selectively forming a second layer on the semiconductor layer to serve as a source electrode or a drain electrode and a source bus or a drain bus. depositing a conductor layer, and the step of removing the non-single crystal semiconductor layer includes depositing the non-single crystal semiconductor layer on the entire surface of the first conductor layer that has been selectively deposited. 1. A method for manufacturing a thin film semiconductor device, characterized in that the step includes remaining steps.