JPH0541146U - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPH0541146U JPH0541146U JP089910U JP8991091U JPH0541146U JP H0541146 U JPH0541146 U JP H0541146U JP 089910 U JP089910 U JP 089910U JP 8991091 U JP8991091 U JP 8991091U JP H0541146 U JPH0541146 U JP H0541146U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor chip
- island portion
- conductive member
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
(57)【要約】
【目的】 特に、携帯電話等の小型の装置に使用される
集積回路において、高周波信号の輻射による特性の劣化
を回避する。
【構成】 半導体チップ５はリードフレームのアイラン
ド部６の下面に搭載されている。そして、アイランド部
６は、２本以上のリードに電気的に接続されている。
【効果】 アイランド部及びプリント板に設けられた導
体パターンが高周波信号に対するシールド板として作用
し、高周波信号の輻射による特性の劣化を回避すること
ができる。
(57) [Abstract] [Purpose] In particular, in an integrated circuit used in a small device such as a mobile phone, deterioration of characteristics due to radiation of a high frequency signal is avoided. [Structure] The semiconductor chip 5 is mounted on the lower surface of the island portion 6 of the lead frame. The island portion 6 is electrically connected to two or more leads. [Effect] The conductor pattern provided on the island portion and the printed board acts as a shield board against a high frequency signal, and deterioration of characteristics due to radiation of the high frequency signal can be avoided.
Description
【０００１】[0001]
本考案は、特に、携帯電話等の小型の装置に使用される集積回路に好適の集積 回路に関する。 The present invention particularly relates to an integrated circuit suitable for an integrated circuit used in a small device such as a mobile phone.
【０００２】[0002]
図２は従来のモールド型集積回路を示す断面図である。 FIG. 2 is a sectional view showing a conventional mold type integrated circuit.
【０００３】 リードフレームは、アイランド部１６及びこのアイランド部１６の周囲に配設 された複数本のリード１４により構成されている。半導体チップ１５は、このリ ードフレームのアイランド部１６上に搭載されている。The lead frame is composed of an island portion 16 and a plurality of leads 14 arranged around the island portion 16. The semiconductor chip 15 is mounted on the island portion 16 of the lead frame.
【０００４】 半導体チップ１５の上面には電極が設けられており、この電極はリード１４の 一方の端部（アイランド部側の端部）にボンディングワイヤ１８を介して電気的 に接続されている。そして、半導体チップ１５及びボンディングワイヤ１８等は 、モールド樹脂１７により封止されている。An electrode is provided on the upper surface of the semiconductor chip 15, and this electrode is electrically connected to one end of the lead 14 (end on the island side) via a bonding wire 18. The semiconductor chip 15, the bonding wire 18 and the like are sealed with the mold resin 17.
【０００５】 リード１４の他方の端部側は、モールド樹脂１７の側部から導出されてその先 端部がプリント板１１の表面に接触するように曲げ加工されている。The other end of the lead 14 is bent from the side of the molding resin 17 so that the tip of the lead 14 contacts the surface of the printed board 11.
【０００６】 このように構成された集積回路をプリント板１１に実装する場合、リード１４ の先端部をプリント板１１に設けられた所定の導体パターン１２に整合させて配 置し、半田１３によりリード先端部を導体パターン１２に固定する。When the integrated circuit configured as described above is mounted on the printed board 11, the leads 14 are arranged by aligning the tips of the leads 14 with a predetermined conductor pattern 12 provided on the printed board 11, and the leads 13 are connected by the solder 13. The tip is fixed to the conductor pattern 12.
【０００７】 なお、上述の従来例においては、半導体チップが樹脂によりモールドされてい る樹脂モールド型集積回路の場合について説明したが、半導体チップがセラミッ クキャップにより封止されているセラミック型集積回路の場合も、樹脂モールド 型集積回路と同様に、半導体チップの上方には導電性部材が設けられていない。In the above-mentioned conventional example, the case of the resin mold type integrated circuit in which the semiconductor chip is molded with resin has been described. However, in the case of the ceramic type integrated circuit in which the semiconductor chip is sealed with the ceramic cap. Also in this case, similar to the resin mold type integrated circuit, the conductive member is not provided above the semiconductor chip.
【０００８】[0008]
しかしながら、上述した従来の集積回路においては、携帯電話等の小型の装置 に実装される場合には、チップ間隔が狭くなるために、例えば高周波のクロック 信号等がチップ表面からモールド樹脂又はセラミックキャップを介して他のチッ プに輻射され、この高周波信号の輻射により装置の特性が損なわれることがある という問題点がある。特に、無線器を構成する集積回路においては、高周波信号 の輻射による特性劣化が著しい。 However, in the above-described conventional integrated circuit, when it is mounted on a small device such as a mobile phone, the chip interval becomes narrow. There is a problem in that the characteristics of the device may be deteriorated by the radiation of the high frequency signal. In particular, in integrated circuits that constitute wireless devices, characteristic deterioration due to radiation of high-frequency signals is remarkable.
【０００９】 本考案はかかる問題点に鑑みてなされたものであって、高周波信号の輻射によ る特性の劣化を回避することができる集積回路を提供することを目的とする。The present invention has been made in view of the above problems, and an object thereof is to provide an integrated circuit capable of avoiding deterioration of characteristics due to radiation of a high frequency signal.
【００１０】[0010]
本考案に係る集積回路は、プリント板に実装される集積回路において、半導体 チップと、この半導体チップの上方に配置された導電性部材と、この導電性部材 及び前記半導体チップを封止する封止部材と、この封止部材の側部から導出され その先端部が前記プリント板に接合される複数本のリードとを有し、前記導電性 部材は前記複数本のリードのうちの少なくとも２本と電気的に接続されているこ とを特徴とする。 The integrated circuit according to the present invention is an integrated circuit mounted on a printed circuit board, wherein a semiconductor chip, a conductive member disposed above the semiconductor chip, a sealing member for sealing the conductive member and the semiconductor chip. A member and a plurality of leads that are led out from the side of the sealing member and have their tips joined to the printed board, and the conductive member is at least two of the plurality of leads. It is characterized by being electrically connected.
【００１１】[0011]
本考案においては、半導体チップの上方に導電性部材が配置されている。従っ て、本考案に係る集積回路をプリント板に実装した場合に、半導体チップは前記 導電性部材とプリント板の導体パターンとの間に位置することとなる。これによ り、前記導電性部材及びプリント板の導体パターンが高周波信号の輻射を遮蔽す るシールド板として作用するため、特性劣化を回避することができる。但し、前 記導電性部材は一定電位に保持する必要があり、導電性部材がリードに電気的に 接続されていないか、又は接続されているリードが１本だけであると、高周波信 号の輻射に対する十分なシールド効果を得ることができない。従って、前記導電 性部材は２本以上のリードに電気的に接続されていることが必要である。 In the present invention, the conductive member is arranged above the semiconductor chip. Therefore, when the integrated circuit according to the present invention is mounted on the printed board, the semiconductor chip is located between the conductive member and the conductor pattern of the printed board. As a result, the conductive member and the conductor pattern of the printed board act as a shield board that shields the radiation of high frequency signals, so that characteristic deterioration can be avoided. However, it is necessary to keep the conductive member at a constant potential, and if the conductive member is not electrically connected to the leads or only one lead is connected, the high frequency signal It is not possible to obtain a sufficient shielding effect against radiation. Therefore, the conductive member needs to be electrically connected to two or more leads.
【００１２】 前記導電性部材としては、例えばモールド型集積回路の場合は、リードフレー ムのアイランド部を使用することができる。即ち、リードフレームのアイランド 部の下面側に半導体チップを固定すればよい。As the conductive member, for example, in the case of a mold type integrated circuit, an island portion of a lead frame can be used. That is, the semiconductor chip may be fixed to the lower surface side of the island portion of the lead frame.
【００１３】 なお、本考案に係る集積回路は、プリント板上においてこの集積回路の投影面 積の少なくとも１／３以上の面積を有し所定の電位に維持される導体パターンが 設けられた領域上に実装することが好ましい。これにより、半導体チップが導電 性部材とプリント板の導体パターンとの間に位置して、高周波信号の輻射に対す るシールド効果を確実に得ることができる。It should be noted that the integrated circuit according to the present invention is provided on a printed circuit board on a region provided with a conductor pattern having an area of at least ⅓ of the projected area of the integrated circuit and maintained at a predetermined potential. It is preferable to mount it on. As a result, the semiconductor chip is located between the conductive member and the conductor pattern of the printed board, and the shield effect against the radiation of the high frequency signal can be surely obtained.
【００１４】[0014]
次に、本考案の実施例について添付の図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the accompanying drawings.
【００１５】 図１は本考案の実施例に係る集積回路を示す断面図である。FIG. 1 is a sectional view showing an integrated circuit according to an embodiment of the present invention.
【００１６】 半導体チップ５は、リードフレームのアイランド部６の下側に搭載されている 。また、このアイランド部６に接続された吊りピン４は、リードとしてモールド 樹脂７の側部から導出され、その先端部がプリント板１に接触するように曲げ加 工されている。The semiconductor chip 5 is mounted below the island portion 6 of the lead frame. Further, the hanging pin 4 connected to the island portion 6 is led out from the side portion of the mold resin 7 as a lead, and is bent and processed so that the tip end portion thereof comes into contact with the printed board 1.
【００１７】 一方、プリント板１上には、所定の導体パターン２が設けられている。集積回 路は、吊りピン４を含む各リードの先端部がこれらの導体パターン２に半田３に より固定される。なお、吊りピン４は、集積回路の下方に配設され一定電位に保 持される導体パターン２に電気的に接続され、アイランド部６はこの導体パター ン２と同電位に保持される。On the other hand, a predetermined conductor pattern 2 is provided on the printed board 1. In the integrated circuit, the ends of the leads including the hanging pins 4 are fixed to these conductor patterns 2 with solder 3. The suspension pins 4 are electrically connected to the conductor pattern 2 disposed below the integrated circuit and kept at a constant potential, and the island portion 6 is kept at the same potential as the conductor pattern 2.
【００１８】 この吊りピン４に電気的に接続された導体パターン２は、通常、電源電位又は 接地電位に保持する。半導体チップ５とリードフレームのアイランド部６とが電 気的に接続されている場合には、この導体パターン２の電位は、半導体チップの 特性により決定する。例えば、半導体チップ５がＰ型サブストレートである場合 には、この導体パターン２を最低電位に保持することが好ましい。一方、半導体 チップ５がＮ型サブストレートである場合には、この導体パターン２を最高電位 に保持することが好ましい。The conductor pattern 2 electrically connected to the hanging pin 4 is normally held at the power supply potential or the ground potential. When the semiconductor chip 5 and the island portion 6 of the lead frame are electrically connected, the potential of the conductor pattern 2 is determined by the characteristics of the semiconductor chip. For example, when the semiconductor chip 5 is a P-type substrate, it is preferable to keep the conductor pattern 2 at the lowest potential. On the other hand, when the semiconductor chip 5 is an N-type substrate, it is preferable to keep the conductor pattern 2 at the highest potential.
【００１９】 一般的に、この種の集積回路に使用される半導体チップ５はＰ型サブストレー トであり、正の単一電源で駆動される。この場合には、吊りピン４に接続された 導体パターン２を接地電位に保持すればよい。Generally, the semiconductor chip 5 used in this kind of integrated circuit is a P-type substrate and is driven by a single positive power source. In this case, the conductor pattern 2 connected to the hanging pin 4 may be held at the ground potential.
【００２０】 なお、本実施例に係る集積回路が実装されるプリント板の集積回路投影面積の １／３以上が導体パターンであり、この導体パターンが、上述の如く、電源電位 又は接地電位等の一定電位に保持されていなければ、交流的に十分なシールド効 果を得ることが困難である。つまり、集積回路の下方に設けられた導体パターン ２の面積がこの集積回路の投影面積の１／３以上であれば、電源部及びグラウン ド部を考慮すると、交流的に接地とみなすことができる導体の面積は２／３以上 となり、大部分の領域が接地であるとみなすことができる。従って、リードフレ ームのアイランド部及びプリント板の導体パターンはシールド板として作用し、 高周波信号の輻射を遮蔽することができる。It should be noted that 1/3 or more of the projected area of the integrated circuit of the printed circuit board on which the integrated circuit according to the present embodiment is mounted is a conductor pattern, and this conductor pattern has a power source potential or a ground potential as described above. Unless it is held at a constant potential, it is difficult to obtain a sufficient AC shield effect. That is, if the area of the conductor pattern 2 provided below the integrated circuit is ⅓ or more of the projected area of this integrated circuit, it can be regarded as an AC ground in consideration of the power supply section and the ground section. The conductor has an area of 2/3 or more, and it can be considered that most of the area is grounded. Therefore, the island portion of the lead frame and the conductor pattern of the printed board act as a shield board and can shield the radiation of high frequency signals.
【００２１】 本実施例においては、リードフレームのアイランド部６と接続された吊りピン ４の本数が多いほど、また、これらの吊りピン４が相互に対向する位置に配置さ れて各ピンの幅が大きいほど、その遮蔽効果が大きい。In the present embodiment, the larger the number of the hanging pins 4 connected to the island portion 6 of the lead frame is, and the width of each pin is arranged at a position where the hanging pins 4 face each other. The larger is, the greater the shielding effect.
【００２２】 なお、上述の実施例においては、比較的チップの形状が大きい樹脂モールド型 集積回路の場合について説明したが、本考案は、ＱＦＰ型のみならず、ＤＩＰ及 びＳＯＰ等のデュアルインライン型パッケージの集積回路、高周波増幅器に用い られる高周波小信号トランジスタ及び高周波パワー増幅器に用いられる高周波大 信号トランジスタ等に適用することが可能であり、これらの集積回路についても 同様の効果を得ることができて、他の集積回路からのスプリアス輻射や、自身の チップからのスプリアス輻射を遮蔽することができる。In the above embodiment, the case of the resin mold type integrated circuit in which the shape of the chip is relatively large has been described, but the present invention is not limited to the QFP type but a dual in-line type such as DIP and SOP. It can be applied to package integrated circuits, high-frequency small-signal transistors used in high-frequency amplifiers, high-frequency large-signal transistors used in high-frequency power amplifiers, etc., and similar effects can be obtained for these integrated circuits. , It is possible to block spurious radiation from other integrated circuits and spurious radiation from its own chip.
【００２３】 また、リードフレームのアイランド部に半導体チップを搭載する集積回路にお いては、アイランド部に銀めっき等の導体めっきを施せば、高周波信号に対する 遮蔽効果をより一層高めることができる。これと同様に、半導体チップがセラミ ックキャップにより封止される集積回路についても、半導体チップの上方に配置 する導電性部材の表面を銀めっきすれば、高周波信号に対する遮蔽効果をより一 層高めることができる有効である。Further, in an integrated circuit in which a semiconductor chip is mounted on the island portion of the lead frame, conducting effect plating such as silver plating on the island portion can further enhance the shielding effect against high frequency signals. Similarly, for an integrated circuit in which a semiconductor chip is sealed with a ceramic cap, silver-plating the surface of a conductive member located above the semiconductor chip can further enhance the shielding effect against high frequency signals. You can be effective.
【００２４】[0024]
以上説明したように本考案においては、半導体チップの上方に導電性部材が配 置されており、この導電性部材は少なくとも２本のリードと電気的に接続されて いるから、前記導電性部材及びプリント板に設けられた導体パターンがシールド 板として作用し、高周波信号の輻射による特性の劣化を回避することができる。 As described above, in the present invention, the conductive member is arranged above the semiconductor chip, and the conductive member is electrically connected to at least two leads. The conductor pattern provided on the printed board acts as a shield board, and it is possible to avoid deterioration of characteristics due to radiation of high frequency signals.
【図面の簡単な説明】[Brief description of drawings]
【図１】本考案の実施例に係る集積回路を示す断面図で
ある。FIG. 1 is a sectional view showing an integrated circuit according to an embodiment of the present invention.
【図２】従来のモールド型集積回路を示す断面図であ
る。FIG. 2 is a sectional view showing a conventional mold type integrated circuit.
１，１１；プリント板 ２，１２；導体パターン ３，１３；半田 ４；吊りピン ５，１５；半導体チップ ６，１６；アイランド部 ７，１７；モールド樹脂 １８；ボンディングワイヤ 1, 11; printed board 2, 12; conductor pattern 3, 13; solder 4; suspension pin 5, 15; semiconductor chip 6, 16; island portion 7, 17; mold resin 18; bonding wire
Claims (2)
て、半導体チップと、この半導体チップの上方に配置さ
れた導電性部材と、この導電性部材及び前記半導体チッ
プを封止する封止部材と、この封止部材の側部から導出
されその先端部が前記プリント板に接合される複数本の
リードとを有し、前記導電性部材は前記複数本のリード
のうちの少なくとも２本と電気的に接続されていること
を特徴とする集積回路。1. An integrated circuit mounted on a printed circuit board, a semiconductor chip, a conductive member arranged above the semiconductor chip, and a sealing member for sealing the conductive member and the semiconductor chip. A plurality of leads, the leading ends of which are joined to the printed board and which are led out from the side portions of the sealing member, and the conductive member is electrically connected to at least two of the plurality of leads. An integrated circuit characterized by being connected.
ランド部であり、前記半導体チップはこのアイランド部
の下面に接合されていることを特徴とする請求項１に記
載の集積回路。2. The integrated circuit according to claim 1, wherein the conductive member is an island portion of a lead frame, and the semiconductor chip is bonded to a lower surface of the island portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP089910U JPH0541146U (en) | 1991-10-31 | 1991-10-31 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP089910U JPH0541146U (en) | 1991-10-31 | 1991-10-31 | Integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0541146U true JPH0541146U (en) | 1993-06-01 |
Family
ID=13983875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP089910U Pending JPH0541146U (en) | 1991-10-31 | 1991-10-31 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0541146U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5634346B2 (en) * | 1971-11-08 | 1981-08-10 | ||
| JPH0263195A (en) * | 1988-08-29 | 1990-03-02 | Mitsubishi Electric Corp | Electronic device |
-
1991
- 1991-10-31 JP JP089910U patent/JPH0541146U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5634346B2 (en) * | 1971-11-08 | 1981-08-10 | ||
| JPH0263195A (en) * | 1988-08-29 | 1990-03-02 | Mitsubishi Electric Corp | Electronic device |
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