JPH0541080A - Ferroelectric memory and method for driving this memory - Google Patents

Abstract

PURPOSE:To execute high-speed driving without deteriorating the polarization state of a ferroelectric memory cell. CONSTITUTION:A load capacitor 14 is connected electrically in series to the dielectric cell consisting of a pair of electrodes and the ferroelectric thin film crimped between these electrodes or the memory cell 12 consisting of a combination of this ferroelectric thin film cell and a semiconductor element. After the potential accumulated in this load capacity 14 is read out, a discharge circuit 15 immediately discharges the accumulated charge of the load capacity 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a ferroelectric memory using a ferroelectric capacitor element and a high speed / high S / N ratio in the ferroelectric memory.
The present invention relates to a driving method for reading.

[0002]

2. Description of the Related Art Generally, ferroelectric materials have a hysteresis characteristic, and it is known that data can be stored by utilizing this characteristic. FIG. 10 shows the hysteresis characteristic of the above-mentioned ferroelectric material. In the figure, the horizontal axis represents the electric field E and the vertical axis represents the polarization P.

Polarization state when the electric field is 0 (residual polarization P _r ).
Has two states of A and C as shown in the figure, and each position is made to correspond to "1" and "0" of the digital signal. That is, the state of A is defined as "1" and the state of C is defined as "0".
Of course, it goes without saying that the reverse is also possible. Data writing is performed as follows.

FIG. 11 shows the minimum and simplest configuration necessary for explaining the write operation, and this configuration will be referred to as a ferroelectric cell hereinafter. That is, the ferroelectric cell 100 has a structure in which the ferroelectric thin film 102 is sandwiched between the upper electrode 103 and the lower electrode 201.

Writing is performed by applying an electric field E _a, which is sufficiently larger than the coercive electric field E _c shown in FIG. 10, to the ferroelectric cell 100 having such a structure. That is, the polarization state is changed, and the polarization state of the ferroelectric thin film 102 after removal of the electric field E is A or C depending on the direction of the applied electric field.

Now, assume that the polarization state is A in FIG. When a positive electric field pulse Ea is applied to the ferroelectric thin film 102 in this state, the polarization state changes from A to B to C and settles at C. That is, if it corresponds to data,
This means that the data has been rewritten from "1" to "0". on the other hand,
If the polarization state is originally C, the polarization state changes from C to B to C, which is the same as the original state.

That is, the ferroelectric thin film 102 depends on the direction of application of the applied electric field E _a for writing, which of the electrodes 102 and 103 is set to high or low in FIG.
The polarization state can be uniquely determined, and the data "1" and "0" can be written without fail. The reading of data from such a ferroelectric cell 100 is performed as follows.

For example, "1" is added to the ferroelectric thin film 102.
It is assumed that a signal is written and the polarization state is A. At this time, if a positive read pulse E _s is applied,
The polarization shifts the polarization state from A to B to C (arrow b in FIG. 10). The slope of the AB section from the A state to the B state is large, and the change in the capacitance value C _f of the ferroelectric thin film 102 is large.

On the other hand, when the "0" signal is written in the ferroelectric thin film 102 and the polarization state is C, when the read pulse E _s is applied, the polarization state becomes C → B → Changes with C (arrow a in FIG. 10)
This BC section has a gentle slope, that is, the change in the capacitance value C _f is small.

Therefore, depending on the magnitude of the capacitance value C _f , the output is large in the case of data "1" and small in the case of data "0", so that "1" and "0" are set. It can be discriminated and read.

Utilizing the above-mentioned hysteresis characteristics, prior art patents for ferroelectric memories using a ferroelectric as an information recording medium are disclosed in, for example, JP-A-55-126905 and JP-A-57-117186. Publication, JP-A-59-2
15096, JP-A-59-215097,
Japanese Patent Laid-Open No. 1-158691 and the like are disclosed.

Writing and reading of information include optical ones and electrical ones. JP-A-1-158691
The publication discloses a circuit example of a ferroelectric memory that can be electrically written and read like a conventional IC memory.

FIG. 12A is a diagram showing a schematic circuit configuration example of the ferroelectric memory cell portion. Ferroelectric cell 1
00 is connected to an access transistor 104 composed of an enhanced NMOS transistor, and a drive line 105,
The word line 106 and the bit line 107 are connected to each other.

The ferroelectric cell 100 can be set so as to have a polarization state of data "1" indicated by the direction of arrow C, as shown in FIG.
On the contrary, the polarization state of data "0" indicated by the opposite direction of arrow C can be set. Reading from the memory circuit 108 is performed as follows.

First, when the read signal from the word line 106 is at a high potential (H level), the transistor 104
Is turned on, and the ferroelectric cell 100 is in a state in which the drive line 105 and the bit line 107 are electrically connected.

In this conductive state, the bit line 107 is set to 0V,
The drive line 105 is set to a high (H) level (≧ E _s ). At this time, if the polarization state is the state of the data “1” indicated by the downward arrow, that is, the A state in FIG. 10, the polarization moves in the AB section from the A state to the B state and is driven. When the line 105 drops to a low potential (low (L) level) 0 V, the polarization changes from the B state to the C state. At this time,
A current i ₁ is applied to the bit line 107 through the transistor 104.
Flows.

On the contrary, when the written data is "0", that is, when the polarization state is C in FIG. 10, the polarization state is changed to C state by the same operation as described above. From the B state to the C state and then to the C state, and the corresponding current i ₂ flows through the bit line 107.

At this time, since a current is generated in proportion to the amount of change in polarization, the relationship of i ₁ > i ₂ (1) holds. Therefore, by comparing the output current with a certain reference signal, it is possible to determine whether the written data is "1" or "0".

Regarding the discrimination operation of the currents i ₁ and i ₂ ,
This will be described with reference to FIG. The ferroelectric cell 100 and the semiconductor switch 104 shown in FIG. 12 constitute one cell. In order to drive and control this cell 108, peripheral circuits such as a decoder 109, a driver 110 and a control circuit 111 are arranged. It is connected. Furthermore, the sense amplifier 11
2 are provided, and the bit line 1 is provided in the sense amplifier 112.
07 and the reference signal line 113 are connected.

The reference signal is provided by the reference signal line 113. In the well-known DRAM, "dummy cells" are arranged, and from the "dummy cells",
Currents i ₁ and i ₂ obtained in the case of data “1” and “0”
A current having an intermediate magnitude is generated and used as a reference signal.

In Japanese Patent Laid-Open No. 1-158691, as shown in FIG. 14, the same ferroelectric cell 1 is used.
00a and 100b are used as a pair, and one ferroelectric cell, for example, 100a is used as a data recording cell, and the other ferroelectric cell 100b is used as a reference cell in combination. In addition, the ferroelectric cell 100
Data is always recorded in a and 100b in a complementary manner. For example, when "1" is recorded in the ferroelectric cell 100a, "0" is recorded in the ferroelectric cell 100b. Has been done.

In such a state, the transistor 1
The word line 106 connected to the gates 04a and 104b is set to the H level to turn on the transistors 104a and 10b.
Turn on 4b. Next, the bit lines 107a, 10
7b is changed to 0V, and the drive line 105 is changed from H level to L level. At that time, for example, data is transferred to the ferroelectric cell 100a.
If the data "1" is recorded and the ferroelectric cell 100b is recorded with "0", the bit line 107
a shows the hysteresis curve shown in FIG.
A current i ₁ flows due to a change in the polarization state that changes from the state to the C state (arrow b), and the bit line 107b is
The current i ₂ flows from the C state to the B state through the change of the C state (arrow a). These currents i ₁ and i ₂ are compared and amplified by the sense amplifier 112.

A well-known DRA is used as the sense amplifier 112.
In the case of a flip-flop type sense amplifier used in M or the like, the currents i ₁ and i ₂ flow into the sense amplifier in the form of being changed to the potential by the capacitive component of the bit line and the like and are comparatively amplified. Further, writing of data is performed as described below in the same manner as reading.

The word line 106 is set to the H level, the transistors 104a and 104b are turned on, and the drive line 10 is turned on.
5 or one of the bit lines 107a and 107b is set to the H level and the other is set to the L level.

At this time, if the drive line 105 is set to the H level and the bit lines 107a and 107b are set to the L level, the polarization state is set to the state of the data "1" indicated by the downward arrow, In the opposite case, the polarization state is set to the state of data "0".

However, in the conventional method, it is unclear how to sense the charges generated from the ferroelectric cell, but since the data is read by the sense amplifier like the DRAM, It is obvious that the load capacitance is connected to the ferroelectric cell, converted into the potential, and the data signal and the reference signal are compared and amplified. With such a configuration, the following problems occur.

FIG. 15A is a diagram showing a circuit configuration for explaining a read / write (R / W) operation by a conventional method. The reading is performed as follows as described above. The transfer gate 104 connected to the sense amplifier 112 is turned on, and then the ferroelectric cell 10 is connected.
The transfer gate 114 connected to 0 is turned on. In this state, the drive line 105 is set high. Those timings are shown in FIG.

[0028]

With such a circuit configuration, a problem occurs when the drive line 105 is dropped from high to low. FIG. 12B is a diagram showing an equivalent circuit at that time. The charge due to the polarization inversion accompanying the read operation to the ferroelectric cell 100 is accumulated in the load capacitor 115, and the potential thereof is sensed by the sense amplifier (SA) 112.
The reference signal V _ref is compared and amplified. In this case, the potential of the load capacitance 115 acts in the direction of depolarizing the inverted polarization, as can be seen from FIG. 12B, so that the polarization state becomes unstable. As a result,
Instead of the A and C states shown in 0, the state becomes an intermediate state.

On the contrary, the transfer gate 114 is OF
If the drive line 105 is set to low after F (indicated by a dotted line in FIG. 15B), the above problem does not occur, but charges accumulated in the ferroelectric film 102 (described later) Is not discharged. Therefore, the transfer gate 114
It has to wait for a spontaneous discharge through the battery and other components.

Although this occurs regardless of the timing of the drive signal φ ₁ , the electric charge accumulated in the load capacitance 115 cannot be discharged by the conventional structure. This also requires waiting for the discharge due to spontaneous discharge, which is stable R as well as high-speed driving.
/ W operation cannot be expected. Even if the drive signal φ _{1 is set} to high and a certain voltage V _a is applied in order to perform the next R / W operation in the state where the charge is stored in the ferroelectric cell 100 or the load capacitance 115, the ferroelectric cell The effective voltage applied to 100 does not depend on V _a but differs by the amount of charges accumulated in the capacitor, and stable R / W operation cannot be performed. Therefore, the ferroelectric cell 100 and the load capacitance 1
It is necessary to surely discharge the charge accumulated in 15 at high speed. The present invention has been made in view of the above points, and an object of the present invention is to enable high-speed driving without deteriorating the polarization state of a ferroelectric memory cell.

[0031]

In order to achieve the above object, the ferroelectric memory according to the present invention is a ferroelectric cell comprising a pair of electrodes and a ferroelectric thin film sandwiched between these electrodes. Alternatively, a memory cell including a combination of the ferroelectric cell and a semiconductor element, a load capacitance electrically connected in series to the memory cell, and the load capacitance immediately after reading the potential accumulated in the load capacitance. And a discharge circuit for discharging the accumulated electric charge.

Here, the load capacitance may be formed by using a part of a portion forming a semiconductor such as a gate oxide film capacitance of a MOS transistor or a diffusion layer capacitance in a semiconductor element. It should be configured by using the capacitance such as the gate oxide film capacitance of the MOS transistor, the diffusion layer capacitance in the semiconductor element, or the parasitic capacitance of the data line or the like, which is inevitably formed by configuring the semiconductor. You can Furthermore, the load capacitance can be configured by using a ferroelectric thin film and a thin film having a high dielectric constant, such as a Ta ₂ O ₅ film or a Si ₃ N ₄ film.

In the ferroelectric memory driving method according to the present invention, in the ferroelectric memory as described above, the charge accumulated in the memory cell and the information in the memory cell are read to read the load. It is characterized in that the electric charge accumulated in the capacitance is discharged in the discharge circuit before the discharge time constant of the load capacitance.

Alternatively, in the ferroelectric memory as described above, the charge accumulated in the load capacitance by reading the information of the memory cell is discharged in the discharge circuit and then accumulated in the memory cell. It is characterized by discharging the generated electric charge.

[0035]

That is, in the ferroelectric memory and the method of driving the same according to the present invention, the electric charge accumulated in the load capacitance is read out by the discharge circuit, the accumulated charge of the load capacitance is immediately discharged, and then the accumulated charge is accumulated in the memory cell. By discharging the stored electric charge, the electric charge accumulated in the ferroelectric cell and the load capacitance can be discharged at high speed and reliably, so that high speed driving is possible without deteriorating the polarization state of the ferroelectric memory cell. can do.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before explaining the embodiments of the present invention, the principle of the present invention will be explained first in order to help understanding of the present invention.

As shown in FIG. 1A, the ferroelectric memory according to the present invention includes a memory cell 12 including at least a ferroelectric cell connected to a voltage supply line 11 and a data cell.
Data read line 13 and its data read line 1
3 and a discharge circuit 15 electrically connected in parallel to the load capacitance 14. The basic operation is performed by discharging the electric charge accumulated in the memory cell 12 and the load capacitance 14 by the discharge circuit 15.

The discharge circuit 15 can be formed by, for example, a MOS transistor. Figure 1 (A)
Is an example of using a MOS transistor as a transfer gate, and the discharge operation is performed by turning on or off the gate of this MOS transistor.
Of course, when the MOS transistor is turned on, the charge accumulated in the memory cell 12 and the load capacitance 14 is
It is discharged to GND via the S transistor. The discharge timing is set, for example, as shown in the timing chart of FIG.

That is, when reading information from the memory cell 12, as shown by the waveform φ ₁ , the voltage supply line 11
Is made high (for example, 5 V), and the charge generated by the memory cell 12 is accumulated in the load capacitor 14. Then, the potential (waveform V _m ) of the data read line 13 which is increased by being accumulated is detected. Then, as shown by the waveform φ ₂ ,
The discharge circuit 15 is turned on, and the electric charge accumulated in the load capacitance 14 is discharged to GND.

At this time, the timing for turning on the discharge circuit 15 must be at least before the timing for turning the voltage supply line 11 low. Further, τ = R _ON C _t where C _t = C _L + C _O C _L : capacitance of the load capacitance 14 C _o : linear capacitance without polarization reversal of the ferroelectric thin film R _ON : discharge circuit ON It must be before the discharge time constant τ defined by the resistance. That is, t _d in FIG.

[0041]

[Equation 1] Must be This is because after that, the load capacitance 14 is not sufficiently discharged and the conventional problems cannot be solved.

By connecting the discharge circuit 15 to the data read line 13 in this manner, high-speed driving can be performed without degrading the polarization state of the memory cell 12, which has been a problem in the prior art. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a sectional view showing the structure of a ferroelectric memory cell according to the first embodiment of the present invention. That is, the memory cell 12 is formed by the discharge circuit 1 by the well-known IC manufacturing technique.
Substrate 1 on which MOS transistor 16 forming 5 is formed
Lower electrode 18, ferroelectric thin film 19, and upper electrode 20 on 7
It has a structure in which layers are sequentially laminated.

Here, the lower electrode 18 is, for example, an O.V. The ferroelectric thin film 19 is platinum having a thickness of 2 μm, and the ferroelectric thin film 19 has a thickness of 0.3 μm and is made of Pb (Zr _0.46 Ti _0.55 ) O ₃ (hereinafter PZ).
(Abbreviated as T), the upper electrode 20 is platinum having a thickness of 0.2 μm. Reference numeral 21 in FIG. 3 is LOCOS, 2
2 is the gate of the MOS transistor 16 and 23 is BPSG
/ LTO, 24 is SiO ₂ , and 25 is Al wiring. The memory cell 12 having such a structure is manufactured as follows.

That is, a lower electrode 18 made of platinum (Pt) having a thickness of 0.2 μm is formed by Rf sputtering on the substrate 17 on which the MOS transistor 16 is formed, and the photolithography process well known in IC manufacturing is used. Pattern appropriately. After that, a ferroelectric thin film 19 made of PZT is formed by a sol-gel method (described later), and subsequently, an upper electrode 20 made of platinum is formed in the same manner as the lower electrode 18. The ferroelectric thin film 19 made of PZT is produced by the sol-gel method of PZT to which a small amount of niobium (Mb) is added, as shown in the flowchart of FIG.

That is, in the first step, Pb: dietokin lead / Pb (OC ₂ H ₂ ) 0.500 mol and Zr: tetra-n-ptoxyzirconium / Zr (OC ₄ Ha)
₄ 0.235 mol, Ti: tetra n-ptoxy titanium / Nb (OC ₄ Ha) ₄ 0.265 mol, and Nb: penta n-ptoxy niobium / Nb (OC ₄ Ha) ₅ 0.01
Solvent: n-butyl alcohol (1) + i-propyl alcohol-so that the concentration becomes 20 wt% at a ratio of 0 mol.
Solution (2) to make a coating solution (step S
1). At this time, the coating solution is partially hydrolyzed (step S2). Next, the above-mentioned coating solution is supplied to a spin coater to coat the substrate at 1500 rpm,
A coating film is formed (step S3).

Then, it is left to stand for 3 hours in an atmosphere of a temperature of 25 ° C. and a humidity of 65% RH to be dried and hydrolyzed (step S4). Next, the substrate is placed in a heat treatment tank and
The temperature of the substrate is raised to 60 ° C., the atmosphere of the substrate is reduced to 0.1 atm and held for 60 minutes, and the alcohol produced by this vacuum treatment (ethyl alcohol, n- (Butyl alcohol), excess water, residual organic matter, etc. are completely removed (step S5).

Further, after introducing a predetermined gas into the processing tank and raising the pressure to 1 atm (step S6), the atmosphere is heated to 550 ° C. at a heating rate of 5 ° C./min and held for 60 minutes. Sintering is performed (step S7) and then gradually cooled to room temperature (step S8) to form a PZT thin film. FIG. 4A is a diagram showing a circuit configuration of the ferroelectric memory thus manufactured.

That is, the load capacitance 14 is connected in series to the ferroelectric cell 12, and the N-type MOS transistor 16 is connected in parallel with the load capacitance 14. The potential of the load capacitance 14 is applied to one input terminal of a sense amplifier 27 via a transfer gate 26 composed of an N-type MOS transistor. In addition, this sense amplifier 2
The reference signal V _ref is input to the other input terminal of 7.

A drive circuit 27 is connected to the other terminal of the ferroelectric cell 12 and applies a control signal φ ₁ to the ferroelectric cell 12 in response to a drive signal from a control circuit (not shown).
The gate of the MOS transistor 16 is connected to a delay circuit 29 that delays the drive signal or the control signal from the read / write system 28 to generate a control signal φ ₂ . Further, the control signal φ ₃ is applied from the control circuit (not shown) to the gate of the MOS transistor forming the transfer gate 26. In reality, a decoder or the like for selecting the ferroelectric cell 12 or the like is also required, but illustration and description thereof are omitted here.
Next, the operation will be described. In the memory having the above structure, reading is performed as shown in the timing chart of FIG.

First, in order to extract the charge accumulated in the signal read line 13, the gate of the MOS transistor 16 is set to high ((1) portion of waveform φ _{2 in} the figure). By this operation, the signal read line 13 is initialized. Next, the read voltage V _a (waveform φ ₁ ) is applied to the ferroelectric cell 12 by the drive circuit 27. Then, as shown in the waveform φ ₃ , the transfer gate 26 connected to the sense amplifier 27 is turned on, and then the OF
Let it be F.

Then, the MOS transistor 16 is turned on as shown in the section (2) of the waveform φ ₂ at the timing of turning it off. At this time, as mentioned above,
The timing for turning on the MOS transistor 16 is 0 V for the read voltage V _a applied to the ferroelectric cell 12.
It is necessary that the time constant τ is at least equal to or longer than the time when the value is lowered to, that is, as shown in Equation 1.

In this way, before the electrode on the drive circuit 27 side of the ferroelectric cell 12 falls to the low (L) level,
Since the charge is discharged via the MOS transistor 16, the potential of the load capacitor 14 is lowered, and the polarization of the ferroelectric cell 12 is not depolarized. Moreover, as in the timing chart shown in FIG. 4B, since the processing is performed in the same operation as the read operation, the operation can be performed at high speed.

FIG. 5A is a diagram showing the configuration of the second embodiment of the present invention. The second embodiment is shown in FIG.
In the ferroelectric memory having the structure shown in FIG. 1, the transfer gate 30 is provided in the ferroelectric cell 11.
The gate 30 functions as a switch that electrically separates the cell 12 from other cells, and is a practical configuration used in an actual device or the like.

In the case of this embodiment, the control signal φ ₄ of the transfer gate 30 is timed with the read voltage V _a as shown in the timing chart of FIG. 5B. In other words, since the gate 30 is merely a switch instead of an electrode line, it is sufficient that it is turned on so as to include the time when V _a is applied in the control signal φ ₁ , and the strict timing is required. No control required. Other operations and their effects are similar to those of the first embodiment described above.

FIG. 6 is a diagram showing a flip-flop (FF) type sense amplifier as a configuration example of the sense amplifier 27. This sense amplifier 27 is M
Comprised of OS transistors, 31-33 are PMO
S and 34 to 38 are formed by NMOS. Of these MOS transistors, transistors 31, 36,
Reference numerals 37 and 38 denote transfer gates for controlling input / output with data or a power supply, GND, etc. Now, when the MOS transistor is formed in this way, as shown in FIG. 7, it has capacitance components (C _GD , G _GS , G _DS ) everywhere. Here, the capacitance formed between the data lines 39 and 40 and the substrate is expressed as C _m .

Furthermore, if the data lines 39 and 40 are also formed on the semiconductor, the distance d between the substrate and the line cannot be increased so much, and the capacitance C _l is inevitably formed. The value depends on the relative permittivity ε _r of the material forming the distance d and the area S of the line, and C _l = ε _o ε _r (S / d) ε _o : the permittivity of the vacuum. Since C _m and C _l are formed in parallel, the capacitance connected to the data line is expressed by the following equation (2).

[0058]

[Equation 2] This C _s is a component that is always generated when a semiconductor element is formed, and its value can be adjusted, but it cannot be lost.

Therefore, as a third embodiment of the present invention, a load capacitance (C _L ) 14 as shown in FIG.
It will be formed with this C _s . The adjustment of C _s may be performed by controlling the magnitude of C _m or C _l .

The value of C _L is determined from the relationship between the memory cell 12 and the FF type sense amplifier 27. When C _{L is represented} by C _m or C _l , there are the following two methods.

That is, on the one hand, one data read line or the capacity inevitably formed by forming the FF type sense amplifier 27 is taken as C _L, and the memory cell 12 and the FF type are adapted to it. This is a method of designing the sense amplifier 27, and the other is a method of matching C _L by adapting it to the memory cell 12 and the FF type sense amplifier 27. The effect operation is the same in both cases, and the effect of the present invention can be realized. In the former method, since a capacity portion that is necessarily formed is appropriately used, a high-density device can be manufactured. The latter will be described in detail in the fourth embodiment below.

In FIG. 1A, the load capacitance 14 is
Usually, the capacitance value is set to be equal to or larger than that of the memory cell ( _CF ) 12. When the ferroelectric film, for example, PZT, is used as the memory cell ( _CF ) 12, it depends on the composition, for example, □ 10 μm × t0.2 to 0.3.
It has a size of μm and a capacitance of several pF. For this value,
When _CL is designed, the gate capacitance (order of [fF]) of the MOS normally forming the line of the device size or the sense amplifier 27 is insufficient, and it is artificially artificial. C _L needs to be formed. Therefore, the diffusion layer capacitance of the semiconductor device, MOS of gate - by using preparative capacity etc.'ll form a C _L. Here, it is assumed that C _L is formed by utilizing the gate capacitance of MOS. This allows
Depending on the MOS fabrication conditions, several hundred μm × several hundred
With a gate area of μm, a capacitance value of several pF can be given.

By adjusting this size, C _L having a size suitable for the memory cell 12 or the FF type sense amplifier 27 is formed. By doing so, the memory of the present invention can be realized by using the conventional semiconductor process technology.

Further, when the C _L is formed by, for example, a data read line or the like, the size of C _L needs to be about several pF as described above, so that the line area becomes large. For example, in the case of the normal configuration as shown in FIG. 2, the relative permittivity of the SiO ₂ film 24 between the line 25 and the substrate 17 is about 4. Therefore, if the SiO ₂ film thickness is 0.5 μm and the line width is 2 μm, it is 1 pF. In order to form the capacitor, a length of 7,000 μm is required from the formula (1), which is impractical in device fabrication. Therefore, as a fifth embodiment of the present invention, it can be formed of a material having a larger ε _r than the SiO ₂ film.

Ε _r = 22 for Ta ₂ O _{3 and} ε _r = 8-9 for Si ₃ N ₄ , which is about 5 times larger for Ta ₂ O _{3 and} about 2 times larger for Si ₃ N ₄ than SiO _2. Even under the same conditions as above, the required length is shortened by the reciprocal of the ratio, and the capacitive element can be formed with high density. Next, a sixth embodiment of the present invention will be described with reference to FIGS.

When an electric field is applied to the ferroelectric cell, electric charge is accumulated at the same time as polarization inversion because it also has a normal linear capacitance component. Figure 8 is a strong but well known as an electrical equivalent circuit of the dielectric film, current source I _s and a linear capacitor C _o representing the generation of charges due to polarization inversion, and the DC resistance component R It consists of parallel connections. This linear capacity C
Charge is accumulated in _o . In this state, next, when an electric field E _a is applied to this ferroelectric film, E _a is no longer effectively applied to the ferroelectric film due to the anti-electric field determined by the accumulated charges, and stable writing / reading operation is performed. I can't do it.

Therefore, the accumulated charge is discharged. In the configuration shown in FIG. 5, in addition to the discharge circuit described above being performed at the above timing, the control signal waveform φ _{1 in} FIG.
As shown in, at the timing of dropping the drive line 11 to the low level, the discharge circuit discharges the electric charge of the load capacitance 14,
It is assumed that the potential of the load capacitance 14 has dropped to the low level.
By doing so, the potentials at both ends of the ferroelectric cell are both at a low level, so that the polarization of the ferroelectric film is not depolarized,
Further, the accumulated charge of the ferroelectric cell can be discharged, and stable writing and reading can be performed.

[0068]

As described above in detail, by connecting the discharge circuit to the data read line, it is possible to drive at high speed without degrading the polarization state of the ferroelectric memory cell, which has been a problem in the past. Becomes

[Brief description of drawings]

FIG. 1A is a circuit configuration diagram of a ferroelectric memory for explaining the principle of the present invention, and FIG. 1B is a timing chart for explaining the operation in the circuit configuration of FIG. is there.

FIG. 2 is a sectional view showing the structure of a ferroelectric memory cell according to the first embodiment of the present invention.

FIG. 3 is a flow chart for explaining a method for manufacturing a ferroelectric thin film.

FIG. 4A is a diagram showing a circuit configuration of a ferroelectric memory of the first embodiment, and FIG. 4B is a timing chart for explaining the operation of the circuit of FIG.

5A is a diagram showing a circuit configuration of a ferroelectric memory according to a second embodiment, and FIG. 5B is a timing chart for explaining the operation of the circuit of FIG.

FIG. 6 is a circuit configuration diagram of a sense amplifier according to a third embodiment.

FIG. 7 is a diagram for explaining a capacitance component of each MOS transistor.

FIG. 8 is a diagram showing an electrical equivalent circuit of a ferroelectric film in a sixth example.

FIG. 9 is a timing chart for explaining the operation of the sixth embodiment.

FIG. 10 is a diagram showing a hysteresis characteristic of a ferroelectric material.

FIG. 11 is a cross-sectional view showing the structure of a ferroelectric cell.

FIG. 12A is a schematic circuit diagram of a conventional ferroelectric memory cell, and FIG. 12B is a diagram showing the drive line dropped from high to low in the circuit configuration of FIG. It is a figure which shows the equivalent circuit at the time.

FIG. 13 is a circuit configuration diagram of a conventional ferroelectric memory circuit.

FIG. 14 is a circuit configuration diagram of a conventional ferroelectric memory.

FIG. 15A is a circuit configuration diagram of a conventional ferroelectric memory for explaining a conventional problem, and FIG. 15B is a circuit diagram of FIG.
3 is a timing chart of the circuit of FIG.

[Explanation of symbols]

11 ... Voltage supply line (driving line), 12 ... Memory cell ( _CF ), 13 ... Data reading line, 14 ... Load capacitance ( _CL ), 15 ... Discharge circuit, 16 ... MOS transistor.

Claims (6)

[Claims] 1. A ferroelectric cell comprising a pair of electrodes and a ferroelectric thin film sandwiched between the electrodes, or a memory cell comprising a combination of the ferroelectric cell and a semiconductor element, and the memory cell. A ferroelectric memory, comprising: a load capacitance electrically connected in series to the load capacitance; and a discharge circuit that immediately discharges the accumulated charge of the load capacitance after reading the potential stored in the load capacitance. .. 2. The ferroelectric memory according to claim 1, wherein the load capacitance is formed by using a part of a portion forming a semiconductor. 3. The ferroelectric memory according to claim 1, wherein the load capacitance is configured by utilizing a capacitance component that is inevitably formed by configuring a semiconductor. 4. The ferroelectric memory according to claim 1, wherein the load capacitance is formed by using one of a ferroelectric thin film and a thin film having a high dielectric constant. 5. A ferroelectric cell comprising a pair of electrodes and a ferroelectric thin film sandwiched between the electrodes, or a memory cell comprising a combination of the ferroelectric cell and a semiconductor element, and the memory cell. A ferroelectric memory comprising: a load capacitance electrically connected in series to and a discharge circuit for immediately discharging a stored charge of the load capacitance after reading a potential accumulated in the load capacitance. The electric charge accumulated in the cell and the electric charge accumulated in the load capacitance by reading the information of the memory cell are discharged in the discharge circuit before the discharge time constant of the load capacitance. Driving method for ferroelectric memory. 6. A ferroelectric cell comprising a pair of electrodes and a ferroelectric thin film sandwiched between these electrodes, or a memory cell comprising a combination of the ferroelectric cell and a semiconductor element, and the memory cell. A ferroelectric memory comprising: a load capacitance electrically connected in series to and a discharge circuit for immediately discharging a stored charge of the load capacitance after reading a potential accumulated in the load capacitance. After discharging the charge accumulated in the load capacitance by reading the cell information, in the discharge circuit,
A method of driving a ferroelectric memory, comprising discharging the electric charge accumulated in the memory cell.