JPH0540613Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a horizontal periodic circuit used in color television receivers and the like.

[Technical background of the invention]

In recent years, systems such as television receivers have been considered in which video signal processing and horizontal/vertical synchronization processing circuits are converted into digital signals. FIG. 3 shows an example of a digitized horizontal periodic circuit. The operation of the horizontal synchronization circuit shown in FIG. 3 will be briefly explained as follows.

Composite video signal is A/D converter 1
The signal is converted into a digital composite video signal, and is supplied to a video signal processing circuit 2 and the like, and is also guided to a synchronization separation circuit 3. The synchronization separation circuit 3 extracts only the synchronization signal from the composite video signal and supplies it to the phase comparator 4 at the subsequent stage.
The operation of the phase comparator 4 is roughly as follows. For example, the dynamic range of A/D converter 1 is
If it is 2VP-P, A/D converter 1
In the standard NTSC case, the composite video signal supplied to the NTSC is set so that the amplitude from the white level of the picture to the leading edge of the synchronization signal is 2VP-P. In that case, the synchronization signal amplitude is approximately 0.57VP-P.

If the leading edge of the synchronization signal is placed at the lower limit of the dynamic range of the A/D converter 1 and the A/D converter 1 is quantized, for example, at 8 bits, the leading edge of the synchronizing signal will be placed at the lower limit of the dynamic range of the A/D converter 1. If expressed as a signal level, it can be expressed in hexadecimal.
It will be 00H (0 in decimal), and the 100% white part of the pattern will be FFH (225 in decimal). Also, the pedestal part is approximately 49H ((73 in decimal) from the relational expression 225 x 0.57/2.0 = 73.
8-bit data is output from the A/D converter 1 and supplied to the synchronous separation circuit 3.

The synchronization separation circuit 3 checks the input digital signal. As explained above, the data range that the synchronization signal can take is generally between 0 and 49H, and the synchronization separation level is set within this range. For example, let's set it to 24H, which is almost the middle value, and if the input data is less than this value, it will output "0", and if it is more than that, it will output "1" (for example
5V), the synchronization signal can be separated. The phase comparator 4 is also supplied with the output of the variable frequency divider 6 at the subsequent stage, and generates an output according to the frequency difference between the two.

As the phase comparator 4, for example, US Pat.
NAND as described in specification 3610954
A combination of circuits can be used. The phase comparator described in this US patent has an input terminal for a reference panel and a comparison pulse, and two output terminals that indicate the magnitude of the comparison result. For example, when the phases of both inputs match, both outputs are "0". ”, and operates so that one of the outputs becomes “1” depending on whether the comparison pulse is ahead or behind the reference pulse. Note that if a phase comparator 4 with such a configuration is used, there will be two output terminals, but the first
In the figure, it is represented by a single line. The output signal from the phase comparator 4 is then filtered by a filter 5 to control the division ratio control terminal of the variable frequency divider 6 to match the frequency of the synchronizing signal and the frequency of the output signal of the variable frequency divider 6. , a so-called periodic state is created.

A reference signal to the variable frequency divider 6 is supplied from a clock generator 7 which oscillates at the natural frequency of a crystal oscillator 8. This clock signal is also used as a sampling clock for the A/D converter 1 or as a clock signal for other circuits such as the video signal processing circuit 2.

The output signal of the variable frequency divider 6 synchronized with the synchronization signal is sent to the delay circuit 9 and the phase comparator 1 in the subsequent stage.
Connected to 2. The delay circuit 9 is a variable frequency divider 6
This is provided to absorb the phase jitter of the output signal. The phase comparator 12 compares the phase of the output signal of the variable frequency divider 6 and the AFC pulse supplied from the horizontal output circuit 11, and the comparison result is led to the filter circuit 13 where it is filtered and output to the delay circuit 9. It controls the delay time.

The signal whose phase jitter has been absorbed by the delay circuit 9 is guided to the horizontal drive circuit 10 to form a horizontal drive pulse for driving the horizontal output circuit 11.

In the circuit configured as described above, when a composite video signal is supplied, the horizontal scanning period (hereinafter referred to as _TH ) of the horizontal output circuit 11 becomes the period of the synchronizing signal. In other words, the phase comparator 12
The AFC taken out from the horizontal output circuit 11 by
The phase of the pulse and the output pulse of the variable frequency divider 6 are made to match, and the phase of the output pulse of the variable frequency divider 6 and the output pulse of the synchronous separation circuit 3 are made to match by the phase comparator 4. . This situation is shown in Fig. 2-1-a and b.

If there is no composite video signal, the A/
A composite video signal is no longer input to the input of the D converter 1, and only a predetermined DC potential is supplied. In the A/D converter 1, in order to match the input dynamic range as described above, when a composite video signal is present, the leading end of the synchronizing signal is set to the lower end of the dynamic range. When adjusting the dynamic range in this way, a peak clamp circuit (not shown) is generally used. By the way, when there is no signal and only a DC level is supplied, the operation of this peak clamp circuit sets this DC potential at the lower end of the input dynamic range of the A/D converter 1. In this case, it can be seen that the output digital signal level of the A/D converter 1 is approximately 00H.
Therefore, when the output signal of the A/D converter 1 is approximately 00H due to the operation of the synchronous separation circuit 3, the second
As shown in FIG. 2-a, the synchronization signal is no longer output from the synchronization separation circuit 3. In this case, phase comparator 4
The phase comparison operation increases the division ratio of the variable frequency divider 6 and lowers the frequency. If there is no synchronization signal, the period of the synchronization signal will appear to be infinite, and even if the frequency division ratio of the variable frequency divider 6 is increased to the limit value, the phases will not match, and the frequency division ratio will not exceed this limit value. is maintained.

As a result, T _H becomes wider as shown in FIG. 2-2-b.

When T _H becomes wider as described above, in other words, when the horizontal scanning frequency (hereinafter referred to as _H ) becomes lower, the following problems arise.

[Problems with background technology]

In the case of a television receiver, etc., the synchronization signal may be lost when selecting a channel that is not being transmitted, or when a signal is not being supplied to the composite video signal input terminal for external video equipment. . In such a case, if _H decreases as described above, not only will the magnetostrictive vibration of the flyback transformer used in the horizontal output circuit become audible and harsh, but also the flyback transformer will decrease as T _H decreases. This has the disadvantage that the resonance energy of the image tube increases, the peak value of the flyback pulse increases, and damage to the high voltage generation circuit or the picture tube increases.

[Purpose of invention]

An object of the present invention is to provide a horizontal synchronization circuit in which the above-mentioned problems are eliminated.

[Summary of the idea]

This invention eliminates the composite video signal,
If there is no horizontal synchronization signal, this is automatically detected and the horizontal scanning frequency _H is forcibly increased to eliminate the whine of the flyback transformer and suppress the peak value of the flyback pulse. It is something.

[Example of idea]

FIG. 1 shows an embodiment of a horizontal synchronization circuit according to the present invention. In Figure 1, switch FET 1 is connected to a specific bit part of the output signal of A/D converter 1.
4 is inserted, and the output of the synchronous separation circuit 3 is connected to the gate electrode of the FET 14 via an integrating circuit 15, which is different from the configuration of the conventional example shown in FIG.

The switching operation by the FET 14 will be explained below.
First, when there is a composite video signal, the synchronization separation circuit 3 obtains a synchronization signal as shown in FIG. 1-a. This synchronizing signal is smoothed by an integrating circuit 15 consisting of a resistor R2 and a capacitor C1, and a DC voltage as shown in FIG. 1-C is supplied to the gate of the FET 14. This voltage is FET14
is at a sufficient level to make FET1 conductive.
4 is turned on, and the digital signal from the A/D converter 1 can be supplied to the synchronous separation circuit 3 as is.
via resistor R1 on the source electrode side of FET14.
Although the AFC pulse is being supplied, when the FET 14 is in the on state, the value of R1 is made sufficiently large relative to the output impedance of the A/D converter to eliminate any influence on the digital signal.

Next, as shown in FIG. 2-2-a, the synchronous separation circuit 3
When the output of
FET14 is cut off. In this case, FET1
4, the signal line of a specific bit among the outputs of the A/D converter 1 is no longer connected to the synchronous separation circuit 3. At this time, the AFC pulse is input to the corresponding bit of the composite video signal input terminal of the synchronization separation circuit 3 via the resistor R1. A/
Since the composite video signal is not input to the D converter 1, most of the bits of the digital composite signal are at the "0" level, and when the AFC pulse is inserted only to the specific bits mentioned above, the synchronous separation circuit 3 The output becomes as shown in FIG. 2, 3-a. The specific bit here refers to a relatively high-order bit such that the input level to the synchronization separation circuit changes beyond the separation level by changing the logic value of the bit.
In other words, any relatively high-order bit can switch from a level higher than the separation level to a level lower than the separation level of the sync separation circuit when the bit becomes ``1'' or ``0''. However, the same effect can be obtained, and there is no particular limitation.

FIG. 2 3-b shows the AFC pulse at this time. The output of the synchronous separation circuit shown in FIG. 3-a appears somewhat delayed from the AFC pulse due to the delay time of the circuit or element. The phase comparator 4 operates by determining that the period during which the output of the synchronization separation circuit 3 is at "L" level is a synchronization signal, so in this case, the phase of the synchronization signal is ahead of the AFC pulse, and the variable frequency divider 6 operates to reduce the frequency division ratio of , increasing _H. f _H increases until it reaches the limit of the division ratio of the variable frequency divider, at which point it stabilizes.

Note that the integration circuit 15 integrates the synchronous separated output shown in FIG. 2 2-a when there is a signal, but since the positive period of this synchronous separated output is longer than the negative period, the integral output 2-c is compared. FET1 is at a high level
4 is turned on, but when there is no signal, the AFC pulse supplied to the synchronization separation circuit 3 is integrated.
Since the AFC pulse has a longer negative period than its positive period, the output of the integrator circuit 15, as shown in Figure 2-3-c, is at a low enough voltage level to keep the FET 14 cut off, and the composite The above state can be continued and _H can be set in a high direction until a video signal is supplied and a regular synchronization signal is obtained.

The upper limit value of _H can be set by setting the frequency division change range of the variable frequency divider 6.

[Effect of idea]

As described above, by using the horizontal synchronization circuit according to the present invention, the horizontal scanning frequency can always be set in a high direction when there is no signal, and the humming noise caused by the magnetostrictive vibration of the flyback transformer used in the horizontal output circuit can be eliminated. In addition to shortening the horizontal scanning period, the resonance energy of the flightback transformer can be lowered, which suppresses the peak value of the flyback pulse, preventing abnormally high voltage power supplies from rising, and preventing use in horizontal output circuits. It is possible to reduce damage caused by voltage resistance to elements that are connected to other devices.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a horizontal synchronous circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram showing waveforms of each part of the horizontal synchronous circuit, and FIG. 3 is a block configuration diagram of a conventional horizontal synchronous circuit. show.

Claims (1)

[Claims for Utility Model Registration] An A/D converter that receives a composite video signal and outputs a multi-bit digital video signal; and an A/D converter that receives a composite video signal and outputs a multi-bit digital video signal; a synchronization separation circuit that separates and outputs a horizontal synchronization signal by setting the frequency, a variable frequency divider circuit that divides a reference oscillation frequency signal to obtain a horizontal oscillation output, and a phase comparison between the horizontal synchronization signal and the horizontal oscillation output. a frequency division ratio control means that includes a phase comparator that performs the above, and supplies an error signal as a comparison result as a control signal for variably controlling the frequency division ratio of the variable frequency divider circuit; means for generating an AFC pulse; an integrating circuit that integrates the output of the horizontal synchronization separation circuit and generates a detection output of a different level depending on the presence or absence of a horizontal synchronization signal; and the detection output from the integration circuit is a horizontal synchronization signal. means for switching a signal of a specific bit in the digital video signal supplied to the synchronization separation circuit to the AFC pulse and supplying the AFC pulse to the synchronization separation circuit; is characterized in that it is equipped with switching means that is a relatively high-order bit such that the input level to the synchronization separation circuit changes beyond the separation level by changing the logical value of the bit. horizontal synchronous circuit.