JPH0537367A - Internal clock generating circuit - Google Patents

Abstract

PURPOSE:To shorten the internal clock generation time of a voltage control type oscillator in the case a vibrator restarts oscillation by adding a device which can select and output other output voltage than an output voltage of a low-pass filter as a control voltage of the voltage control type oscillator of an internal clock generating device using a PLL circuit. CONSTITUTION:Between a low-pass filter(LPF) 12 and a voltage control type oscillating circuit(VCO) 13, a selecting device 16 is provided so that a control voltage of the VCO 13 can be selected and switched between an output voltage of a voltage generating device 21 and an output voltage of the LPF 12, and by a selecting device control signal 20, an output voltage of an external voltage generating device 21 is selected, when a vibrator restarts vibration from a vibration stop state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer internal clock generation circuit, and more particularly to an internal clock generation circuit using a phase locked loop (hereinafter referred to as PLL) circuit.

[0002]

2. Description of the Related Art As shown in FIG. 5, an internal clock generating circuit using a conventional PLL circuit is attached to a semiconductor integrated circuit 1 and has a capacitor 2 and a vibrator 3 externally attached to the outside of the integrated circuit 1. A reference clock signal 6 is generated by the oscillator circuit 4 provided in the integrated circuit 1. The reference clock signal 6 is supplied to the CPU in the PLL circuit 5.
9 is multiplied by a multiple specified by the PLL control signal 8 output from the CPU 9 and becomes an internal clock signal 7 having a higher frequency than the frequency of the reference clock signal 6 and is input to the CPU 9.
It becomes the operation clock of the CPU 9. This operation clock is a clock having a frequency considerably higher than the frequency of the vibrator 3.

FIG. 6 is a block diagram showing a concrete configuration of the PLL circuit 5. The reference clock signal 6 is first input to the phase comparator 10, and the internal clock signal 7 generated from the voltage controlled oscillator 13 is frequency-divided by the frequency divider 14 to obtain the divided clock signal 15 and the reference clock signal. 6 is compared in phase by the phase comparator 10. The output of the charge pump 11 changes according to the difference in the phase comparison, and the oscillation frequency of the voltage controlled oscillator 13 is controlled by the DC voltage obtained through the low pass filter 12. As a result, the voltage controlled oscillator 13 generates an oscillation frequency corresponding to the voltage.

FIG. 7 shows the characteristics between the input voltage and the oscillation frequency of the voltage controlled oscillator 13. As shown in this figure,
The oscillation frequency changes in proportion to the input voltage. In the locked state of the PLL circuit, if the frequency of the internal clock signal 7 is fosc, the frequency division ratio of the frequency divider 14 is N, and the frequency of the reference clock signal 6 is fc, then fosc = fc × N holds, and By changing the frequency ratio N, N of the reference clock
The doubled frequency signal can be arbitrarily supplied as the internal clock signal 7.

[0005]

However, in this conventional internal clock generation circuit, when the oscillation of the oscillator is stopped and the reference clock signal 6 is stopped and then the oscillation of the oscillator 3 is restarted, a desired frequency is generated. However, there is a problem that it takes a considerable time to generate the internal clock signal 7 of FIG.

Particularly, in the case of an oscillator having a low oscillation frequency, the oscillation stabilization time of the oscillator itself takes a long time.
Up to 2 at operating voltage from 4.5V to 6.0V for 32KHz oscillator
Seconds, a voltage of 2.7V requires a maximum of 10 seconds. The internal clock signal 7 starts the operation of the PLL circuit 5 after the reference clock signal 6 is generated, and then the desired frequency is generated, so that the oscillator 3 of 32 KHz starts oscillating and 4 MHz or 8 MHz.
It takes a considerable amount of time to obtain the internal clock signal. As an example of stopping the oscillator 3, in a microcomputer, the oscillator is stopped by an instruction to create a state in which the internal clock signal 7 is stopped. For example, when an external signal is input, the oscillator responds to the signal and the oscillator It is common to have a standby mode that restarts the vibration of.

On the other hand, even though it has been found that the oscillation oscillator of 5 MHz or more becomes a noise source for peripheral devices due to the high frequency, the oscillation stabilization time is 4.5 ms at the maximum of 10 ms and 2.7 V at the maximum of 30 ms. Because of its short advantage, it is possible to oscillate with an oscillation oscillator of 5 MHz or more and use it as it is as an internal clock signal without using this conventional internal clock generation circuit.

The present invention has been made in view of the above problems, and it is possible to generate an internal clock signal immediately after the oscillation stop of the vibrator is released, and it is possible to execute the processing urgently. An object of the present invention is to provide an internal clock signal generation circuit that enables the realization of a semiconductor integrated circuit.

[0009]

An internal clock generating circuit according to the present invention includes an oscillator circuit, a phase comparator for phase comparison between an output pulse of the oscillator circuit and a divided clock signal, and detection by the phase comparator. Charge pump that changes its output in response to a phase difference that is generated, a low-pass filter that smoothes the output of this charge pump, or an output voltage of this low-pulse filter or an output voltage from an external voltage generator. And a voltage-controlled oscillator that receives the output voltage of the selection device as an input and generates an output pulse having a higher frequency than the frequency of the output pulse of the oscillation circuit in response to the voltage level of the selection device. And a frequency divider which receives the output pulse of the voltage controlled oscillator and outputs the divided clock signal.

[0010]

In the present invention, the control device causes the selection device to selectively output either the output voltage of the low-pass filter or the output voltage of the external voltage generation device, so that the vibrator stops vibrating. When the vibration is restarted from the state, the selection device selects and outputs the output voltage from the external voltage generation device. As a result, the internal clock is generated from the voltage-controlled oscillation circuit to which the output of the selection device is input, immediately after the oscillation of the oscillator is started.

[0011]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an internal clock generating circuit according to an embodiment of the present invention. A reference clock signal 6 is generated from the oscillation circuit 4 due to the vibration of the crystal oscillator, and the reference clock signal 6 is input to the phase comparator 10. The internal clock signal 7 generated from the voltage controlled oscillator 13 is divided by the frequency divider 14 to become a divided clock signal 15, and the divided clock signal 15 and the reference clock signal 6 are phase-compared by the phase comparator 10. It The output of the charge pump 11 changes according to the difference in the phase comparison, and the low-pass output voltage 18 obtained through the low-pass filter 12 is used as the selection device 1.
Enter in 6. The selection device 16 selects either the voltage signal 17 output from the voltage generation device 21 or the low-pass output voltage 18 by the selection device control signal 20, and supplies the selected control voltage signal 19 to the voltage controlled oscillator 13. ing. Then, the oscillation frequency corresponding to the level of the control voltage signal 19 is output from the voltage controlled oscillator 13 and becomes the internal clock signal 7.

FIG. 5 shows the internal clock generating circuit of this embodiment.
The following operation becomes possible by incorporating it in the semiconductor integrated circuit. First, under the control of the CPU, the oscillation of the voltage controlled oscillator 13 is also stopped in a state where the oscillation of the vibrator is stopped. Then, when the stop state is released at the time when a predetermined external signal is input, the selection device 16 controls the voltage signal 17 of the voltage generation device 21 incorporated in the integrated circuit.
Is selected as the control voltage signal 19, and the oscillation operation of the voltage controlled oscillator 13 is started before the oscillator stabilizes oscillation.
The internal clock signal 7 having a frequency corresponding to the control voltage signal 19 is generated to operate the CPU. When the oscillation of the oscillator is stabilized and the oscillation of the oscillator is stabilized and the low-pass output voltage 18 reaches a predetermined level, the CPU detects by means of time measurement after the oscillation of the oscillator is restarted or by a level detection device, The selection device 16 is caused to selectively output the low-pass output voltage 18 as the control voltage signal 19 by the selection device control signal 20. At this point, the PLL operation restarts and P
Lock to a frequency near the internal clock signal frequency before the LL operation.

FIG. 2 is a diagram showing the time between the voltage signal 17 input to the voltage controlled oscillator 13 and the voltage level A set value of the low-pass output 18, starting from the time when the stopped state is released. The solid line is for the voltage signal 17 and the broken line is for the low-pass output voltage 18. In this way, after canceling the stop, the internal clock signal can be generated in the order of millisecond. FIG. 3 is a block diagram of an internal clock generating circuit according to the second embodiment of the present invention. The basic operation is the same as that of the first embodiment, but the voltage generating device 21 of FIG. 1 is replaced by a programmable voltage generating device 22 capable of setting a generated voltage value programmably by a CPU due to its configuration. With this configuration, the frequency at the start of oscillation of the voltage controlled oscillator 13 can be made variable when the stopped state is released, and a desired frequency can be obtained according to the operating voltage of the semiconductor integrated circuit including the internal clock circuit. The operation can be restarted by the internal clock signal of the frequency.

FIG. 4 shows the voltage level B of the low-pass output voltage 18 and the voltage level of the low-pass output voltage 18 which are input to the voltage controlled oscillator 13 and whose voltage levels can be changed programmably and the voltage levels differ depending on the set value of the frequency divider 14. It is the figure which represented the time until C setting starting from the time of cancellation | release of a stopped state. The solid line is for the voltage signal 17 and the broken line is for the low-pass output voltage 18. The selection device control signal 20 of FIGS. 1 and 3 operates even when a vibrator stop due to an external factor is detected in addition to the stop of the vibrator under CPU control and the release of the vibrator stop state by an external signal. As a result, the internal clock signal can be continued, and a highly reliable system can be realized.

[0016]

As described above, according to the present invention, the selection device capable of controlling the input voltage of the voltage controlled oscillator is provided between the voltage controlled oscillator and the low-pass filter. It is possible to apply a predetermined input voltage to the voltage controlled oscillator before the reference clock is generated, and it is possible to shorten the generation start time of the internal clock signal when the oscillator is released from the stopped state. Therefore, since the internal clock signal can be generated immediately after the stop of the oscillator is released, it is possible to provide a versatile semiconductor integrated circuit capable of executing processing urgently.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal clock generation circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an input voltage and a required time of the voltage controlled oscillator according to this embodiment.

FIG. 3 is a block diagram showing an internal clock generation circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between an input voltage and a required time of the voltage controlled oscillator of this embodiment.

FIG. 5 is a block diagram showing a semiconductor integrated circuit having an internal clock generation circuit built therein.

FIG. 6 is a block diagram showing a conventional internal clock circuit.

7 is a diagram showing characteristics of the voltage controlled oscillator 13. FIG.

[Explanation of symbols]

1; Semiconductor integrated circuit 2; Capacitor 3; oscillator 4; Oscillation circuit 5; PLL circuit 6; Reference clock signal 7: Internal clock signal 8: PLL control signal 9; CPU 10: Phase comparator 11; Charge pump 12; Low-pass filter 13; Voltage controlled oscillator 14; Divider 15: Divided clock signal 16; Selection device 17; voltage signal 18; Low-pass output voltage 19; Control voltage signal 20; Selector control signal 21; Voltage generator 22; Programmable voltage generator

Claims (2)

[Claims] 1. An oscillator circuit, a phase comparator for phase-comparing an output pulse of the oscillator circuit and a divided clock signal, and a charge pump for changing an output in response to a phase difference detected by the phase comparator. A low-pass filter for smoothing the output of the charge pump; a selection device for selectively outputting one of the output voltage of the low-pulse filter and the output voltage of the external voltage generator by a control signal; and this selection device. Of the output voltage of the oscillator circuit, which generates an output pulse of a higher frequency than the frequency of the output pulse of the oscillation circuit, and an output pulse of the voltage control type oscillator. An internal clock generation circuit comprising: a frequency divider that outputs a frequency-divided clock signal. 2. The internal clock generation circuit according to claim 1, wherein the output voltage level of the external voltage generator can be set programmable.