JPH0537357A - Integrated photoelectric logical arithmetic system - Google Patents

Abstract

PURPOSE:To make the most of a high-speed property and simplicity of a photoelectric logical arithmetic gate consisting of a semiconductor photodetector, and compactness of the whole system by integrating it into a feedback loop of an optical signal, and also, to simplify an input/output system of the optical signal. CONSTITUTION:An integration photoelectric logical arithmetic substrate 1 provided with an arithmetic circuit part 11 using plural pieces of semiconductor light receiving elements, and integration optical signal output substrates 21, 22 in which plural semiconductor photodetector 211-21n, and 221-22n are integrated and placed, respectively are connected through electric wirings 31, 32. The integrated optical signal output substrate 21 is a substrate for outputting a result of operation to the outside, and the integrated optical signal output substrate 22 is a substrate for leading an optical signal into a feedback loop in order to store temporarily the result of operation, or in order to input it to the integrated photoelectric logical arithmetic substrate 1 again. By opposing these substrates, sticking and fixing them, while aligning the optical axes, and converting them to a module, a signal loop can simply be constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical signal logical operation system.

[0002]

2. Description of the Related Art An optical computer and a logical operation system based on optical signals, which have been mainly studied in the past, have a spatial light modulator 1 as a spatial filter, as shown in FIG.
5 is used in combination with the light emitting element array 16 and the light receiving element array 17, and is characterized in that a large-scale two-dimensional matrix operation utilizing the parallelism of light can be performed at one time. As a memory used for this, a ferroelectric crystal such as LiNbO ₃ or a semiconductor p
There is an optical switch having an npn structure and a switch utilizing the nonlinearity of a semiconductor laser. Research and development have been carried out on a spatial light modulation tube configured in a vacuum tube type by combining these, and an optical computer element and an optical neuro element modularized using semiconductor technology. The details are given below in the fall of 1989. , The 50th Academic Meeting of The Japan Society of Applied Physics
Symposium Digest, "Optical Computing"
(JSA cat-no: AP891232).

On the other hand, the present inventors have previously constructed the circuits shown in FIGS. 16 and 17, and perform a logical operation such as half addition using an optical signal on several semiconductor light receiving elements 8, 8 _1. , 8
It was shown that ₂ can be used. According to this, by combining the bias power sources 18 ₁ to 18 ₃ , the auxiliary resistors and capacitors 19 _{1 to} 19 ₄ , and the load resistors 20 ₁ and 20 ₂ with the photoelectric half addition arithmetic circuit, the operation speed and the simplicity of the configuration are superior. You can find sex. 18 and 19 are examples of integrated circuits in which the photoelectric half-addition arithmetic circuits shown in FIGS. 16 and 17 are integrated on the same semiconductor substrate 4. The same parts as those in FIGS. 16 and 17 are designated by the same reference numerals. Note that these photoelectric half-addition arithmetic circuits and integrated circuits using the same are described in the following document by the present inventors, “IEEE J.Qantum electron., Vol.26, pp.619-621, 199”.
0 ”, Japanese Patent Application No. 1-077332, or Japanese Patent Application No. 2
It is described in detail in Japanese Patent Laid-Open No. 103410. Further, as shown in FIG. 20, the photoelectric half-addition operation circuit described above is connected to the optical memory 26 to form one logical operation unit, and these are connected to each other by an optical wiring portion 27 using an optical fiber or an optical waveguide.
It was proposed that high-speed photoelectric full addition operation can be performed by optically coupling via. The details of this are described in Japanese Patent Application No. 1-161913.

Further, a photoelectric exclusive OR (XOR) operation gate array 28 and a photoelectric AND (AND) operation gate array 29, which are composed of such light receiving elements, are arranged on a plane together with the light emitting elements, and a reflecting mirror or An optical signal is fed back between the integrated circuit boards by a corner cube or the like, and a signal loop is configured to devise a multi-bit (4-bit) parallel operation type photoelectric full addition operation system (see FIG. 21). .. For more information on this, see H. Kamiyama
Et al., “Japan J. Appl. Phys., Pt.2, vol.29, pp.1248-1251,”
1990 ". Also, the inventors have found that during the signal loop,
We have proposed a serial arithmetic photoelectric full addition arithmetic system that is configured by incorporating a memory loop for one clock. This memory loop utilizes the fact that this photoelectric operation system is composed of a feedback loop of an optical signal using a reflecting mirror, and a set of a light emitting element and a light receiving element for circulating a signal in the operation system is used. It was introduced easily by providing it. FIG. 22 shows a specific example of the semiconductor light emitting devices 21 _{1 to} 21 in which a photoelectric exclusive OR (XOR) operation gate array 28 and a photoelectric AND (AND) operation gate array 29 each including a semiconductor light receiving element are provided. It is realized including the memory function by arranging it together with ₃ on a plane and by using the corner cube 10 to perform feedback of an optical signal.

[0005]

First, when a spatial light modulator is used, this material is a liquid crystal or a ferroelectric crystal.
Also, a semiconductor multiple quantum well (MQW) or the like is used. Among them, the liquid crystal has a very slow response time of several msec and is not suitable for high-speed calculation. Ferroelectric crystal has a response time of 1
On the order of 00 μs, it is faster than the liquid crystal, but not sufficient. In addition, the light transmittance is low and the contrast cannot be high.
Therefore, in the spatial light modulator, the micro channel plate is incorporated inside, but the optical computer configured by this has a drawback that the entire system becomes large. Furthermore, at present, it is very difficult to produce stable crystals, and there is no prospect of industrialization. MQW is a material that has been attracting attention due to recent improvements in semiconductor crystal technology, and has a very fast response speed of 1 ns or less, but has a drawback that the on / off ratio is poor and the contrast is low. In addition, it requires a high-level crystal growth technique, which makes it very expensive.

On the other hand, the method of connecting the optoelectronic logic operation unit composed of the semiconductor light receiving element and the optoelectronic logic operation unit composed of the light emitting element by the optical wiring is characterized by high speed and simple structure. Further, by incorporating this in a feedback loop of an optical signal using a reflecting mirror or the like, the whole system can be made compact and the memory function can be easily incorporated, so that these features can be further utilized. However, here, since the input and output of the optical signal and the feedback function are covered by one reflecting mirror or corner cube, it is troublesome to sort the optical signals of different destinations, and the polarization state is changed by the external control. It is necessary to control these optical signals for each clock by inserting a polarizing plate such as an electro-optical element. For example, in the arithmetic system shown in FIG. 21,
First, the half mirror, which is a reflecting mirror, is a polarizing mirror with different transmittance depending on the polarization state of the incident light, and the above-mentioned polarizing plates are inserted before and after the mirror so that an optical signal is input from the outside or an optical signal is input. When outputting a signal to the outside, it allows light to pass through the polarizing mirror, and when returning the optical signal internally, the polarizing mirror reflects the light, which is a very troublesome control. Need. For this reason, the optical system and the timing clock system have become complicated, and it has not been possible to make full use of the above characteristics.

The present invention takes advantage of the high speed and simplicity of a photoelectric logic operation gate composed of a semiconductor light receiving element, and the compactness of the entire system by incorporating this in a feedback loop of an optical signal. A more practical photoelectric logic operation system is provided by simplifying the input / output system.

[0008]

In the integrated photoelectric logic operation system of the present invention, the semiconductor light receiving element is used as an input photoelectric conversion gate, a plurality of these gates are arranged on the semiconductor substrate, and wiring between these gates is provided.
Or, depending on the polarity and size of the bias power supply given to each gate, a predetermined logical operation
An optoelectronic logic operation circuit, which receives an optical signal, arranges a plurality of integrated optoelectronic logic operation boards and a plurality of semiconductor light emitting elements on a semiconductor substrate, and outputs these operation results to an optical signal. One or more integrated optical signal output boards for converting and outputting, and electrical wiring for electrically connecting the integrated optoelectronic logic operation board and the integrated optical signal output board An integrated optical signal output board provided for inputting a part of the obtained optical output signal to the optoelectronic logic operation circuit in the optoelectronic logic operation board again, in which the light emitting element is integrated optoelectronic logic operation board And an input photoelectric conversion gate corresponding to each of the above, and a feedback unit of the optical signal by being arranged so as to have a geometrical optical coupling relation. Furthermore, by arranging a plurality of these as unit operation blocks in parallel, and by optically connecting the unit operation blocks so that a part of each optical output signal is cascaded, a plurality of unit operation blocks can be provided. The present invention is characterized in that it is a parallel type integrated optoelectronic logic operation system configured to perform logic operations simultaneously in parallel by simultaneous input of bit optical signals.

In the unit operation block described above, the integrated optical signal output board provided for feeding back an optical signal is arranged to face the integrated photoelectric logic operation board, or the unit operation block described above is provided. Inside, there is provided means for branching and outputting a part of the integrated optical signal output substrate into two sets, one is for outputting the operation result to the outside of the unit operation block, and the other is Can be configured only to feed back the operation result in the unit operation block.

Further, the above-mentioned semiconductor light receiving element has a substantially symmetrical electrode structure constituted by arranging Schottky junctions facing each other on a semiconductor substrate, and further, the semiconductor light emitting element has a surface emitting device. It is preferably an integrated optoelectronic logic system that is a laser.

In the integrated optoelectronic logic operation system described above, the integrated optoelectronic logic operation board and a part or all of the integrated optoelectronic signal output board are included in the same semiconductor substrate, including electrical wiring for electrically connecting them. In the configuration monolithically integrated above, an optical signal is input to one surface of the semiconductor substrate and an optical signal is output from the other surface,
Further, another integrated optical signal output board for returning a signal between the integrated circuit boards is faced and overlapped so as to satisfy the optical coupling relationship corresponding to each other, and a fixed configuration is taken. However, shortening the propagation delay time,
It is desirable in terms of suppressing crosstalk and downsizing the system.

As the semiconductor substrate, semi-insulating GaAs is used.
It is desirable to use a substrate, a semi-insulating InP substrate, or a GaP substrate.

The integrated optoelectronic logic operation system of the present invention further comprises means for receiving in parallel optical input signals having a plurality of bits and arranging the bit signals in parallel in the logic circuit.
It may include means for arranging the optical output signals in parallel for output of a multi-bit configuration.

Further, a full addition arithmetic system can be constructed as a concrete example of the above-mentioned integrated photoelectric logic arithmetic system. This is because a circuit configured to perform a half addition operation is provided in the integrated photoelectric logic operation board, and the CARRY optical signal output as the operation result and converted by the integrated optical signal output board is transferred between the integrated circuit boards. Is temporarily stored by the signal circulation function by the feedback of the above, and is inputted again to the half addition arithmetic circuit part in the integrated photoelectric logic arithmetic circuit board. A circuit designed to perform a half addition operation is provided in the logical operation board, and the CARRY optical signals output as the operation result and converted by the integrated optical signal output board are arranged in parallel and optically cascaded. As a whole, the method of performing the full addition operation in parallel can be achieved by the configuration configured to input to the photoelectric half addition operation circuit portion in the unit operation block of 1-bit higher order. It is possible to realize.

The CARRY electric signal in the calculation result obtained by the parallel optical signal input may be used as an electric signal input to the arithmetic gate of 1-bit higher without being converted into an optical signal. ..

[0016]

[Especially p. 5, l. 19-p. 6, l. Solution of 3]
According to the present invention, the semiconductor light receiving element and the semiconductor light emitting element,
The respectively integrated semiconductor substrates can be spatially arranged to be optically coupled to each other to form a signal loop. In particular, the optical signal input / output system can be spatially distributed to simplify the path. This results in even faster computing speed and significantly less attenuation of the optical signal within the computing system.

To this end, in the present invention, the input / output system of the optical signal is first distributed to simplify the optical signal path. Specifically, the optical signal output to the outside and the output portion of the optical signal circulating in the loop may be spatially separated so that the output signal to the outside does not pass through the loop.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of an integrated photoelectric logic operation system according to the present invention. Here, an operational circuit portion 11 is provided in an integrated photoelectric logic operation substrate 1 in which a plurality of semiconductor light receiving elements are integrated and arranged on a semiconductor substrate, and the semiconductor light receiving elements included in each of them are provided, and between these elements. A predetermined logical operation is performed according to the wiring and the polarity of the bias applied to the element. The integrated optical signal output board 2 ₁ and 2 _2, a plurality of semiconductor light emitting elements 21 ₁ through 21 _n and 22 ₁ to 22
_n are collected and arranged. Of these, the integrated optical signal output substrate 2 ₁ is a substrate for outputting the operation result to the outside, and the integrated optical signal output substrate 2 ₂ temporarily stores the operation result or again the integrated photoelectric logic operation substrate 1 It is a substrate for introducing an optical signal into a feedback loop for input to. These may include the semiconductor light emitting device 21 as necessary.
Electronic amplification circuits for amplifying the electric signals input to _{1 to} 21 _n and 22 _{1 to} 22 _n are added and integrated. This signal loop is realized by arranging the integrated optical signal output board 2 ₂ and the integrated optoelectronic logic operation board 1 so as to have a geometrical optical coupling relationship. In a simple manner, as shown in FIG. 1, the integrated optical signal output substrate 2 ₂ can be constructed by arranging the integrated optical signal output substrate 2 ₂ so as to face the integrated photoelectric logic operation substrate 1. Optical signals can be re-input to the integrated optoelectronic logic board 1. For this purpose, a semiconductor light emitting element 22 ₁ through 22 _n on the integrated optical signal output board 2 _2, the partner optical signal is input will now output a light receiving element on the integrated photoelectric logic operation board 1 However, they must face each other and be integrated and integrated in the same position. In particular, a signal loop can be easily constructed by facing these two integrated circuit boards, adhering and fixing them while aligning the optical axes, and modularizing this part. In this case, since it is not necessary to use optical components such as a lens, the entire system can be made compact. The electric signals output from the integrated optoelectronic logic operation board 1 are input to the integrated optical signal output boards 2 ₁ and 2 ₂ via the electric wirings 3 ₁ and 3 ₂ , respectively. By configuring the entire system in this way, the optical signal output to the outside does not have to pass through the loop, and the path of the optical signal is simplified, so that complicated control for each clock is unnecessary. Also, a signal delay circuit such as a shift register, which is often required for complicated operations such as four arithmetic operations, can be easily incorporated in the present photoelectric logic operation system by utilizing this signal loop.

Further, when the logical operation is performed by using the optical signal as described above, a plurality of signals can be combined by the optical multiplexing method and a plurality of logical operations can be simultaneously performed. It is possible. Lena structure is preferable. This structure is generally called an MSM (metal-semiconductor-metal) structure, and the light receiving element of this structure, MSM-PD.
Has been studied by the present inventors as an element having excellent high speed characteristics. For details, refer to the following document “IEEE Trans. Electoron Devices, vol.37, pp.31-35,
2 shows a typical device structure thereof. Here, Schottky electrodes 5 ₁ and 5 ₂ are formed on a semiconductor substrate (including an active layer) 4 so as to face each other. In addition, the insulator thin film 6 is formed on the portion other than the light receiving portion.The light receiving portion preferably has a comb-shaped electrode structure in order to make an effective light receiving area. As a result, it is easy to integrate a plurality of devices in the same semiconductor substrate, the symmetrical electrode structure is optimal for logical operation, and the junction type has a small dark current, and furthermore, it has excellent high-speed response characteristics. There are four points of being.

Examples of the light emitting element include an LED and a semiconductor laser, which have high speed and high coherence (light condensing property).
From this point of view, a semiconductor laser is suitable. Of these, surface emitting lasers, which have recently attracted attention, emit light beams perpendicularly to the semiconductor substrate, and therefore can be arrayed and integrated on a plane. Optimal. For more information on this, see K. I
The following reference by Ga et al., “J. Vac. Sci. Technol. A, vol. 7, pp. 842-846, 1989” is described. FIG. 3 shows a typical element structure thereof. A multilayer film reflection mirror 7 ₁ is provided on the active region 4 ₂ of the semiconductor substrate 4 ₁ , and an ohmic electrode 5 ₁ is further formed on _one surface of the substrate. Its the other surface of the substrate ohmic electrode 5 ₂ through the insulating thin film 6 is formed, it is covered further by the reflecting mirror 7 _2.

FIG. 4 is a conceptual diagram of the integrated optoelectronic logic operation board 1 using the MSM-PD. M on the semiconductor substrate 4
The light receiving elements 8 ₁ to 8 _n using the SM-PD are arranged, and the insulating thin film 6 is formed on the portion other than the light receiving portion. The light receiving elements 8 ₁ to 8 _n are wired by a conductor thin film electrode 9. FIG. 5 is a conceptual diagram of the integrated optical signal output substrates 2 ₁ and 2 ₂ using the surface emitting laser, in which light emitting elements 21 _{1 to} 21 _n using the surface emitting laser are formed on the semiconductor substrate 4. The other parts are covered with the insulator thin film 6.
The light emitting elements 21 _{1 to} 21 _n are wired by the conductor thin film electrode 9. As shown here, in the present invention, since the integrated photoelectric logic operation substrate 1 and the integrated optical signal output substrates 2 ₁ and 2 ₂ are integrated on the semiconductor substrate 4, respectively, high density and high efficiency are achieved. Can be configured. In addition, since the position of each element is clearly determined by this integration, the optical axis alignment for spatial optical coupling, which is indispensable in the present invention, is facilitated.

Furthermore, a photoelectric logic operation circuit portion and an optical signal output portion are integrated together on the same semiconductor substrate, and an optical signal is input to one surface and an optical signal is output from the other surface. It is also possible to do so. FIG. 6 is a conceptual diagram of this integrated circuit, in which M on the semiconductor substrate 4 is shown.
The light receiving elements 8 ₁ to 8 _n using the SM-PD and the light emitting elements 21 _{1 to} 21 _n using the surface emitting laser are arranged, and the insulator thin film 6 is formed on the other portions. Light emitting element 2
Between 1 _{1 to} 21 _n are wired by the conductor thin film electrode 9. As a result, the delay time in the electric wiring portion connecting these two portions can be shortened and the propagation distortion of the electric waveform can be minimized. In this configuration, an integrated optical signal output substrate 2 ₁ for returning an optical signal is faced to this substrate, and the entire arithmetic system can be configured by only a total of two substrates. Further, as described above, the integrated optical signal output substrate 2 ₁ for returning optical signals is superposed on this, and is adhered and fixed, so that the arithmetic system is integrated into only one module, which is more compact. It becomes a shape. This specific example is shown in FIG. The same parts as those in FIG. 6 are designated by the same reference numerals.

As the semiconductor substrate 4 used for these integrated circuits, a GaAs III-V compound semiconductor or InP is used to form a photoelectric element, especially a semiconductor laser.
Substrates are common. In particular, a high-resistance, low-capacity semi-insulating substrate that is easy to separate between elements and has excellent high-speed characteristics is suitable. Among them, the semi-insulating GaAs substrate is for short wavelength of about 0.8 μm, and the semi-insulating InP substrate is
It is used for long wavelengths with wavelengths of 1.3 μm and 1.55 μm. Further, recently, there are cases in which a GaP substrate is used.

Next, a system configuration diagram in FIG. 1, particularly an embodiment in which the optical signal feedback method is modified will be shown. In FIG. 8, the integrated optical signal output substrate 2 ₂ is arranged in a plane perpendicular to the integrated optoelectronic logic operation substrate 1, and an optical coupling portion is configured by using a reflecting mirror 7 ₂ . 9, placing the integrated optical signal output board 2 ₂ for integration photoelectric logical operation substrate 1 and the same plane, with the corner cube 10, which is constituted of the optical coupling portion. In this configuration, the optoelectronic logic operation part of the integrated optoelectronic logic operation board 1 and the optical signal output parts of the two integrated optical signal output boards 2 ₁ and 2 ₂ can all be integrated on the same semiconductor substrate. is there. When actually integrated, the propagated electric signals are all processed in the semiconductor substrate, so that the propagation delay time and the waveform distortion are minimized, and the system has the highest speed. As shown herein, in the method of forming the optical coupling portion with the reflector 7 ₂ and corner cube 10 and the like, by using these to that of the semi-transparent material such as a beam splitter,
It is possible to take out a part of the optical signal to the outside and monitor it, or add another function. Besides this, there is also a method of wiring each substrate with an optical fiber. However, these methods require an optical component such as a lens or an optical fiber as an optical coupling means for returning an optical signal, so that the entire system is not necessarily compact.

Next, as a specific logical operation, a full addition operation will be taken as an example. The full addition operation is the most basic operation in a computer, and is the most important operation in realizing an optical computer. Although a semiconductor light emitting element and a light receiving element are spatially optically coupled by using a corner cube or the like, a proposal has already been made to perform a full addition operation, but according to the present invention, this is It can be realized with a simpler configuration and method.

FIG. 10 shows an embodiment of the integrated photoelectric logic operation system shown in FIG. 1 in the case where the full addition operation is performed in series. Here, the integrated photoelectric logic operation substrate 1 performs half addition operation by inputting an optical signal, and outputs the result as an electric signal. Here, there are two sets of circuits 11 for actually performing calculations.
And 12, and photoelectric conversion gates 11 ₁ and 11 ₂ , 12 ₁ and 12 ₂ each including _{two of them} , and a photoelectric conversion gate 13 for forming a signal loop and temporarily storing an operation result. ing. As an example of the arithmetic circuit, as described above, FIG.
, And corresponding integrated circuit diagrams are shown as prior art in FIGS. 18 and 19, respectively. In these circuits, the MSM-PD is suitable for the semiconductor light receiving element used as the photoelectric conversion gate, as described above. Further, a semiconductor light emitting element 24 for converting the calculation result into an optical signal and outputting the signal to the outside is also integrated on this substrate, which corresponds to a specific example of the configuration shown in FIG.

The integrated optical signal output board 2 receives an electric signal from the integrated optoelectronic logic operation board 1, converts the electric signal into an optical signal and outputs the optical signal, and inputs the electric signal to the integrated optoelectronic logic operation board 1 again. The integrated optical signal output board 2 constitutes a signal loop by being arranged so as to face the integrated photoelectric logic operation board 1. Here, the semiconductor light emitting elements 21 and 22 for outputting optical signals to be inputted to the photoelectric conversion gates 12 ₁ and 12 ₂ of the arithmetic circuit portion incorporated in the integrated photoelectric logic operation substrate 1 and the operation result are shown. A semiconductor light emitting device 23 that outputs an optical signal to be input to the photoelectric conversion gate 13 for temporary storage is incorporated. In addition, an electronic amplifier circuit for amplifying an electric signal before input is added to and integrated with each of these semiconductor light emitting elements as needed. As the semiconductor light emitting device used here, the surface emitting laser is suitable as described above.

The electrical signal output from the integrated optoelectronic logic operation substrate 1 is input to the integrated optical signal output substrate 2 via the electrical wiring 3 ₁ . Moreover, the operation result electrical signal, the integrated photoelectric logic operation substrate 1, it is input to the semiconductor light emitting element 25 via the electrical wiring 3 _2.

Next, the operation of this example will be described with reference to the flowchart shown in FIG. If the two sets of input data to be added are X and Y, these are the lower bits (digits).
From the upper bits to X (x ₀ ,
x ₁ , ..., X _n ), Y (y ₀ , y ₁ , ..., Y
_n ) of n binary data. Now, when the optical signal of the k-th bit x _k , y _k is inputted to the photoelectric conversion gates 11 ₁ and 11 ₂ of the arithmetic circuit portion 11 incorporated in the integrated photoelectric logic arithmetic substrate 1, here, Addition processing is performed, and the calculation result s corresponding to SUM and CARRY
_k and c _k are output as electric signals, respectively. At the same time, the photoelectric conversion gates 12 ₁ and 1 of the arithmetic circuit portion 12 are
2 ₂ includes the SUM signal s _k-1 which is the (k-1) th operation result _one bit before and the CARRY "optical signal c" _k which is the (k-2) th carry signal two bits before. _-2 is input and half addition arithmetic processing is performed here, SUM, CARRY
It is the operation result _{s 'k-1, c'} k-1 corresponding to, are respectively output as an electric signal. Further, the photoelectric conversion gate 13
Is a semiconductor light emitting element 23 in the integrated optical signal output substrate 2.
From the (k-1) th operation result one bit before,
The CARRY optical signal c _k-1 temporarily stored by the signal loop is input and similarly output as an electrical signal.
These electrical signals is inputted to the integrated optical signal output substrate 2 through the electrical wiring 3 _1, of which s _k is the semiconductor light emitting element 21, c _k is the semiconductor light emitting element 23, also c
_k-1 and _c'k-1 are combined in the electrical wiring 3 _-1 (wired OR) and input to 22 as c " _k-1 .

These are converted into optical signals here and input again to the integrated optoelectronic logic operation substrate 1. However, as predetermined, the optical signal s _k output from the semiconductor light emitting device 21 is The optical signal c output from the semiconductor light emitting element 22 is supplied to the photoelectric conversion gate 12 ₁ of the arithmetic circuit portion 12.
_k-1 is the 12 _2, optical signal c _k output from the semiconductor light emitting element 23 also is input to the photoelectric conversion gate 13, is temporarily stored by the signal loop. At the same time, the optical signals of the next bits x _{k + 1} and y _{k + 1} are transferred to the photoelectric conversion gate 1
It is input to 1 ₁ and 11 ₂ .

Here, the half-addition operation is simultaneously performed in the two sets of operation circuit portions 11 and 12 incorporated in the integrated optoelectronic logic operation substrate 1, of which, from the operation circuit portion 12,
Each SUM, operation results s _'k, c' corresponding to the CARRY _k is output as an electrical signal. At the same time, the CA temporarily stored from the photoelectric conversion gate 13
The RRY signal c _k is also output as an electric signal.

[0032] Among these electric signals, s' _k, through electrical wiring 3 _2, both integrated into integrated photoelectric logic operation substrate 1, is input to the semiconductor light emitting element 24. Also, c
_k and c ′ _k are combined in the electric wiring 3 ₁ and input as c ″ _{k to} the semiconductor light emitting element 22 in the integrated optical signal output substrate 2. Further, (k + k) is input to the arithmetic circuit portion 11.
The 1) th optical signals x _{k + 1} and y _{k + 1} are processed in the same manner as the above-mentioned kth optical signal.

The electrical signal s' _k, which is input to the semiconductor light emitting element 24, where it is converted into an optical signal is output to the outside as the full addition operation result of k-th bit. In this way, two sets of binary data are input as optical signals in order from the lower bits, and the full addition operation is repeated n times, so that the operation results are output to the outside as optical signals in order from the lower bits. It

In the serial type full addition operation method described here,
As the half-addition arithmetic circuit, which is the center of the circuit, we use a circuit with excellent high-speed characteristics. Since its operation speed is substantially equal to the response speed of the semiconductor light-receiving element used for this, the light-receiving element has By using the MSM-PD, one half addition operation time is about 0.1 ns. 1
The serial serial full addition operation of bits only adds two half addition operation times and the propagation delay time of the electric signal, the response time of the semiconductor light emitting element, and the propagation delay time of the optical signal to the light emitting element. Using a semiconductor laser such as a surface emitting laser,
In addition, by modularizing the whole and minimizing the signal propagation time, the total addition operation time for 1 bit is 0.3
A very high-speed arithmetic system of about 0.5 ns can be realized.

Next, a parallel integrated photoelectric logic operation system will be described. FIG. 12 shows a configuration in which the integrated optoelectronic logic operation system as shown in FIG. 1 is used as one unit and is arranged in parallel. It is designed to be able to perform arithmetic processing simultaneously. Such a parallel operation method is effective when a very large amount of data needs to be processed in a short time, such as two-dimensional image processing, or when the shape of input data has a spatial spread. Is. Here, ..., (k-1), k, (k + 1), ...
Each of ... Is a unit of an integrated optoelectronic logic operation system as shown in FIG. Each unit operation block may act independently, or adjacent operation systems may collectively act while exchanging data with each other in the form of an optical signal. In this case, by arranging the respective unit operation blocks so as to geometrically overlap each other as shown in the figure, it is possible to optically couple them without using optical components such as lenses and optical fibers. is there.

As a concrete example of the parallel integrated photoelectric logic operation system, a case where the full addition operation is performed in a parallel system will be described. FIG. 13 shows a ripple carry type parallel full addition operation in which the integrated photoelectric logic operation system for performing the full addition operation as shown in FIG. System.

In the integrated photoelectric logic operation substrate 1, two sets of half addition operation circuits 11 and 12 per bit are provided to perform half addition operation by inputting an optical signal and output the result as an electric signal. The photoelectric conversion gates 11 ₁ , 11 ₂ , 12 ₁ , 12 ₂ each including two of them and the photoelectric conversion gate 13 for forming a signal loop and temporarily storing the operation result are incorporated therein, and these are the number of bits. It is integrated in parallel by the amount. This half addition arithmetic circuit is the same as that used in FIG. As described above, the MSM-PD is suitable for the semiconductor light receiving element used as the photoelectric conversion gate. Further, one semiconductor light-emitting element 24 for converting the operation result into an optical signal and outputting the same to the outside is also integrated on this substrate, one for each bit, and the configuration shown in FIG. It corresponds to a specific example.

The integrated optical signal output board 2 is for receiving an electric signal from the integrated optoelectronic logic operation board 1, converting it into an optical signal, and inputting it to the integrated optoelectronic logic operation board 1 again. The signal loop is formed by being arranged so as to face the integrated photoelectric logic operation substrate 1. Here was incorporated into an integrated opto-electric logic operation substrate 1, and outputs an optical signal to be input to the photoelectric conversion gate 12 _second arithmetic circuit portion 12, the arithmetic circuit portion of the semiconductor light emitting element 21 and a bit higher, 12 photoelectric conversion gates 1
A semiconductor light emitting element 22 that outputs an optical signal for input to 2 ₁ and a semiconductor light emitting element 23 that outputs an optical signal for input to the photoelectric conversion gate 13 for temporarily storing the operation result are incorporated. ing. In addition, an electronic amplifier circuit for amplifying an electric signal before input is added to and integrated with these semiconductor light emitting elements as needed. As the semiconductor light receiving element used here, the surface emitting laser is suitable as described above.

The electrical signal output from the integrated optoelectronic logic operation substrate 1 is input to the integrated optical signal output substrate 2 via the electrical wiring 3 ₁ . In the integrated photoelectric logic operation substrate 1, the operation result an electrical signal is input to the semiconductor light emitting element 24 via the electrical wiring 3 _2. As described above, the parallel type full addition operation system shown here is merely a spatial expansion of the serial type full addition operation system shown in FIG. 10, and the operation is exactly the same. Therefore, the operation speed is equal to that of the serial type, but this method is effective when the optical input signal is spatially expanded such as image data.

Next, the operation of this example will be described with reference to the flow chart shown in FIG. Similarly to the above, the two sets of input data to be added are X (..., x _k-1 , x _k ,
x _{k + 1} , ...), Y (..., y _k-1 , y _k ,
y _{k + 1} , ...). Each of these binary data is bit by bit, that is, (x _k-1 , y _k-1 ), (x
_k , y _k ), (x _{k + 1} , y _{k + 1} ), ... Spatially distributed and incorporated into the integrated optoelectronic logic operation substrate 1 and are unit operations corresponding to the respective bits. The photoelectric conversion gates 11 ₁ and 11 ₂ of the arithmetic circuit portion 11 in the block
Are input in order from the least significant bit. Now, when the optical input signals x _k and y _{k of} the k-th bit are inputted to the photoelectric conversion gates 11 ₁ and 11 ₂ of the arithmetic circuit portion 11 incorporated in the integrated photoelectric logic arithmetic substrate 1, here, are added processing, SUM, operation result s _k corresponding to CARRY, c _k are respectively output as an electric signal. These electrical signals through electrical wiring 3 _1, the integrated optical signal output substrate 2, but is input to the semiconductor light-emitting device of the same unit operation block, of which s _k is the semiconductor light emitting element 21, c _k Is input to the semiconductor light emitting device 23.

These are converted into optical signals here and input to the integrated photoelectric logic operation substrate 1 again, but here, as determined in advance, the semiconductor light emitting element 21 is used.
The optical signal s _k output from the photoelectric conversion gate 12 of the other arithmetic circuit portion 12 in the same unit arithmetic block
₂ and the optical signal c output from the semiconductor light emitting device 23
_k is input to the photoelectric conversion gate 13 and temporarily stored by the signal loop. At the same time, the CARR from the semiconductor light emitting element 22 in the unit operation block of 1-bit lower order, which is integrated and arranged in the integrated optical signal output substrate 2, is CARR.
The Y ″ optical signal c ″ _k−1 is input to the photoelectric conversion gate 12 ₁ of the arithmetic circuit section 12. At the same time with these, (k
The +1) th optical input signals x _{k + 1} and y _{k + 1} are input to the photoelectric conversion gates 11 ₁ and 11 ₂ of the arithmetic circuit portion 11 of the unit arithmetic block of 1-bit higher order, respectively.

Here, in the integrated photoelectric logic operation substrate 1, the operation circuit portion 12 in the k-th unit operation block,
Half-addition operations are simultaneously performed in the operation circuit portion 11 in the and (k + 1) th unit operation blocks, respectively, and as the operation results, the SUM ′ signal s ′ _k and the CARRY ′ signal c ′ _k are _obtained from the former. , SUM signal s from the latter
_{The k + 1} and CARRY signals c _{k + 1} are output as electric signals. The CARRY signal c _k input to the photoelectric conversion gate 13 for temporary storage is converted into an electric signal here and output.

[0043] Among these electric signals, s' _k, through electrical wiring 3 _2, integrated photoelectric incorporated both logic operations substrate 1, the semiconductor light-emitting element 2 of the same unit operation block
4, is converted into an optical signal, and is output to the outside as the addition operation result of the k-th bit. At the same time, _c'k is c
It is combined with the electric wiring 3 ₁ together with _k and inputted to the semiconductor light emitting element 23 in the integrated optical signal output substrate 2 as c ″ _k , converted into an optical signal here, and incorporated into the integrated photoelectric logic operation substrate 1. In the unit operation block of 1-bit higher order, it is input to the photoelectric conversion gate 12 ₁ of the operation circuit portion 12. In this way, two sets of binary data are input as an optical signal bit by bit. , The full addition operation is performed in order from the lower bit, and the operation result is output to the outside as an optical signal.

Also in the parallel type full addition operation method described here, a half addition operation circuit, which is the center of the parallel full addition operation method, has excellent high-speed characteristics, and its operation speed is substantially the same as that of the semiconductor used. Since the response speed of the light receiving element is equal to that of the light receiving element, the half-addition operation time for one time becomes about 0.1 ns by using a high-speed response MSM-PD. The parallel type full addition operation only adds the half addition operation time for the number of bits and the propagation delay time of the electric signal, the response time of the semiconductor light emitting element, and the propagation delay time of the optical signal to the light emitting element. By using a semiconductor laser such as a light emitting laser and by modularizing the whole to minimize the signal propagation time, the total addition operation time for 1 bit is
A very high-speed arithmetic system of about 0.3 to 0.5 ns can be realized.

In the parallel type full-addition photoelectric logic operation system described here, the size of the semiconductor substrate is increased by the number of bits as compared with the so-called serial type system described above, and the entire system is increased accordingly. Although it will be,
This parallel operation method is suitable when optical input data processing having a spatial spread such as two-dimensional image processing is required. Further, in this system, the photoelectric half-addition logic operation circuit used here is the SUM that is the operation result.
Since it is possible to output the electric signals of and CARRY at exactly the same time, it is very effective to use this system as a carry-save parallel full-addition photoelectric logic operation system. This operation method is often used in a multiplication circuit, but in the case where it is generally composed of an electronic circuit, that is, only a transistor, the outputs of SUM and CARRY do not occur at the same time, so it is necessary to incorporate a complicated timing circuit. Since this is not necessary here as described above, the multiplication circuit can be configured very easily, and the calculation speed can be increased accordingly. In general, a signal delay circuit such as a shift register, which is often required when performing complex operations such as four arithmetic operations, is easily introduced into the photoelectric logic operation system by using a signal loop in each unit operation block. be able to.

Further, in such a parallel type full adder circuit, since the carry (CARRY) signal of each bit is transferred to the input gate of the adjacent upper bit, it is output as an electric signal as a result of the operation. The carry signal to be input is directly connected to the adjacent higher-order bits and input, and does not necessarily have to be converted into an optical signal. That is, the advantage of the optical output signal dealt with in this patent is that the optical signal is superior in many points when it is transferred from a certain unit operation block to a unit operation block in another photoelectric logic operation board in the next stage. However, the signal transfer inside the same logical operation board, that is, the internal carry signal does not have to be converted into an optical signal. In this patent, the concept of the optical signal input / output is also intended to serve as the optical wiring to the next-stage photoelectric logic operation board. Therefore, as in this case, the carry signal is transferred without being converted into the optical signal. Also in the case, if the SUM electric signal is converted into an optical signal and is input to the next stage as an optical signal, it is included in the present invention.

[0047]

According to the present invention, the semiconductor substrate on which the semiconductor light receiving element and the semiconductor light emitting element are integrated is spatially arranged so as to be optically coupled to each other to form a signal loop. , Complex logical operations such as full addition operations using optical signals can be realized with a simple configuration.
In particular, in the present invention, the input / output system of the optical signal is spatially distributed, and the path is simplified, so that a complicated optical system,
Another feature is that complicated control for each clock is no longer necessary. As a result, it is expected that the operation speed will be further increased and that the attenuation of the optical signal in the operation system will be significantly reduced. For this reason, it is expected that a large-scale parallel arithmetic system can be substantially realized by spatially arranging the arithmetic systems, and its effect will be maximized especially in image arithmetic processing. It

[Brief description of drawings]

FIG. 1 shows a basic configuration of an integrated photoelectric logic operation system according to the present invention.

FIG. 2 shows a typical element structure of MSM-PD, which is optimum as a semiconductor light receiving element used for an integrated optoelectronic logic operation substrate in the present invention.

FIG. 3 is a view showing a typical device structure of a surface emitting laser, which is most suitable as a semiconductor light emitting device used for an integrated optical signal output substrate in the present invention.

FIG. 4 is a conceptual diagram of an integrated circuit in the case where the integrated optoelectronic logic operation board of the present invention is configured by integrating the MSM-PD on a semiconductor substrate. ..

FIG. 5 is a conceptual diagram of an integrated circuit in a case where an integrated optical signal output substrate is configured by integrating a surface emitting laser on a semiconductor substrate in the integrated photoelectric logic operation system according to the present invention. ..

FIG. 6 shows an integrated circuit in an integrated optoelectronic operation system according to the present invention, in which an optoelectronic logic operation board and an optical signal output board are integrated together by using an MSM-PD and a surface emitting laser on a semiconductor substrate. It is a conceptual diagram.

FIG. 7 shows an integrated optoelectronic logic operation system according to the present invention, in which an optoelectronic logic operation board and an optical signal output board are integrated on a semiconductor substrate by using an MSM-PD and a surface emitting laser, and FIG. 7 is a conceptual diagram showing another integrated optical signal output substrate for feedback, which is face-to-face overlapped and adhered and fixed so as to satisfy the optical coupling relationship corresponding to each other.

FIG. 8 shows a configuration example of an integrated photoelectric logic operation system according to the present invention.

FIG. 9 shows a configuration example of an integrated photoelectric logic operation system according to the present invention.

FIG. 10 shows an embodiment in the case of performing a full addition operation as an integrated photoelectric logic operation system according to the present invention.

11 shows a flowchart of the full addition arithmetic system shown in FIG.

FIG. 12 is a parallel-type integrated optoelectronic logic operation system according to the present invention, which is configured by integrating the operation system as shown in FIG. 1 into one unit, and spatially arranging and integrating the operation systems. 1 shows a basic configuration of an integrated photoelectric logic operation system.

FIG. 13 shows an embodiment in the case of performing a full addition operation as a parallel type integrated photoelectric logic operation system in the present invention.

14 shows a flowchart of the full addition arithmetic system shown in FIG.

FIG. 15 is an optical operation system configured by combining a spatial light modulator with a light emitting element array and a light receiving element array.

FIG. 16 is a photoelectric half addition arithmetic circuit configured using a semiconductor light receiving element.

FIG. 17 is also formed by using a semiconductor light receiving element,
It is a photoelectric half addition arithmetic circuit.

FIG. 18 is an example of an integrated circuit when the photoelectric half-addition arithmetic circuit shown in FIG. 16 is integrated on a semiconductor substrate.

FIG. 19 is an example of an integrated circuit when the photoelectric half-addition arithmetic circuit shown in FIG. 17 is integrated on a semiconductor substrate.

FIG. 20 is a block diagram of a photoelectric full addition arithmetic system configured using the photoelectric half addition arithmetic circuit shown in FIGS. 16 and 17 and a latch memory.

FIG. 21 is a photoelectric exclusive OR (XOR) operation gate array including a semiconductor light receiving element, and a photoelectric AND (AN).
D) By arranging the operation gate array on a plane, arranging the semiconductor laser array on the other plane, and optically coupling them by using a half mirror, the optical signal is returned. It is a figure which shows the photoelectric full addition arithmetic system implement | achieved.

FIG. 22 is a diagram illustrating a photoelectric exclusive OR (XOR) operation gate and a photoelectric AND (AND) operation gate each including a semiconductor light receiving element arranged on a plane together with a semiconductor light emitting element, and using a corner cube to return an optical signal. 2 is a diagram showing a photoelectric full addition arithmetic system that is realized by including a memory function by being configured to perform.

[Simple explanation of symbols]

1 ... integrated photoelectric logic operation board 11, 12 ... operation circuit portion _{11 1 ~11 n, 12 1 ~12} 2, 13,14 ... photoelectric conversion gate 2,2 _1, 2 ₂ ... integrated optical signal output board 21, 21 _{1 to} 21 _n , 22, 22 _{1 to} 22 _n , 23,
24,25 ... semiconductor light-emitting element 3 _1, 3 ₂ ... electric wiring 4,4 ₁ ... semiconductor substrate 4 ₂ ... active regions 5 _1, 5 ₂ ... Schottky electrode 6 ... insulating film 7 ₁ ... multilayer mirror 7 ₂ … Reflector 8, 8 ₁ to 8 _n … Semiconductor light receiving element 9… Conductor thin film electrode 10… Corner cube

Front page continuation (72) Inventor Takashi Iida 1 1126 Ichinomachi, Hamamatsu, Shizuoka Prefecture 1126 Hamamatsu Photonics Co., Ltd. (72) Inventor Sadahisa Warashi 1 1126 1 Nonomachi, Hamamatsu City, Shizuoka Prefecture 1 Hamamatsu Photonics Co., Ltd. (72) Inventor Kenichi Sugimoto, 1 Hamamatsu Photonics Co., Ltd., 1126 Nomachi, Hamamatsu, Shizuoka Prefecture (72) Inventor Tomoko Suzuki 1 1126, Ichinocho, Hamamatsu, Shizuoka Prefecture Hamamatsu Photonics Co., Ltd. (72) Invention Hirofumi Suga 1 Hamamatsu Photonics Co., Ltd. 1 1126 Nomachi, Hamamatsu City, Shizuoka Prefecture

Claims (12)

[Claims] 1. A semiconductor light receiving element is used as an input photoelectric conversion gate, and a plurality of these gates are arranged on a semiconductor substrate. Depending on the wiring between these gates or the polarity and size of a bias power supply applied to each gate, A photoelectric logic operation circuit for performing a predetermined logic operation by inputting an optical signal, an integrated optoelectronic logic operation board in which a plurality of sets are integrated, and a plurality of semiconductor light emitting elements are integrated and arranged on the semiconductor substrate, One or more integrated optical signal output boards for converting these operation results into optical signals and outputting the signals, and electrically connecting these integrated optoelectronic logic operation boards and the integrated optical signal output boards. The integrated optical signal output base provided for inputting a part of the optical output signal obtained by the logical operation to the photoelectric logic operation circuit in the integrated photoelectric logic operation board again by the electric wiring of The board is arranged so that the light-emitting elements therein have a geometrical optical coupling relationship with the corresponding input photoelectric conversion gates of the integrated optoelectronic logic operation board, thereby providing an integrated circuit having optical signal feedback means. The optoelectronic logic operation system and multiple unit operation blocks are arranged in parallel, and the unit operation blocks are optically coupled to each other so that a part of each optical output signal is input in cascade. By doing so, by simultaneously inputting optical signals of a plurality of bits, logical operations are simultaneously performed in parallel.
Parallel integrated photoelectric logic operation system. 2. The integrated circuit according to claim 1, wherein an integrated optical signal output board provided for returning an optical signal in the unit operation block is arranged to face the integrated optoelectronic logic operation board. Optoelectronic logic operation system. 3. A unit operation block is provided with means for branching and outputting a part of the integrated optical signal output substrate into two sets, one of which outputs the operation result to the outside of the unit operation block. The integrated optoelectronic logic operation system according to claim 1, wherein the integrated optoelectronic logic operation system is used only for the purpose of returning the operation result to the unit operation block. 4. The integrated optoelectronic logic operation system according to claim 1, wherein the semiconductor light receiving element has a substantially bilaterally symmetric electrode structure formed by arranging Schottky junctions facing each other on a semiconductor substrate. 5. The integrated photoelectric logic operation system according to claim 1, wherein the semiconductor light emitting device is a surface emitting laser. 6. A structure in which a part or all of an integrated optoelectronic logic operation board and an integrated optical signal output board are monolithically integrated on the same semiconductor substrate, including electrical wiring for electrically connecting them. 2. The integrated photoelectric logic operation system according to claim 1, wherein an optical signal is input to one surface of the semiconductor substrate and an optical signal is output from the other surface. 7. An integrated optoelectronic logic operation board and an integrated optical signal output board are integrated monolithically on the same semiconductor substrate, including electric wirings for electrically connecting them, and signals are integrated therein. 2. The integrated optoelectronic logic operation system according to claim 1, wherein another integrated optical signal output substrate for returning between the substrates is superposed and fixed so as to face each other so as to satisfy the optical coupling relation corresponding to each other. 8. The integrated photoelectric logic operation system according to claim 1, wherein a semi-insulating GaAs substrate, a semi-insulating InP substrate, or a GaP substrate is used as the semiconductor substrate. 9. A means for receiving an optical input signal of a plurality of bits in parallel and arranging the bit signals in parallel in a logic circuit, and an optical output signal in parallel for outputting a plurality of bits. 2. The integrated optoelectronic logic operation system according to claim 1, including means for array processing. 10. A CA configured to perform half addition operation in an integrated optoelectronic logic operation board, output as the operation result, and converted by an integrated optical signal output board.
The RRY optical signal is temporarily stored by the signal circulation function by the feedback between the integrated circuit boards and is inputted again to the half addition operation circuit section in the integrated photoelectric logic operation board. The integrated photoelectric logic operation system according to claim 1, wherein 11. A circuit configured to perform a half addition operation in an integrated photoelectric logic operation board, which is output as a result of this operation and converted by an integrated optical signal output board.
The RRY optical signal is arranged in parallel and optically cascade-coupled, and is input to the photoelectric half-addition operation circuit portion in the unit operation block of 1-bit higher order. The integrated photoelectric logic operation system according to claim 1, wherein 12. A CARRY electric signal of a calculation result by parallel optical signal input is converted into an optical signal without conversion into an optical signal.
2. The integrated optoelectronic logic operation system according to claim 1, wherein the integrated optoelectronic logic operation system is used as an electric signal input of an operation gate having a higher bit.