JPH0537146A - Wiring board - Google Patents

Abstract

PURPOSE:To correctly mount electronic parts without causing displacement of parts or generation of defective soldering on the occasion of mounting electronic parts. CONSTITUTION:In a wiring board where a wiring pattern 2 formed by patterning of a conductive layer is provided on an insulating base material 1, a through hole formed as a conductor is provided in the necessary areas, a land 4 extending from a wiring pattern 2 is also formed by a conductor at the chip parts mounting region and solder resist 5 is formed to the region except for the land 4, a solder layer 6 having protruded and recessed regions is formed on the land 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board having a land formed on its surface by a conductor layer on which an electronic component such as a semiconductor chip is mounted.

[0002]

2. Description of the Related Art Conventionally, as a method of joining semiconductor chips, a method of connecting an IC formed by sealing a semiconductor chip in a resin package to a printed wiring board has been generally used. However, when the wiring pattern of the printed wiring board has a fine pitch, the above method has a problem that the mounting density cannot be increased. Therefore, at present, the mounting density is improved by directly connecting the semiconductor chip to the printed wiring board.

As a method of directly bonding a semiconductor chip to a wiring board, a wire bonding method using a gold wire or a method of forming bumps on the wiring board or the semiconductor chip and connecting the semiconductor chips via the bumps (bump method) ). Since the former wire bonding method is inferior in workability and packaging density to the latter bump method, the latter bump method is now drawing attention as a technique for increasing the packaging density.

Specifically, the bump method is to face the wiring board with the active surface (front surface) of the semiconductor chip facing downward, and to electrically connect both connection points via the bumps. (Face down joining method).

In a conventional wiring board, as shown in FIG. 9, a eutectic solder 23 having a thickness of, for example, about 3 to 5 μm is formed on a land 22 formed of a conductor layer formed on an insulating base material 21. . Incidentally, 24 is a solder resist.

When the semiconductor chip C with bumps is mounted on the wiring board, the semiconductor chip C is placed on the land 22 of the wiring board, and then reflow processing is performed at a temperature at which the eutectic solder 23 melts. The eutectic solder 23 is melted to electrically connect the bumps 25 of the semiconductor chip C to the lands 22 on the wiring board.

[0007]

However, in the conventional wiring board, the eutectic solder 23 is formed on the land 22 by using, for example, a deposition method such as plating. Therefore, as shown in FIG. The eutectic solder 23 is the land 2
It is formed in a substantially hemispherical shape on 2. Therefore, when the semiconductor chip C is mounted, the semiconductor chip C
There was a problem that the position of was easily displaced. In particular, there is a drawback in that the semiconductor chip C moves on the eutectic solder 23 during the reflow process performed when the semiconductor chip C is mounted, and the semiconductor chip C is easily displaced. This misalignment also occurred during transportation.

Also, the bumps 25 of the semiconductor chip C are usually used.
However, the hemispherical eutectic solder 23 cannot absorb the variation when the semiconductor chip C is mounted. Between the bumps 25 of the semiconductor chip C,
There is a problem in that soldering defects are likely to occur and the reliability of the wiring board on which the semiconductor chip C is mounted is significantly deteriorated.

When the semiconductor chip C is mounted on the wiring board, the position of the land 22 is checked by image processing or the like. When the hemispherical eutectic solder 23 is formed on the land 22, the accuracy of There was an inconvenience that it was difficult to grab a certain position.

The present invention has been made in view of the above problems. An object of the present invention is to mount a semiconductor chip without causing misalignment of the semiconductor chip and causing soldering failure. An object of the present invention is to provide a wiring board on which a semiconductor chip can be satisfactorily mounted without causing the above problem.

[0011]

According to the present invention, an uneven conductor layer (solder layer 6) is provided on the land 4 in a wiring board having a land 4 on which an electronic component C is mounted. Constitute.

Further, the present invention provides the above wiring board,
The land 4 itself is formed to have an uneven shape.

[0013]

According to the first configuration of the present invention described above, the land 4
Since the uneven conductor layer (solder layer 6) is provided on the upper surface of the electronic component C, the conductor layer 6 surrounds the connecting portion (bump 10) of the electronic component C, unlike the conventional hemispherical solder. Can be implemented. Therefore, it is possible to prevent the position of the electronic component C from being displaced when the electronic component C is mounted, and to prevent the electronic component C from being reflowed.
The phenomenon that the vehicle moves on the land 4 is also avoided. Of course, it is possible to prevent the position shift of the electronic component C during transportation.

Since the conductor layer 6 formed on the land 4 has an uneven shape, the conductor layer 6 is used as a positioning mark when the electronic component C is positioned with respect to the land 4. be able to. That is, for example, when the position of the land 4 is searched for by image processing, the position of the land 4 is easily recognized because the conductor layer 6 has an uneven shape. Therefore, the conductor layer 6 itself can be effectively used as a positioning mark. Therefore, in the case of the present invention, the electronic component C
Can be mounted on the land 4 with high accuracy.

In general, the height (height) of the connecting portion (bump 10) of the electronic component C varies due to manufacturing. However, when the electronic component C is mounted, the unevenness is caused by the uneven conductor layer 6. Since it can be absorbed, soldering failure between the land 4 of the wiring board and the connection portion (bump 10) of the electronic component C is less likely to occur.

From the above, according to the wiring board of the present invention, when the electronic component C is mounted, the electronic component C is not displaced and the soldering failure does not occur. The component C can be mounted well, and the reliability of the wiring board on which the electronic component C is mounted can be significantly improved.

Further, according to the above-mentioned second structure of the present invention, since the land 4 itself is formed in an uneven shape, the shape of the solder layer 6 formed on the land 4 is also the shape of the land 4. Is reflected to form an uneven shape. Therefore, also in this configuration, similarly to the first configuration, when the electronic component C is mounted, the electronic component C is prevented from being displaced and the soldering failure is not caused. It can be mounted well, and the reliability of the wiring board on which the electronic component C is mounted can be significantly improved.

[0018]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a configuration diagram showing a main part (a connection part of an electronic component) of a wiring board according to the first embodiment.

This wiring board has a wiring pattern 2 formed by patterning a conductor layer on an insulating base material 1 and conductive through-holes 3 at required positions thereof. In the component mounting portion, a large number of lands (in the illustrated example, one land is representatively shown as one) 4 extending from the wiring pattern 2 are also formed of a conductor layer. A portion other than the land 4 (including the through hole 3) is covered with a solder resist 5.

In this example, however, the solder layer 6 having an uneven shape is formed on the exposed land 4. 2A, for example, as shown in FIG. 2A, in the solder layer 6 having a rectangular outer shape, two convex portions (indicated by diagonal lines) 6a are provided on both left and right sides thereof, and a concave portion 6b is provided in the center. It may be shaped, or as shown in FIG. 2B, a planar L-shaped convex portion 6a may be provided and two concave L-shaped inner sides may surround a part of the concave portion 6b. Further, as shown in FIG. 2C, the central concave portion 6b may be formed so as to be surrounded by the convex portion 6a formed in a planar frame shape.

The outer shape of the land 4 (and the solder layer 6) is not limited to the above-mentioned rectangular shape and may be a circular shape. Also, the uneven shape of the solder layer 6 is only an example in the example shown in FIG. 2, and various shapes are conceivable.

Next, an example of the method of forming the wiring board according to the first embodiment will be described with reference to FIGS. The same reference numerals are given to those corresponding to FIG.

First, as shown in FIG. 3A, the insulating base material 1
A copper-clad substrate 8 having copper foils 7 formed on both surfaces thereof is prepared, and through holes 3 are formed at required positions of the copper-clad substrate 8. Then, electroless plating and copper plating are applied to the copper-clad substrate 8 to form a copper plating layer 9 on the entire surface including the through holes 3. Then, the copper plating layer 9 and the copper foil 7 below it are patterned to form the wiring pattern 2 and the land 4 extending from the wiring pattern 2 on the insulating base material 1.

Next, as shown in FIG. 3B, a solder resist 5 is formed on the entire surface except the land 4. Then, the exposed land 4 is selectively coated with the solder layer 6b.

Next, as shown in FIG. 3C, a resist film 9 is formed only on a part of the surface of the solder layer 6b formed on the land 4. After that, the solder layer 6a is coated on the exposed solder layer 6b by, for example, solder plating or Dip. Here, the portion of the solder layer 6a becomes a convex portion, and the portion of the solder layer 6b below the resist film becomes a concave portion.

Next, as shown in FIG. 4, the solder layer 6b is formed.
The upper resist film 9 is peeled off to obtain the wiring board according to the first embodiment.

According to the first embodiment, since the uneven solder layer 6 is provided on the land 4, unlike the conventional hemispherical solder, as shown in FIG. The chip C can be mounted by surrounding the bump 10 with the solder layer 6. Therefore, it is possible to prevent the position of the semiconductor chip C from being displaced when the semiconductor chip C is mounted, and to avoid the phenomenon that the semiconductor chip C moves on the land 4 in the reflow process. Of course, semiconductor chip C during transportation
It is also possible to prevent the position shift of.

Since the solder layer 6 formed on the land 4 has an uneven shape, this solder layer 6 is used as a positioning mark when the semiconductor chip C is positioned with respect to the land 4. be able to. That is, for example, when the position of the land 4 is searched by image processing, the position of the land 4 is easily recognized because the solder layer 6 formed on the upper layer of the land 4 has an uneven shape. Therefore, the solder layer 6 itself can be effectively used as a positioning mark. Therefore, in the case of the wiring board according to the first embodiment, the semiconductor chip C can be mounted on the land 4 with high accuracy.

In addition, the bump 10 of the semiconductor chip C is usually used.
Although there is a manufacturing variation in the height, the unevenness can be absorbed by the uneven solder layer 6 when the semiconductor chip C is mounted. Therefore, the land 4 of the wiring substrate and the semiconductor chip C can be absorbed. Soldering failure between the bumps 10 is less likely to occur.

From the above, according to the wiring board of the first embodiment, when the semiconductor chip C with bumps is mounted, the misalignment of the semiconductor chip C is not caused and the soldering failure occurs. Without letting
The semiconductor chip C can be mounted well, and the reliability of the wiring board on which the semiconductor chip C is mounted can be greatly improved.

In the first embodiment described above, the solder layer 6 having an uneven shape was formed on the land 4, but next, a second embodiment in which the land 4 itself has an uneven shape is shown in FIGS.
This will be described with reference to FIG. The same reference numerals are given to those corresponding to FIG.

In the wiring board according to the second embodiment, as shown in FIG. 5, the land 4 itself has an uneven shape. Then, the solder layer 6 is formed on the land 4 formed in the uneven shape.
Are formed and configured. The solder layer 6 is formed in an uneven shape similar to the land 4 by directly reflecting the shape of the lower land 4.

Next, a method of forming the wiring board according to the second embodiment will be described with reference to FIGS. 6 and 7.

First, as shown in FIG. 6A, the insulating base material 1
A copper-clad substrate 8 having copper foils 7 formed on both surfaces thereof is prepared, and through holes 3 are formed at required positions of the copper-clad substrate 8. Then, the copper foil 7 of the copper-clad substrate 8 is patterned to form the wiring pattern 2 and the land 4 extending from the wiring pattern 2 on the insulating base material 1.

Next, as shown in FIG. 6B, after the resist film 11 is formed on the entire surface, the resist film 11 at a desired portion on the land 4 is removed to form an opening 11a.

Next, as shown in FIG. 6C, electroless plating and copper plating are applied. At this time, the copper plating layer 9 is formed only on the inner wall of the through hole 3 and the land 4 exposed from the opening 11a.

Next, as shown in FIG. 7A, the resist film 1
1 is peeled off. At this time, the land 4 has a shape in which the land 4 itself is formed in an uneven shape by the copper plating layer 9 formed in FIG. 6C.

Next, as shown in FIG. 7B, a solder resist 5 is formed on the entire surface except the land 4. Then, the exposed land 4 having an uneven shape is coated with a solder layer 6 by, for example, solder plating or Dip to obtain a wiring board according to the second embodiment. At this time, the solder layer 6
Are formed in an uneven shape along the shape of the lower land 4.

According to the second embodiment, since the land 4 itself is formed in an uneven shape, the shape of the solder layer 6 formed on the land 4 also reflects the shape of the land 4 and is uneven. Becomes Therefore, also in this example, when mounting the semiconductor chip C, as in the first embodiment,
The semiconductor chip C can be satisfactorily mounted without causing the positional displacement of the semiconductor chip C and without causing the soldering failure, and the reliability of the wiring board on which the semiconductor chip C is mounted is significantly improved. You can

By the way, in the first and second embodiments, all the lands 4 corresponding to the bumps 10 of the semiconductor chip C may be formed in an uneven shape. However, as shown in FIG. Lands 4c corresponding to the bumps 10c formed at the corners of the bumps 10 of the chip C
Only (and the solder layer 6c) may be formed in an uneven shape. In addition, in FIG. 8, a hatched portion indicates a convex portion.

[0041]

According to the wiring board of the present invention, when an electronic component is mounted, the electronic component is satisfactorily mounted without causing displacement of the electronic component and without causing soldering failure. be able to.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a main part (a connection part of an electronic component) of a wiring board according to a first embodiment.

FIG. 2 is a plan view showing an example of an uneven shape of a solder layer.

FIG. 3 is a process diagram (1) showing the method for forming a wiring board according to the first embodiment.

FIG. 4 is a process diagram (No. 2) showing the method for forming the wiring board according to the first embodiment.

FIG. 5 is a configuration diagram showing a main part (a connection part of an electronic component) of a wiring board according to a second embodiment.

FIG. 6 is a process drawing (1) showing a method for forming a wiring board according to a second embodiment.

FIG. 7 is a process diagram (part 2) showing the method of forming the wiring board according to the second embodiment.

FIG. 8 is a plan view showing an example of a land (and solder layer) formation pattern for bumps of a semiconductor chip.

FIG. 9 is a configuration diagram showing a main part (a connection part of an electronic component) of a wiring board according to a conventional example.

[Explanation of symbols]

1 Insulating base material 2 wiring pattern 3 through holes 4 lands 5 Solder resist 6 Solder layer 6a convex part 6b recess 10 bumps C semiconductor chip

Claims (2)

[Claims] 1. A wiring board having a land on which an electronic component is mounted is formed on a surface of the wiring board, wherein a conductor layer having an uneven shape is provided on the land. 2. A wiring board having a land on which an electronic component is mounted is formed on a surface thereof, wherein the land itself has an uneven shape.