JPH0536915A - Insulated gate type field effect transistor and semiconductor device using the same - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which can operate at a high speed, has no latchup, etc., and excellent radiation resistant characteristic by manufacturing an insulated gate type field effect transistor in which stray capacitances of a source and a drain are reduced. CONSTITUTION:Single crystalline layers 4, 5 for constituting at least channel regions of insulated gate type field effect transistors 2, 3 are formed of single crystalline semiconductor layers on a light transmission base 1 obtained by removing in steps of adhering a surface of a nonporous single crystalline layer on a silicon base made porous or an oxidized surface of a nonporous single crystalline layer to the base 1 and then etching the silicon base made porous at least by wet chemical etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor and a semiconductor device using the same, and particularly to an insulated gate field effect transistor in which an insulated gate field effect transistor is formed on a light transmissive insulator substrate. The present invention relates to an effect transistor and a semiconductor device using the same.

[0002]

2. Description of the Related Art The formation of a single crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique, and is unattainable in a bulk Si substrate for producing an ordinary Si integrated circuit. Much research has been done because the device utilizing the SOI technology has an advantage. In other words, by using SOI technology,
． Dielectric isolation is easy and high integration is possible. Excellent radiation resistance ,. Stray capacitance is reduced and speedup is possible. The well process can be omitted. Latch-up can be prevented. Advantages such as a fully depleted field effect transistor can be obtained by thinning the film.

In order to realize the many advantages in device characteristics as described above, a method for forming an SOI structure has been researched for several decades. This content is, for example, Special Issue: "Single-crystal silicon on n
on-single-crystal insulators "; edited by GWCulle
n, Journal of Crystal Growth, volume 63, no3, pp 4
29-590 (1983).

Further, SOS (silicon on sapphire) formed by heteroepitaxy Si by CVD (chemical vapor deposition) on a single crystal sapphire substrate has been known for a long time, and is the most mature SOI. Although the technology was successful for the time being, a large number of crystal defects due to the lattice mismatch between the Si layer and the underlying sapphire substrate interface, the mixing of aluminum from the sapphire substrate into the Si layer, and above all, the high cost and large size of the substrate. The delay in making the area hinders its widespread application. In recent years, attempts have been made to realize an SOI structure without using a sapphire substrate. This attempt is roughly divided into the following two. (1) After the surface of the Si single crystal substrate is oxidized, a window is opened and Si is
The substrate is partially exposed and laterally epitaxially grown using the portion as a seed to form a Si single crystal layer on SiO ₂ (in this case, Si layer is deposited on SiO ₂ ). (2) Using the Si single crystal substrate itself as the active layer,
SiO ₂ is formed thereunder (this method does not involve deposition of a Si layer).

Various semiconductor devices and integrated circuits made of them have been formed on a silicon layer on an insulator formed by these methods.

[0006]

As means for realizing the above (1), a single crystal layer Si is directly formed by a CVD method.
Lateral epitaxial growth, amorphous Si deposition, and solid phase lateral epitaxial growth by heat treatment, electron beam on the amorphous or polycrystalline Si layer,
A method of converging and irradiating an energy beam such as a laser beam to grow a single crystal layer on SiO ₂ by melting and recrystallization, and a method of scanning a melting region in a band shape with a rod heater (Zone melting recrystallization) are known. ing. Each of these methods has advantages and disadvantages,
There are still many problems in its controllability, productivity, uniformity, and quality, and none has been industrially put to practical use. For example, the CVD method requires sacrificial oxidation to achieve a flat thin film, and the solid phase growth method has poor crystallinity. Further, the beam annealing method has problems in processing time by convergent beam scanning, controllability such as beam overlapping and focus adjustment. Of these, the Zone Melting Recrystallization method is the most mature, and relatively large-scale integrated circuits have been prototyped, but crystal defects such as sub-grain boundaries still occur.
Majority remains and has not led to the creation of minority carrier devices. Moreover, since neither method requires a Si substrate, a good quality Si single crystal layer cannot be obtained on a transparent amorphous insulator substrate such as glass.

In the method (2) above, in which the Si substrate is not used as seeds for epitaxial growth, there are the following three types of methods.

[0008] An oxide film is formed on a Si single crystal substrate in which V-shaped grooves are anisotropically etched on the surface, a polycrystalline Si layer is deposited on the oxide film to be as thick as the Si substrate, and then polished from the back surface of the Si substrate. Is a method for forming a Si single crystal region surrounded by V-grooves and dielectrically isolated on a thick polycrystalline Si layer. In this method, the crystallinity is good, but the step of depositing polycrystalline Si to a thickness of several hundreds of microns, and
This requires a step of polishing the single crystal Si substrate from the back surface to leave only the separated Si active layer, which is problematic in terms of controllability and productivity.

[0009]. SIMOX: Seperati
This is a method of forming a SiO ₂ layer by ion implantation of oxygen in a Si single crystal substrate called “on by ion implanted oxygen”, which is the most mature method at present because it has good compatibility with the Si process. However, in order to form the SiO ₂ layer, oxygen ions are added at 10 ¹⁸ ions / cm ^2.
It is necessary to implant the above, the implantation time is long, the productivity cannot be said to be high, and the wafer cost is high. Further, many crystal defects remain, and from an industrial point of view, the quality is not sufficient to produce a minority carrier device.

[0010]. This is a method of forming an SOI structure by dielectric isolation by oxidation of porous Si. This method is
Ion implantation of N-type Si layer on the surface of type Si single crystal substrate (Imai et al., J. Crystal Growth, vol 63, 547 (1983)),
Alternatively, it is formed into an island shape by epitaxial growth and patterning, and only the P-type Si substrate is made porous by an anodization method in a HF solution so as to surround the Si island from the surface, and then the N-type Si island is increased by accelerated oxidation. It is a method of dielectric separation. This method has a problem that the separated Si region is determined before the device process, which may limit the degree of freedom in device design.

By the way, forming a semiconductor element on a light-transmissive substrate is important in constructing a contact sensor, which is a light-receiving element, and a projection type liquid crystal image display device. In addition, pixels (pixels) of sensors and display devices
In order to achieve higher density, higher resolution, and higher definition, extremely high performance drive elements are required. In addition, the number of terminals of the switching element for switching the pixel and its drive circuit and peripheral circuit becomes enormous, and the connection between them after making them separately becomes a density that is no longer possible by mechanical connection. As a result, it is desirable that the semiconductor device and the peripheral drive circuit are formed in the same substrate by the same process, and the mutual connection is performed in a normal integrated circuit. Moreover, it should be formed by patterning a conductive thin film, and only then can high-density mounting be possible. Further, from the inevitable industrial demand for higher performance of products to be produced, it is necessary to produce a device provided on a light transmissive substrate by using a single crystal layer having excellent crystallinity.

However, on a light-transmissive substrate typified by glass, in general, only a polycrystalline layer is formed, which is amorphous or good, reflecting the disorder of the crystal structure, and the defect Due to the large number of crystal structures, it has been difficult to fabricate a driving element having sufficient performance required or required in the future. This is due to the fact that the crystal structure of the substrate is amorphous, and simply depositing a Si layer will not yield a good-quality single crystal layer. When a semiconductor element or the like is formed on a light transmissive substrate, any of the above methods using a Si single crystal substrate is unsuitable for the purpose of obtaining a good quality single crystal layer on the light transmissive substrate. Is.

The present invention is a field effect transistor which is a basic unit of an integrated circuit which can be formed on a high quality single crystal semiconductor layer on a light-transmitting insulator substrate which can meet the above problems and the above requirements. , And an integrated circuit comprising them.

[0014]

According to another aspect of the present invention, there is provided an insulated gate field effect transistor comprising a non-porous silicon substrate on which a single crystal layer constituting at least a channel region of the insulated gate field effect transistor is made porous. Obtained by adhering the surface of a porous single crystal layer or the oxidized surface of the non-porous single crystal layer to a light-transmitting substrate, and then removing the porous silicon substrate by a step including at least wet chemical etching. Another feature is that it is a single crystal semiconductor layer on a light-transmitting substrate.

The semiconductor device of the present invention uses the above-mentioned insulated gate field effect transistor.

It should be noted that the light transmissive substrate includes a substrate provided with a metal electrode, a transparent electrode or the like on its surface.

[0017]

[Operation] Although the density of porous silicon is less than half that of single crystal Si, the single crystallinity is maintained, and it is possible to grow a single crystal Si layer epitaxially on top of the porous layer. It is possible. Further, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half. As a result, the surface area is dramatically increased as compared with the volume, so that the chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

The present invention utilizes such properties of porous silicon to produce a single crystal semiconductor layer on a light-transmissive substrate to produce an insulated gate field effect transistor. That is, the present invention forms a non-porous single crystal layer with excellent crystallinity on a porous silicon substrate, the surface of the non-porous single crystal layer or the oxidized surface of the non-porous single crystal layer After being bonded to a light-transmissive substrate, the porous silicon substrate having an etching rate increased as compared with a normal single crystal layer is removed by a step including at least wet chemical etching to obtain a single crystal semiconductor. A layer is formed, and using this single crystal semiconductor layer, an insulated gate field effect transistor and a semiconductor device using the same are manufactured.

In the present invention, on a Si single crystal layer formed on a light-transmissive substrate, which is excellent in economy, is uniform and flat over a large area, has extremely excellent crystallinity, and has extremely few defects. Since an element is formed in the semiconductor device, an insulated gate field effect transistor with reduced stray capacitance of the source and drain can be manufactured, high-speed operation is possible, a semiconductor device excellent in radiation resistance characteristics without latch-up phenomenon, etc. Can be provided.

[0020]

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic sectional view of an embodiment of a semiconductor device according to the present invention. In the figure, the substrate 1 is a light transmissive substrate (becomes a light transmissive substrate) made of SiO ₂ formed by selectively removing porous Si as described later.

An N-channel field effect transistor 2 and a P-channel field effect transistor 3 are formed on the substrate 1, and a complementary field effect semiconductor device is manufactured by connecting both elements to each other.

The steps of manufacturing the transistors 2 and 3 will be described below with reference to FIGS. 2 and 3 from the step of manufacturing the single crystal semiconductor layer on the light transmissive substrate.

2A to 2C and 3A to 3C.
(D) is a process drawing for explaining the method for manufacturing a semiconductor substrate according to the present invention, and is shown as a schematic cross-sectional view in each process.

According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer, and the density thereof is less than half that of single crystal Si. Nevertheless, single crystallinity is maintained, and it is also possible to epitaxially grow a single crystal Si layer on top of the porous layer. However, 1000 ° C
In the above, rearrangement of the internal holes occurs and the characteristics of the enhanced etching are impaired. Therefore, for epitaxial growth of the Si layer, molecular beam epitaxial growth, plasma CV
Low temperature growth such as D method, thermal CVD method, photo CVD method, bias sputtering method, liquid phase growth method and the like is preferable.

First, a method of epitaxially growing a single crystal layer after making the entire Si-P type substrate porous will be described. As shown in FIG. 2A, first, a Si single crystal substrate is prepared and made porous to form a porous Si single crystal substrate 21. By various growth methods, epitaxial growth is performed on the surface of the porous substrate to form a thin film single crystal layer 2
Form 2. The Si substrate is made porous by an anodization method using an HF solution. This porous Si layer has a density of 1.1 to 0.6 g / cm ³ by changing the density of the single crystal Si from 2.33 g / cm ³ to an HF solution concentration of 50 to 20%. It can be changed in the range of ³ . This porous layer is a P-type S for the following reasons.
It is easily formed on the i substrate. According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in this porous Si layer.

Porous Si is described in 1956 by Uhlir et al.
It was discovered in the research process of electropolishing of semiconductors in 2010 (A.
Uhlir, Bell Syst.Tech.J., vol 35, p.333 (1956)). Also, Unagami et al. Studied the dissolution reaction of Si in anodization and reported that the anodic reaction of Si in HF solution requires holes, and the reaction is as follows (T .
Unagami: J. Electrochem. Soc., Vol.127, p.476 (198
0)).

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ^- SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4 -λ) e ⁺ → SiF ₄ + 4H ⁺ + λe ^- SiF ₄ + 2HF → H ₂ SiF ₆ Here, e ⁺ and e ⁻ represent a hole and an electron, respectively. Further, n and λ are the numbers of holes required for dissolving one silicon atom, respectively, and porous silicon is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type silicon in which holes are present is made porous, but N-type silicon is not made porous. The selectivity of this porosification has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Anno, Ohnaka, Kajiwara; IEICE technical report, vol 79, SSD 79-
9549 (1979), (K.Imai; Solid-State Electronics vol2
4,159 (1981)).

However, there is also a report that high-concentration N-type Si is made porous (RP Holmstrom and JY Chi.
Appl.Phys.Lett. Vol.42,386 (1983)), P type and N type, it is important to select a substrate that can realize porosity.

Further, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
The chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

As shown in FIG. 2B, a light transmissive substrate 23 typified by glass is prepared, and the surface of the single crystal Si layer on the porous Si substrate is oxidized. The transparent substrate 23 is attached. The oxide layer plays an important role in making a device. That is, the interface level generated by the underlying interface of the Si active layer can be lower at the oxide film interface level according to the present invention than at the glass interface, and the characteristics of the electronic device are significantly improved. Figure 2
As shown in (b), Si _{3 is used} as an etching prevention film.
An N ₄ layer 25 is deposited to cover the entire two bonded substrates and the Si ₃ N ₄ layer on the surface of the porous silicon substrate is removed. Apiezon wax may be used as another etching prevention film instead of the Si ₃ N ₄ layer. After that, the porous Si substrate 21 is entirely removed by a method such as etching, and the thinned single crystal silicon layer 22 is left on the light transmissive substrate 23 to be formed.

FIG. 2C shows a semiconductor substrate obtained by the present invention. That is, by removing the Si ₃ N ₄ layer 25 as the etching prevention film in FIG. 2B, the single crystal Si layer 22 having the crystallinity equivalent to that of the silicon wafer is flattened on the light transmissive substrate 23. Moreover, the layer is uniformly thinned and formed in a large area over the entire wafer. The semiconductor substrate thus obtained can be suitably used from the viewpoint of manufacturing an electronic element that is insulated and separated.

A selective etching method for electroless wet chemical etching of only porous Si will be described below.

As an etching solution which does not have an etching effect on crystalline Si and can selectively etch only porous Si, hydrofluoric acid, buffered hydrofluoric acid, hydrofluoric acid containing hydrogen peroxide or buffered fluorine is used. A mixed solution of an acid, a mixed solution of hydrofluoric acid or a buffered hydrofluoric acid with an alcohol, and a mixed solution of hydrofluoric acid with a hydrogen peroxide solution and an alcohol or a buffered hydrofluoric acid are preferably used. 4 to 11 show porous S
It is a characteristic view which shows the etching time dependence of the thickness of the porous Si and single crystal Si which were etched when i and single crystal Si were infiltrated in said various etching liquids. The etching liquids are 49% hydrofluoric acid in FIG. 4, FIG. 5 is a mixed liquid of 49% hydrofluoric acid and hydrogen peroxide (1: 5), and FIG. 6 is a mixed liquid of 49% hydrofluoric acid and alcohol ( 10: 1), 49% in Figure 7
Mixture of hydrofluoric acid, alcohol, and hydrogen peroxide (10:
6:50), and FIG. 8 shows buffered hydrofluoric acid and FIG.
Is a mixed solution of buffered hydrofluoric acid and hydrogen peroxide solution (1:
5), FIG. 10 shows a mixed solution of buffered hydrofluoric acid and alcohol (10: 1), and FIG. 11 shows a mixed solution of buffered hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 50). It should be noted that the one to which alcohol was added was infiltrated without stirring, and the one to which alcohol was not added was infiltrated with stirring.

Porous Si is produced by anodizing single crystal Si, and the conditions are as follows. The starting material of porous Si formed by anodization is not limited to single crystal Si, and Si having other crystal structure may be used.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 2.4 ( Time) Thickness of porous Si: 300 (μm) Porosity: 56 (%) The porous Si prepared under the above conditions was infiltrated into the above various etching solutions at room temperature.

When the reduction in the thickness of the porous Si was measured for the one infiltrated in 49% hydrofluoric acid (white circle in FIG. 4) with stirring, the porous Si was rapidly etched,
90 μm in about 40 minutes, and 20 minutes after 80 minutes
Even 5 μm had a high degree of surface property and was uniformly etched.

The reduction in the thickness of the porous Si was measured for the one infiltrated with a mixed solution (1: 5) of 49% hydrofluoric acid and hydrogen peroxide solution (white circle in FIG. 5) with stirring. , Porous Si is rapidly etched, 112 μm in about 40 minutes, and 256 μm in 80 minutes.
It had a high degree of surface properties and was uniformly etched.

Mixed liquid of 49% hydrofluoric acid and alcohol (1
0: 1) (white circles in FIG. 6) infiltrated without stirring, the reduction in the thickness of the porous Si was measured, and the porous Si was rapidly etched to 85 μm in about 40 minutes. , 195 μm after 80 minutes
Also had a high degree of surface properties and was uniformly etched.

The thickness of the porous Si, which was infiltrated in a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (white circles in FIG. 7) without stirring. The porous Si was rapidly etched, and was 107 μm in about 40 minutes, and even 244 μm after 80 minutes had a high degree of surface property and was uniformly etched.

When the reduction in the thickness of the porous Si was measured for the one that was stirred and infiltrated with buffered hydrofluoric acid (white circle in FIG. 8), the porous Si was rapidly etched.
70 μm in about 0 minutes, then 11 after 120 minutes
Even 8 μm had a high degree of surface property and was uniformly etched.

When the mixed solution (1: 5) of buffered hydrofluoric acid and hydrogen peroxide (white circle in FIG. 9) was infiltrated and stirred, the reduction in the thickness of the porous Si was measured.
Porous Si is rapidly etched, and after about 40 minutes 88
.mu.m, and even after lapse of 120 minutes, 147 .mu.m had a high degree of surface property and was uniformly etched.

The decrease in the thickness of the porous Si was measured for the one infiltrated with a mixed solution (10: 1) of buffered hydrofluoric acid and alcohol (white circle in FIG. 10) without stirring. Porous Si is rapidly etched, 4
67 μm in about 0 minutes, and 11 after 120 minutes
Even 2 μm had a high degree of surface property and was uniformly etched.

The thickness of the porous Si in the case of being infiltrated in a mixed solution (10: 6: 50) of buffered hydrofluoric acid, alcohol and hydrogen peroxide solution (white circles in FIG. 11) without stirring. The porous Si was rapidly etched, and it was found that it was 83 μm in about 40 minutes.
After 0 minutes, it had a high surface property of 140 μm and was uniformly etched.

The solution concentration of the hydrogen peroxide solution is 30% here, but it is set at a concentration that does not impair the effect of adding the hydrogen peroxide solution described below and is practically acceptable in the manufacturing process and the like. It As buffered hydrofluoric acid, ammonium fluoride (NH ₄ F) 36.2%, hydrogen fluoride (HF)
A 4.46% aqueous solution is used.

The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid and hydrogen peroxide.
By adding hydrogen peroxide solution, the oxidation of silicon can be accelerated and the reaction rate can be increased as compared with that without addition. By further changing the ratio of hydrogen peroxide solution, the reaction rate can be increased. Can be controlled. Further, by adding alcohol, the bubbles of the reaction product gas due to etching can be instantly removed from the etching surface without stirring, and the porous Si can be uniformly and efficiently etched.

The conditions of solution concentration and temperature are set within a range in which the effect of hydrofluoric acid, buffered hydrofluoric acid and the above hydrogen peroxide solution or the above alcohol is exhibited, and the etching rate is practically acceptable in the manufacturing process and the like.

In the present application, the case of the above-mentioned solution concentration and room temperature was taken up as an example, but the present invention is not limited to such conditions.

The HF concentration in the buffered hydrofluoric acid is set within the range of preferably 1 to 95%, more preferably 1 to 85%, further preferably 1 to 70% with respect to the etching solution. The NH ₄ F concentration in the acid is set within the range of preferably 1 to 95%, more preferably 5 to 90%, and further preferably 5 to 80% with respect to the etching solution.

The HF concentration is preferably set in the range of 1 to 95%, more preferably 5 to 90%, and further preferably 5 to 80% with respect to the etching solution.

The H ₂ O ₂ concentration depends on the etching solution.
It is preferably 1 to 95%, more preferably 5 to 90%, still more preferably 10 to 80%, and is set within a range in which the above hydrogen peroxide solution effect is exhibited.

The alcohol concentration is set to preferably 80% or less, more preferably 60% or less, still more preferably 40% or less with respect to the etching solution, and within the range in which the effect of the alcohol is exhibited.

The temperature is preferably set in the range of 0 to 100 ° C, more preferably 5 to 80 ° C, and further preferably 5 to 60 ° C.

As the alcohol used in the present invention, in addition to ethyl alcohol, isopropyl alcohol and the like which can be used in the manufacturing process and the like and have the above-mentioned alcohol addition effect can be used.

Further, non-porous Si having a thickness of 500 μm was infiltrated into the above various etching solutions at room temperature. Later,
The reduction in thickness of the non-porous Si was measured. Non-porous Si
Was etched less than 100 Å even after 120 minutes.

Porous Si and non-porous Si after etching
The sample was washed with water, and its surface was microanalyzed with secondary ions. No impurities were detected.

Hereinafter, another method for manufacturing a semiconductor substrate according to the present invention will be described in detail with reference to the drawings.

FIGS. 3A to 3D are process drawings for explaining another method for manufacturing a semiconductor substrate according to the present invention, each of which is shown as a schematic sectional view in each process.

First, as shown in FIG. 3A, a low impurity concentration layer 32 is formed on a high concentration silicon single crystal substrate 31 by epitaxial growth by various thin film growth methods.
Alternatively, the surface of the P-type Si single crystal substrate 31 is ion-implanted with protons to form the N-type single crystal layer 32.

Next, as shown in FIG. 3B, P-type Si
The single crystal substrate 31 is transformed from the back surface into a porous Si substrate 33 by an anodization method using an HF solution. This porous Si layer has a density of 1.1 to 0.6 g / cm ³ by changing the density of the single crystal Si from 2.33 g / cm ³ to an HF solution concentration of 50 to 20%. It can be changed into a range. This porous layer is formed on the P-type substrate as described above.

As shown in FIG. 3C, the light transmissive substrate 3
4 is prepared and the light transmissive substrate is attached to the surface of the single crystal Si layer on the porous Si substrate. As shown in FIG. 3C, the porous Si substrate 33 is removed by etching to form a thinned single crystal silicon layer on the light transmissive substrate.

FIG. 3D shows a semiconductor substrate obtained by the present invention. That is, by removing the Si ₃ N ₄ layer 35 as the etching prevention film in FIG. 3C, the single crystal Si layer 32 whose crystallinity is equivalent to that of the silicon wafer is flattened on the light transmissive substrate 34. Moreover, the layer is uniformly thinned and formed in a large area over the entire wafer.

The semiconductor substrate thus obtained can be suitably used from the viewpoint of manufacturing an electronic element which is insulated and separated.

The above is a method of forming an N-type layer before making it porous and then selectively making only the P-type substrate porous by anodization.

Next, the single crystal thin layer 22 or 32 on the surface of the light transmissive substrate thus produced is separated by the partial oxidation method or the island-shaped etching as shown in FIG.
Next, P-type impurity ions are formed on the single crystal silicon island (4 in FIG. 1) in which the N channel transistor (2 in FIG. 1) is to be formed, and single crystal silicon in which the P channel transistor (3 in FIG. 1) is to be formed. N-type impurity ions are independently implanted into the island (5 in FIG. 1).

Next, each single crystal silicon layer (see FIG.
Gate insulating film (6, 7 in FIG. 1) on the gate electrodes (5, 8) in FIG.
9) is patterned and formed.

Source and drain regions are formed by self-aligned ion implantation of impurities using the polycrystalline silicon gate electrode as a mask. A source region (10 in FIG. 1) and a drain region (11 in FIG. 1) are formed by implanting N-type impurity ions into the N-channel transistor (2 in FIG. 1).
For the P-channel transistor (3 in FIG. 1), P-type impurity ions are implanted and the source (1 in FIG.
2) and the drain region (13 in FIG. 1). Source and drain electrodes (14, 15, 16 and 17 in FIG. 1) are formed by depositing and patterning a metal thin film to complete the device. A complementary field effect transistor is manufactured by connecting each element to each other by a thin film electrode.

[0069]

EXAMPLES The present invention will be described below with reference to specific examples. In the examples described below, the case where a mixed solution of 49% hydrofluoric acid, alcohol, and hydrogen peroxide solution (10: 6: 50) is used as an etching solution will be taken as an example. It goes without saying that a liquid can be used as well. (Example 1) A P-type (10
0) The single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time was 8.4 μm / m.
in. And a P-type (10
0) The entire Si substrate became porous in 24 minutes.

MB on the P-type (100) porous Si substrate
E (Molecular Beam Epitaxy)
The Si epitaxial layer was grown at a low temperature of 0.5 μm by the m epitaxy method. The deposition conditions are as follows.

Temperature: 700 ° C. Pressure: 1 × 10 ⁻⁹ Torr Growth rate: 0.1 nm / sec Next, the surface of this epitaxial layer was thermally oxidized by 50 nm. Optically polished fused silica glass substrates were superposed on the thermal oxide film and heated in an oxygen atmosphere at 800 ° C. for 0.5 hours to firmly bond the two substrates.

Si ₃ N ₄ was added to 0.1 by the low pressure CVD method.
The two substrates that have been deposited by μm and bonded to each other are covered, and only the nitride film on the porous substrate is removed by reactive ion etching.

Then, the bonded substrates are mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5).
In 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains unetched,
Porous S using single crystal Si as an etch stop material
The i substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is about a little less than Angstrom, and the selection ratio to the etching rate of the porous layer reaches more than ten to the fifth power, and the etching amount in the non-porous layer (several tens of Angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 0.5 μm could be formed on the quartz glass substrate.

As a result of cross-sectional observation by a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

A field effect transistor was formed on the above single crystal silicon thin film and connected to each other to manufacture a complementary element and its integrated circuit. Since a known MOS integrated circuit manufacturing technique is used for the method of manufacturing each transistor, description thereof will be omitted, and only the method of forming a substantial single crystal semiconductor layer will be described. The same applies to the following examples. (Example 2) P-type (10
0) The single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time was 8.4 μm / m.
in. And a P-type (10
0) The entire Si substrate became porous in 24 minutes. A Si epitaxial layer was grown at a low temperature of 5 microns on the P-type (100) porous Si substrate by a plasma CVD method. The deposition conditions are as follows.

Gas: SiH ₄ High frequency power: 100 W Temperature: 800 ° C. Pressure: 1 × 10 ⁻² Torr Growth rate: 2.5 nm / sec Next, the surface of this epitaxial layer was thermally oxidized to 50 nm. Optically polished glass substrates having a softening point were stacked on the thermal oxide film at around 500 ° C.
By heating at 50 ° C. for 0.5 hour, both substrates were firmly bonded.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

Thereafter, the bonded substrates are mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5).
In 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains unetched,
Porous S using single crystal Si as an etch stop material
The i substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and even after 65 minutes, it was 40.
It is about a little less than Angstrom, and the selection ratio to the etching rate of the porous layer reaches more than ten to the fifth power, and the etching amount in the non-porous layer (several tens of Angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 5 μm could be formed on the low softening point glass substrate. A field effect transistor was formed on the single crystal silicon thin film and connected to each other to manufacture a complementary element and its integrated circuit. A known MOS integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 3) A P-type (10
0) The single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time was 8.4 μm / m.
in. And a P-type (10
0) The entire Si substrate became porous in 24 minutes. On the P-type (100) porous Si substrate, an S
The i-epitaxial layer was grown at a low temperature of 5 microns. The deposition conditions are as follows.

Gas: SiH ₂ Cl ₂ (0.6 1 / min), H ₂ (100 1 / min) Temperature: 850 ° C. Pressure: 50 Torr Growth rate: 0.1 μm / min Next, the surface of this epitaxial layer is It was thermally oxidized to 50 nm. Optically polished glass substrates having a softening point were stacked on the thermal oxide film at around 500 ° C.
By heating at 50 ° C. for 0.5 hour, both substrates were firmly bonded.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

After that, the bonded substrates are mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide (10: 6: 5).
In 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains unetched,
Porous S using single crystal Si as an etch stop material
The i substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low and was 40 even after 65 minutes.
It is about a little less than Angstrom, and the selection ratio to the etching rate of the porous layer reaches more than ten to the fifth power, and the etching amount in the non-porous layer (several tens of Angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 5 μm could be formed on the low softening point glass substrate.

The same effect can be obtained when Apiezon wax or electron wax is coated instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

A field effect transistor was formed on the above-mentioned single crystal silicon thin film and connected to each other to manufacture a complementary element and its integrated circuit. A known MOS integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 4) A P-type (10
0) The single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time was 8.4 μm / m.
in. And a P-type (10
0) The entire Si substrate became porous in 24 minutes. A Si epitaxial layer was grown at a low temperature of 1.0 micron on the P-type (100) porous Si substrate by a bias sputtering method. The deposition conditions are as follows. RF frequency: 100 MHz _Z frequency power: 600W Temperature: 300 ° C. Ar gas pressure: 8 × 10 ^-3 Torr Growth time: 120 minutes Target direct current bias: -200 V substrate direct current bias: + 5V Next, 50 nm Heat the surface of the epitaxial layer Oxidized Optically polished glass substrate and Si substrate having a softening point around 500 ° C. are superposed on the thermal oxide film, and heated at 450 ° C. for 0.5 hours in an oxygen atmosphere to make both substrates strong. Was joined to.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

Thereafter, the bonded substrates were mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5).
In 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains unetched,
Porous S using single crystal Si as an etch stop material
The i substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and the etching rate was 40 even after 65 minutes.
It is about a little less than Angstrom, and the selection ratio to the etching rate of the porous layer reaches more than ten to the fifth power, and the etching amount in the non-porous layer (several tens of Angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 1.0 μm could be formed on the low melting point glass substrate.

Further, the same effect can be obtained when Apiezon wax or electron wax is coated instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

A field effect transistor was formed on the above single crystal silicon thin film and connected to each other to manufacture a complementary element and its integrated circuit. A known MOS integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 5) A P-type (10
0) The single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time was 8.4 μm / m.
in. And a P-type (10
0) The entire Si substrate became porous in 24 minutes. Si was formed on the P-type (100) porous Si substrate by liquid phase epitaxy.
The epitaxial layer was grown at a low temperature of 10 microns. The deposition conditions are as follows.

Solvent: Sn Growth temperature: 900 ° C. Growth atmosphere: H ₂ Growth time: 20 minutes Next, the surface of this epitaxial layer was thermally oxidized by 50 nm. By superposing a glass substrate having a softening point at around 800 ° C., which is optically polished on the thermal oxide film, and a Si substrate, and heating them in an oxygen atmosphere at 750 ° C. for 0.5 hour, both substrates are made strong. Was joined to.

Si ₃ N ₄ was added to 0.1 by the low pressure CVD method.
The two substrates that have been deposited by μm and bonded to each other are covered, and only the nitride film on the porous substrate is removed by reactive ion etching.

Then, the bonded substrates are mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5).
In 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains unetched,
Porous S using single crystal Si as an etch stop material
The i substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 65 minutes.
It is about a little less than Angstrom, and the selection ratio to the etching rate of the porous layer reaches more than ten to the fifth power, and the etching amount in the non-porous layer (several tens of Angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, 10μ on the glass substrate.
A single crystal Si layer having a thickness of m could be formed. Also, S
Apiezon wax instead of i ₃ N ₄ layer, or
The same effect was obtained when the electron wax was coated, and only the porous Si substrate could be completely removed.

A field effect transistor was formed on the above single crystal silicon thin film and connected to each other to manufacture a complementary element and its integrated circuit. A known MOS integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 6) A P-type (10
0) A Si epitaxial layer was grown to 0.5 μm on the Si substrate by the CVD method. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 l / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 1 min. This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . The porosification rate at this time was 8.4 μm / min. And P-type (100) Si with a thickness of 200 microns
The entire substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer did not change.

Next, the surface of this epitaxial layer is exposed to 50
nm thermal oxidation was performed. An optical-polished fused silica glass substrate is placed on the thermal oxide film, and the temperature is set to 800 in an oxygen atmosphere.
By heating at 0.5 ° C. for 0.5 hour, both substrates were firmly bonded.

Si ₃ N ₄ was added to 0.1 by the low pressure CVD method.
Two substrates that had been deposited with a thickness of μm and adhered were covered, and only the nitride film on the porous substrate was removed by reactive ion etching.

Thereafter, the bonded substrates are mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5).
In 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains unetched,
Porous S using single crystal Si as an etch stop material
The i substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is about a little less than Angstrom, and the selection ratio to the etching rate of the porous layer reaches more than ten to the fifth power, and the etching amount in the non-porous layer (several tens of Angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed and S
After removing the i ₃ N ₄ layer, 0.5μ on the glass substrate.
A single crystal Si layer having a thickness of m could be formed. Also, S
Apiezon wax instead of i ₃ N ₄ layer, or
The same effect can be obtained by coating with electron wax, and only the porous Si substrate can be completely removed.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

A field effect transistor was formed on the single crystal silicon thin film and connected to each other to manufacture a complementary element and its integrated circuit. A known MOS integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 7) P-type (10
0) N ions are formed on the surface of the Si substrate by ion implantation of protons.
A type Si layer was formed to 1 micron. H ⁺ injection amount is 5 × 1
It was 0 ¹⁵ (ions / cm ² ). 50% of this board
Anodization was performed in the HF solution. The current density at this time was 100 mA / cm ² . The porosification rate at this time was 8.4 μm / min. The entire P-type (100) Si substrate having a thickness of 200 μm was made porous in 24 minutes. As mentioned above, in this anodization,
Only the P-type (100) Si substrate was made porous, and the N-type Si layer remained unchanged. Next, the surface of this N-type single crystal layer was thermally oxidized by 50 nm. An optical-polished fused silica glass substrate was superposed on the thermal oxide film, and was placed in an oxygen atmosphere at 80
By heating at 0 ° C for 0.5 hours, both substrates are
It was firmly joined.

Si ₃ N ₄ was added to 0.1 by the low pressure CVD method.
The two substrates that have been deposited by μm and bonded to each other are covered, and only the nitride film on the porous substrate is removed by reactive ion etching.

Then, the bonded substrates were mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5).
In 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains unetched,
Porous S using single crystal Si as an etch stop material
The i substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low and was 40 even after 65 minutes.
It is about a little less than Angstrom, and the selection ratio to the etching rate of the porous layer reaches more than ten to the fifth power, and the etching amount in the non-porous layer (several tens of Angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, 1.0 on the glass substrate.
A single crystal Si layer having a thickness of μm could be formed.

The same effect can be obtained when Apiezon wax or electron wax is coated instead of the Si ₃ N ₄ layer, and only the porous Si substrate can be completely removed.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

A field effect transistor was formed on the above single crystal silicon thin film and connected to each other to manufacture a complementary element and its integrated circuit. A known MOS integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Embodiment 8) A P-type (10
0) The single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 10 mA / cm ²
Met. A porous layer having a thickness of 20 μm was formed on the surface in 10 minutes. On the P-type (100) porous Si substrate, a Si epitaxial layer was grown at a low temperature of 0.5 μm by a low pressure CVD method. The deposition conditions are as follows.

Gas: SiH ₂ Cl ₂ (0.6 1 / min.), H ₂ (100 1 / min) Temperature: 850 ° C. Pressure: 50 Torr Growth rate: 0.1 μm / min Next, the surface of this epitaxial layer Was thermally oxidized to 50 nm. Optically polished fused silica glass substrates were superposed on the thermal oxide film and heated in an oxygen atmosphere at 450 ° C. for 0.5 hour, whereby both substrates were firmly bonded.

After that, from the back surface of the silicon substrate, 49
It was removed by 0 micron grinding to expose the porous layer.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

Then, the bonded substrates are mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5).
In 0), selective etching is performed without stirring. After 15 minutes, only the single crystal Si layer remains without being etched,
Porous S using single crystal Si as an etch stop material
The i layer was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low and was 40 even after 15 minutes.
It is about a little less than Angstrom, and the selection ratio with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several Angstroms) is a practically negligible reduction in film thickness. After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 0.5 μm could be formed on the fused silica glass substrate.

The same effect can be obtained when Apiezon wax or electron wax is coated instead of the Si ₃ N ₄ layer, and only the porous Si layer can be completely removed.

A field effect transistor was formed on the above single crystal silicon thin film and connected to each other to manufacture a complementary element and its integrated circuit. A known MOS integrated circuit manufacturing technique is used for the method of manufacturing each transistor. (Example 9) P-type (10
0) A Si epitaxial layer was grown on the Si substrate by the CVD method to a thickness of 1 micron. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 1 / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 2 min This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . The rate of porosity at this time is 8.4 μm / mi.
n. And a P-type (10
0) The entire Si substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer remained unchanged.

Next, a fused silica glass substrate which has been optically polished is superposed on the surface of this epitaxial layer and heated in an oxygen atmosphere at 800 ° C. for 0.5 hour to firmly bond the two substrates. It was

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

Then, the bonded substrates were mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5).
In 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains unetched,
Porous S using single crystal Si as an etch stop material
The i substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, and the etching rate was 40 even after 65 minutes.
It is about a little less than Angstrom, and the selection ratio to the etching rate of the porous layer reaches more than ten to the fifth power, and the etching amount in the non-porous layer (several tens of Angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, 1 on the quartz glass substrate.
A single crystal Si layer having a thickness of μm could be formed.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained. A field effect transistor was formed on the single crystal silicon thin film and connected to each other to manufacture a complementary element and its integrated circuit. A known MOS integrated circuit manufacturing technique is used for the method of manufacturing each transistor.

[0123]

As described in detail above, according to the insulated gate field effect transistor and the semiconductor device using the same according to the present invention, a high-quality single crystal layer formed on a light-transmissive substrate has high performance. Insulated gate field effect transistor is manufactured. Therefore, there is little stray capacitance in the light transmissive substrate and high-speed operation is possible, and there is no latch-up phenomenon.
It becomes possible to provide an integrated circuit at a low price.

Conventionally, a good quality single crystal layer could not be obtained on a light-transmissive substrate typified by glass because the crystal structure of the substrate is generally amorphous. According to the above, a good quality single crystal Si substrate is used as a starting material,
A single crystal layer can be transferred onto a light-transmitting substrate (for example, a transparent glass substrate containing SiO ₂ as a main component), which is essential for contact sensors and projection-type liquid crystal image display devices. It becomes possible to fabricate a high-performance drive element, and it becomes possible to perform a large number of processes in a short time, and there is a great improvement in productivity and economical efficiency.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a complementary insulated gate field effect transistor according to the present invention.

FIG. 2 is a schematic cross-sectional view for explaining a substrate manufacturing process of the present invention.

FIG. 3 is a schematic cross-sectional view for explaining a process of the present invention.

FIG. 4 shows etching characteristics of porous and non-porous Si.

FIG. 5 shows etching characteristics of porous and non-porous Si.

FIG. 6 shows etching characteristics of porous and non-porous Si.

FIG. 7 shows etching characteristics of porous and non-porous Si.

FIG. 8 shows etching characteristics of porous and non-porous Si.

FIG. 9 shows etching characteristics of porous and non-porous Si.

FIG. 10 shows etching characteristics of porous and non-porous Si.

FIG. 11 shows etching characteristics of porous and non-porous Si.

[Explanation of symbols]

1 light transmissive silicon oxide substrate, 2 N-channel field effect transistor, 3 P-channel field effect transistor,
4 island-shaped single crystal layer, 5 island-shaped single crystal layer, 6 gate oxide film, 7 gate oxide film, 8 gate electrode, 9
Gate electrode, 10 source region, 11 drain region, 12 source region, 13 drain region, 14
Source electrode, 15 drain electrode, 16 source electrode, 17 drain electrode, 21 porous Si substrate,
22 non-porous Si single crystal layer, 23 glass light transmissive substrate, 24 silicon oxide layer, 25 etching prevention film, 31 P-type Si single crystal substrate, 32 N-type Si single crystal layer, 33 porous Si substrate, 34 glass light Transparent substrate, 35 Anti-etch film.

Claims (5)

[Claims] 1. An insulated gate field effect transistor, comprising:
The single crystal layer constituting at least the channel region is the surface of the non-porous single crystal layer on the porous silicon substrate, or after bonding the oxidized surface of the non-porous single crystal layer to the light transmissive substrate, An insulated gate field effect transistor, which is a single crystal semiconductor layer on a light transmissive substrate, obtained by removing the porous silicon substrate by at least a step including wet chemical etching. 2. The insulated gate field effect transistor according to claim 1, wherein the channel region of the insulated gate field effect transistor is an N type channel. 3. The insulated gate field effect transistor according to claim 1, wherein the channel region of the insulated gate field effect transistor is a P type channel. 4. A complementary insulated gate field effect transistor comprising the insulated gate field effect transistor according to claim 2. 5. A semiconductor device comprising the insulated gate field effect transistor according to claim 2, claim 3 or claim 4 as a constituent element.