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JPH0536893A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPH0536893A
JPH0536893A JP3193358A JP19335891A JPH0536893A JP H0536893 A JPH0536893 A JP H0536893A JP 3193358 A JP3193358 A JP 3193358A JP 19335891 A JP19335891 A JP 19335891A JP H0536893 A JPH0536893 A JP H0536893A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
lead frame
active
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3193358A
Other languages
Japanese (ja)
Inventor
Shigekichi Hirata
平田重吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3193358A priority Critical patent/JPH0536893A/en
Publication of JPH0536893A publication Critical patent/JPH0536893A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable a hybrid integrated circuit to be highly integrated by a method wherein circuit elements are thransfer mold-silaled in the same package pasting their rears each other. CONSTITUTION:An insulating wiring board 4, which is mounted with an active element and a passive element 5 connected with metal fine wires 3, is bonded to a flat metal lead frame 1 with adhesive agent 6 for the formation of a hybrid integrated circuit element, and the hybrid integrated circuit elements are sealed up by transfer molding. Thereafter, the hybrid integrated circuit elements are brought into contact with each other making the lead frame 1 face inward or bonded together with adhesive agent 6 and sealed up by transfer molding. By this setup, a hybrid integrated circuit of this design can be enhanced 1.5-2.0 times as high in degree of integration as a conventional one and consequently can cope with a demand for an increase in number of active and passive elements attendant on the improvement of a product in function and the miniaturization of a product.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は混成集積回路の構造に関
し、特に配線基板を伴う混成集積回路の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a hybrid integrated circuit, and more particularly to the structure of a hybrid integrated circuit with a wiring board.

【０００２】[0002]

【従来の技術】従来この種の混成集積回路は、フラット
な金属製のリードフレームに接着剤を用いて絶縁性の配
線基板を接着し、この配線基板に能動素子及び受動素子
（以下能動及び受動素子という）を搭載した構造となっ
ている。2. Description of the Related Art Conventionally, in this type of hybrid integrated circuit, an insulative wiring board is bonded to a flat metal lead frame with an adhesive, and an active element and a passive element (hereinafter referred to as active and passive elements) are bonded to the wiring board. (It is called an element).

【０００３】すなわち、図５および図６（図６は図５の
Ｃ−Ｃ線の断面図）に示すように金属性リードフレーム
１の片面に配線基板４を接着し、この配線基板４に能動
及び受動素子５を搭載し、能動及び受動素子５との相互
間ならびにこれらの金属製リードフレーム１との間を金
属細線３で接続し、合成樹脂などのモールド材にて外装
２を形成している。That is, as shown in FIGS. 5 and 6 (FIG. 6 is a sectional view taken along the line CC in FIG. 5), a wiring board 4 is adhered to one surface of the metallic lead frame 1 and the wiring board 4 is activated. And the passive element 5 are mounted, and the active and passive elements 5 and the metal lead frame 1 are connected to each other by a thin metal wire 3, and the outer casing 2 is formed by a molding material such as synthetic resin. There is.

【０００４】[0004]

【発明が解決しようとする課題】上述した従来の技術に
よる混成集積回路の構造は、金属製リードフレームの片
側にのみ配線基板と能動及び受動素子が搭載されている
ので、高集積化および高機能化には制限があった。In the structure of the hybrid integrated circuit according to the above-mentioned conventional technique, since the wiring board and the active and passive elements are mounted only on one side of the metal lead frame, high integration and high function are achieved. There was a limit to the conversion.

【０００５】本発明の目的は、高集積化が可能な混成集
積回路を提供することにある。An object of the present invention is to provide a hybrid integrated circuit which can be highly integrated.

【０００６】[0006]

【課題を解決するための手段】本発明の混成集積回路の
構造は、フラットな金属製のリードフレームに接着剤を
用いて絶縁性の配線基板を接着し、この配線基板に能動
及び受動素子を搭載し金属細線３で接続して成る混成集
積回路素子を金属製リードフレーム１と１の裏面を合わ
せるかあるいは接着剤を用いて接着した前記混成集積回
路素子をトランクファモールド封止して構成される。According to the structure of a hybrid integrated circuit of the present invention, an insulating wiring board is adhered to a flat metal lead frame using an adhesive, and active and passive elements are attached to the wiring board. A hybrid integrated circuit element which is mounted and connected by a thin metal wire 3 is formed by aligning the back surfaces of the metal lead frames 1 and 1 or by encapsulating the hybrid integrated circuit element with an adhesive. It

【０００７】[0007]

【実施例】次に本発明について図面を参照して説明す
る。図１および図２は本発明の第１の実施例の構造を示
す平面図および断面図である（図２は図１のＡ−Ａ線断
面図）。図１および図２に示すように、能動及び受動素
子５を搭載し、金属細線３で接続した絶縁性の配線基板
４に接着剤６を用いてフラットな金属製のリードフレー
ム１に接着して成る混成集積回路素子を複数個用い、ト
ランスファーモールド封止して構成する。その際、混成
集積回路素子はリードフレーム１を内側にして合わせる
か、または接着剤６を用いて接着させトランスファーモ
ールド封止して構成する。The present invention will be described below with reference to the drawings. 1 and 2 are a plan view and a sectional view showing the structure of the first embodiment of the present invention (FIG. 2 is a sectional view taken along the line AA of FIG. 1). As shown in FIGS. 1 and 2, the active and passive elements 5 are mounted, and the insulating wiring board 4 connected by the fine metal wires 3 is bonded to the flat metal lead frame 1 by using the adhesive 6. A plurality of such hybrid integrated circuit elements are used and transfer mold sealing is performed. At this time, the hybrid integrated circuit element is formed by aligning the lead frame 1 inside or by adhering the lead frame 1 using an adhesive 6 and sealing the transfer mold.

【０００８】図２および図４は本発明の第２の実施例の
構造を示す平面図および断面図である（図４は図３のＢ
−Ｂ線断面図）。2 and 4 are a plan view and a cross-sectional view showing the structure of the second embodiment of the present invention (FIG. 4 shows B of FIG. 3).
-B line sectional view).

【０００９】本実施例は図３に示すように、能動及び受
動素子５を接着剤６を用いて直接フラットな金属製のリ
ードフレーム１に搭載し金属細線３で能動及び受動素子
５とリードフレーム１を接続させて成る混成集積回路素
子はリードフレーム１を内側にして合わせるかまたは接
着剤６を用いて接着させトランスファーモールド封止し
て構成する。In this embodiment, as shown in FIG. 3, the active and passive elements 5 are directly mounted on a flat metal lead frame 1 with an adhesive 6 and the thin metal wires 3 are used to mount the active and passive elements 5 and the lead frame. A hybrid integrated circuit element formed by connecting 1's is formed by aligning the lead frame 1 inside or by adhering the lead frame 1 with an adhesive 6 and transfer-mold sealing.

【００１０】その際、混成集積回路素子はリードフレー
ム１を内側にして合わせるかまたは接着剤６を用いて接
着させトランクファーモールド封止して構成する。At this time, the hybrid integrated circuit element is formed by fitting the lead frame 1 inside or by adhering the lead frame 1 with an adhesive 6 and encapsulating it by a trunk fur mold.

【００１１】[0011]

【発明の効果】以上説明したように本発明は、フラット
な金属製のリードフレームに接着剤を用いて絶縁性の配
線基板を接着し、この配線基板に能動及び受動素子を搭
載した混成集積回路基板を複数個用いる構造にしたの
で、従来の技術に対し、集積度が１．５〜２倍となり高
機能化による能動及び受動素子の増大と製品の小型指向
に対応できるという効果がある。As described above, the present invention is a hybrid integrated circuit in which an insulating wiring board is bonded to a flat metal lead frame by using an adhesive and active and passive elements are mounted on the wiring board. Since a structure using a plurality of substrates is used, the degree of integration is 1.5 to 2 times that of the conventional technology, and there is an effect that the number of active and passive elements can be increased due to the high function and the product can be miniaturized.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.

【図２】図１のＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along the line AA of FIG.

【図３】本発明の他の実施例を示す平面図である。FIG. 3 is a plan view showing another embodiment of the present invention.

【図４】図３のＢ−Ｂ線断面図である。FIG. 4 is a sectional view taken along line BB of FIG.

【図５】従来例を示す平面図である。FIG. 5 is a plan view showing a conventional example.

【図６】図５のＣ−Ｃ線断面図である。FIG. 6 is a sectional view taken along line CC of FIG.

【符号の説明】[Explanation of symbols]

１ 金属製リードフレーム ２ 外装 ３ 金属細線 ４ 配線基板 ５ 能動及び受動素子 ６ 接着剤 1 Metal Lead Frame 2 Exterior 3 Metal Fine Wire 4 Wiring Board 5 Active and Passive Elements 6 Adhesive

Claims (1)

【特許請求の範囲】 【請求項１】 金属製リードフレーム表面に回路素子を
搭載してなる混成集積回路において、複数個の前記回路
素子を裏面を貼り合わせ同一パッケージ内にトランスフ
ァーモールド封止した事を特徴とする混成集積回路。Claim: What is claimed is: 1. In a hybrid integrated circuit in which circuit elements are mounted on the surface of a metal lead frame, the back surfaces of a plurality of the circuit elements are bonded together, and transfer mold sealing is performed in the same package. A hybrid integrated circuit characterized by.
JP3193358A 1991-08-02 1991-08-02 Hybrid integrated circuit Pending JPH0536893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3193358A JPH0536893A (en) 1991-08-02 1991-08-02 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3193358A JPH0536893A (en) 1991-08-02 1991-08-02 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPH0536893A true JPH0536893A (en) 1993-02-12

Family

ID=16306584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3193358A Pending JPH0536893A (en) 1991-08-02 1991-08-02 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPH0536893A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0778937A (en) * 1993-09-09 1995-03-20 Nec Corp Semiconductor device and its manufacture
EP0815615A4 (en) * 1995-03-13 2000-12-06 Intel Corp A package housing multiple semiconductor dies
JP2006303290A (en) * 2005-04-22 2006-11-02 Mitsubishi Electric Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0778937A (en) * 1993-09-09 1995-03-20 Nec Corp Semiconductor device and its manufacture
EP0815615A4 (en) * 1995-03-13 2000-12-06 Intel Corp A package housing multiple semiconductor dies
JP2006303290A (en) * 2005-04-22 2006-11-02 Mitsubishi Electric Corp Semiconductor device

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