JPH0536718A - Semiconductor device, and its semiconductor substrate, and these manufacture - Google Patents

Abstract

PURPOSE:To prevent pattern defects, etc., and improve the coverage of a drain electrode in a contact hole by forming each diffused region, a gate electrode, and a first drain electrode, respectively, on the surface of a semiconductor substrate. CONSTITUTION:N<+>-type diffused regions 12 and 13 to become a source and a drain respectively are selectively made in advance on the main surface of a p-type silicon substrate 11. Next, a gate electrode 14 which covers these whole surface is made, and through this gate oxide film 14, a gate electrode 15 is made. And the gate electrode 15 is buried with a first interlayer insulating film 16, and further a first drain electrode 17 is made which is connected to the n<+>-type diffused region 13 corresponding to a drain. Hereby, the inclusion of foreign matters between each layer can be avoided, and the occurrence of pattern defects can be prevented. Furthermore, in the later process, the depth of the aperture of a contact hole 19a into the third interlayer insulating film 19 can be reduced effectively, and the coverage of a drain electrode 20 can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a semiconductor substrate body for the same, and a manufacturing method thereof, more specifically, a MOS.FET, a semiconductor substrate body used for the MOS.FET, and a semiconductor substrate body for these. Manufacturing method, that is,
The present invention relates to a method for manufacturing a MOS • FET and a method for manufacturing a semiconductor substrate body used for the MOS • FET.

[0002]

2. Description of the Related Art FIG. 4 is a cross-sectional view schematically showing a general structure of a MOS.FET portion of this type which constitutes a memory cell of a semiconductor device in a conventional example.

That is, the conventional MOS
In the FET structure, reference numeral 1 is a p-type silicon substrate that serves as a device substrate portion, and 2 and 3 are the p-type silicon substrate 1
N ⁺ type diffusion regions which are selectively formed on the main surface of and serve as a source and a drain, 4 is a gate oxide film, 5 is a gate electrode, and 6 is a first interlayer insulation covering the gate electrode 5. A film, 7 is a second interlayer insulating film that covers the entire surface of these films, 8
Is a drain electrode connected to the n ⁺ type diffusion region 3 as the drain through a contact hole 7a selectively opened in the second interlayer insulating film 7.

[0004] In the case of the conventional MOS · FET of the above configuration, as is well known, together with lowering the n ⁺ -type diffusion region 2 serving as a source to ground, the drain to become n ⁺ -type diffusion through the drain electrode 8 By applying a-voltage to the gate electrode 5 while applying a-voltage to the region 3, an n ⁺ channel is formed at the interface between the gate oxide film 4 and the p-type silicon substrate 1 to conduct electricity. , Holes move from the n ⁺ type diffusion region 2 serving as the source to the n ⁺ type diffusion region 3 serving as the drain. That is, the source and drain are electrically connected by controlling the gate voltage.

Here, FIG. 5 shows the conventional MOS FET described above.
FIG. 2 is a cross-sectional view schematically showing a p-type silicon substrate as a device substrate portion in the configuration, showing, as described above, a source and a drain on the main surface of the p-type silicon substrate 1. The n ⁺ type diffusion regions 2 and 3 are selectively formed in the.

Next, FIGS. 6 (a) to 6 (g) show the above-mentioned conventional device substrate portion and a MOS / F using the device substrate portion.
It is each sectional drawing which shows typically the main processes of the manufacturing method of ET one by one.

First, on the main surface of the p-type silicon substrate 1 (see FIG. 6 (a)), a mask such as a resist pattern is used to perform n ⁺ -type diffusion on the source and drain by ion implantation. Regions 2 and 3 are selectively doped (see FIG. 6 (b)), and a thin oxide film 4a which will later become a gate oxide film 4 is formed on the surface of these regions by a thermal oxidation method (see FIG. 6B). See 6 (c)).

On the oxide film 4a, a conductive film (not shown) such as polycrystalline silicon doped with impurities, which will later become the gate electrode 5, is formed by the CVD method or the like, and each of these films is formed. The gate electrode 5 and the gate oxide film 4 are respectively formed by selective etching (see FIG. 6 (d)), and then the gate electrode including the gate oxide film 4 is again formed by the CVD method or the like. 5 is covered with a first interlayer insulating film 6 such as an oxide film (see FIG. 6 (e)).

Further, a second interlayer insulating film 7 is formed on the entire surface including the first interlayer insulating film 6 by a CVD method or the like, and a contact hole 7a is selectively opened in the second interlayer insulating film 7. (See FIG. 6 (f)), and the drain electrode 8 made of a conductor such as Al is connected to the n ⁺ type diffusion region 3 as the drain through the contact hole 7a (see FIG. 6 (g)). In this way, the desired MOS FET can be obtained.

[0010]

However, in the conventional MOS FET constructed as described above, the required circuit patterns are sequentially formed in multiple layers on the p-type silicon substrate 1 as the device substrate portion. In the process of moving, it is extremely difficult to eliminate pattern defects due to the intervention of foreign matters and the like, and the contact holes that are selectively opened in the second interlayer insulating film 7 because the cross section of each circuit pattern has a multilayer film structure. 7a becomes deeper and the contact hole 7a
However, there is an unfavorable problem such that the coverage of the drain electrode 8 formed through is deteriorated.

The present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is to prevent pattern defects and the like due to the inclusion of foreign matters in the multilayer structure in the manufacturing process. At the same time, the coverage of the drain electrode in the contact hole penetrating each layer can be improved, the semiconductor device of this type, the semiconductor substrate body thereof, and the manufacturing methods thereof,
An object of the present invention is to newly provide a device structure in a MOS • FET, a semiconductor substrate body applied to the device structure, and manufacturing methods thereof.

[0012]

In order to achieve the above object, a semiconductor device according to the present invention, a semiconductor substrate body thereof, and a manufacturing method thereof are provided with a source, A semiconductor substrate body is formed by respectively forming a diffusion region serving as a drain and a drain, a gate electrode via a gate oxide film, and a first drain electrode connected to the diffusion region corresponding to the drain. Further, by using the semiconductor substrate body, a required element structure is formed to form a semiconductor device.

That is, according to the present invention, a semiconductor substrate of a first conductivity type as a device substrate portion, and diffusions of a second conductivity type selectively formed on the main surface of the semiconductor substrate to serve as a source and a drain. A region and a gate electrode selectively formed corresponding to each of the diffusion regions via a gate oxide film,
A first drain electrode connected to the diffusion region corresponding to the drain and a first interlayer insulating film filling the periphery of each of these electrodes are formed to form a semiconductor substrate body,
A second cover that covers the gate electrode using the semiconductor substrate body;
Connected to the first drain electrode through the interlayer insulating film, the third interlayer insulating film including the second interlayer insulating film and covering the entire surface, and the contact hole opened in the third interlayer insulating film. And a second drain electrode formed as described above.

Further, according to the present invention, a semiconductor substrate of a first conductivity type as a device substrate portion and diffusions of a second conductivity type selectively formed on the main surface of the semiconductor substrate to serve as a source and a drain. Region, a gate electrode selectively formed corresponding to each diffusion region through a gate oxide film, a first drain electrode connected to the diffusion region corresponding to the drain, and the periphery of each of these electrodes And a first interlayer insulating film for burying at.

Further, according to the present invention, a step of selectively forming each diffusion region of the second conductivity type serving as a source and a drain on the main surface of the semiconductor substrate of the first conductivity type as the device substrate portion. A step of selectively forming a gate oxide film corresponding to each of the diffusion regions and a gate electrode via the gate oxide film, and a first drain electrode connected to the diffusion region corresponding to the drain. Forming a semiconductor substrate body including at least a step of selectively forming and a step of embedding the periphery of each of these electrodes with a first interlayer insulating film, and using the semiconductor substrate body, the gate electrode is formed. With a second interlayer insulating film, a step of covering the entire surface of the second interlayer insulating film with a third interlayer insulating film, and a contact opened in the third interlayer insulating film. Through Lumpur, relative to the first drain electrode, and a step of connecting the second drain electrode, a method of manufacturing a semiconductor device, which comprises at least.

Further, according to the present invention, a step of selectively forming each diffusion region of the second conductivity type to be a source and a drain on the main surface of the semiconductor substrate of the first conductivity type as the device substrate portion. A step of selectively forming a gate oxide film corresponding to each of the diffusion regions and a gate electrode via the gate oxide film, and a first drain electrode connected to the diffusion region corresponding to the drain. And a step of burying the periphery of each of these electrodes with a first interlayer insulating film, the method of manufacturing a semiconductor substrate body.

[0017]

Therefore, according to the present invention, the diffusion regions serving as the source and the drain, the gate electrode via the gate oxide film, and the diffusion region corresponding to the drain are connected to the surface of the semiconductor substrate in advance. Since the semiconductor substrate body is formed by forming the drain electrode of No. 1, it becomes possible to avoid the intervention of foreign matters between layers during the formation of the multilayer structure, and the pattern defects due to the intervention of the foreign matter can be avoided. In addition to being able to prevent the generation, in the semiconductor substrate body configured in this way, the opening depth of the contact hole to the multilayer film during the subsequent formation of the element structure can be reduced, and the drain electrode formed through the contact hole can be prevented. Improves coverage.

[0018]

Embodiments of the semiconductor device according to the present invention, the semiconductor substrate body thereof, and the manufacturing method thereof will be described below.
This will be described in detail with reference to FIGS. 1 to 3.

FIG. 1 is a sectional view schematically showing a semiconductor device to which an embodiment of the present invention is applied, in this case, a MOS.FET.

That is, M according to the embodiment shown in FIG.
Even in the configuration of the OS • FET (semiconductor device) 100,
Reference numeral 11 denotes a p-type silicon substrate which is a substrate portion of the device, and 12 and 13 are selectively formed on the main surface of the p-type silicon substrate 11 to serve as a source and a drain, respectively.
An n ⁺ type diffusion region, 14 is a gate oxide film formed on the entire surface thereof, and 15 is a gate selectively formed on the gate oxide film 14 so as to extend between the n ⁺ type diffusion regions 12 and 13. Reference numeral 16 denotes an electrode, 16 is a first interlayer insulating film formed to fill the periphery of the gate electrode 15, and 17 is a first interlayer insulating film.
Connected to the n ⁺ type diffusion region 13 as the drain through the interlayer insulating film 16 and the gate oxide film 14.
The drain electrode of the MOS.FET 100 is formed on the substrate side structure, in other words, the semiconductor substrate 200.

Reference numeral 18 is a second interlayer insulating film that covers the periphery of the gate electrode 15, 19 is a third interlayer insulating film that covers the entire surface of the gate electrode 15, and 20 is a third interlayer insulating film 19. , A second drain electrode connected to the n ⁺ type diffusion region 13 as the drain through a contact hole 19a selectively opened to reach the first drain electrode 17, and in this way, MOS FET 10 using the semiconductor substrate body 200 as expected
It constitutes 0.

However, even in the case of the MOS.FET 100 using the semiconductor substrate body 200 of the embodiment having the above structure, the n.sup. ⁺ Type diffusion region 12 serving as the source is formed in the same manner as in the conventional case described above. While dropping to the ground, second
While the negative voltage is applied to the n ⁺ type diffusion region 13 serving as a drain through the drain electrode 20 and the first drain electrode 17, the negative voltage is applied to the gate electrode 15 so that the gate oxide film 14 is formed. An n ⁺ channel is formed at the interface with the p-type silicon substrate 11 to conduct electricity and serve as a source.
the drain of n ⁺ -type diffusion region 12 n ⁺ -type diffusion region 13
The hall moves to. That is, the source and drain are electrically connected by controlling the gate voltage.

FIG. 2 shows the MOS / F in the above embodiment.
FIG. 3 is a cross-sectional view schematically showing a semiconductor substrate body 200 including a p-type silicon substrate as a device substrate portion in the configuration of the ET100 and showing the semiconductor substrate body 200 as described above. N ⁺ type diffusion regions 12 and 13 respectively serving as a source and a drain are selectively formed on a main surface of a p-type silicon substrate 11 as a portion, and a gate oxide film 14 covering the entire surfaces thereof is formed. Also,
A gate electrode 15 is selectively formed via the gate oxide film 14, and the periphery thereof is filled with a first interlayer insulating film 16, and further, the first interlayer insulating film 16 and the gate oxide film. A first drain electrode 17 connected to the n ⁺ type diffusion region 13 as a drain through 14 is formed.

Next, FIGS. 3 (a) to 3 (g) show the semiconductor substrate body 200 according to the above-mentioned embodiment and the semiconductor substrate body 2 concerned.
10A to 10C are cross-sectional views each schematically showing main steps of a method of manufacturing a MOS-FET 100 using 00.

First, on the main surface of the p-type silicon substrate 11 (see FIG. 3A) as a device substrate portion, a mask such as a resist pattern is used to form a source and a drain by ion implantation. N ⁺ type diffusion regions 12, 13
By selectively doping (see FIG. 3 (b)) and using a mask such as a similar resist pattern on these surfaces, the connection with the n ⁺ -type diffusion region 13 serving as a drain is not provided. And a gate oxide film 14 made of a thin oxide film is formed by an oxygen implantation method or the like, and further, for example, a single crystal silicon layer 21 or the like is formed on the entire surface thereof by a CVD method or the like (see FIG. See 3 (c)).

Further, with respect to the single crystal silicon layer 21,
By a mask such as a resist pattern, by ion implantation, a gate electrode 15 is interposed between the n ⁺ type diffusion regions 12 and 13 as sources and drains, and an n ⁺ type diffusion region as a drain is provided. Each n ⁺ type diffusion region to be the first drain electrode 17 connected to 13 and each of these electrodes 15 by the oxygen implantation method,
A first interlayer insulating film 16 that fills the periphery of 17 is formed in each (see FIG. 3D).

That is, each step up to this point, that is, each step from FIG. 3 (a) to FIG. 3 (d) is the MO according to this embodiment.
This is a manufacturing process of the semiconductor substrate body 200 used for the S-FET 100, and by extension, the semiconductor substrate body 200 used for the semiconductor device.

Then, by using the semiconductor substrate body 200, the first drain electrode 1 is formed on the entire surface of the semiconductor substrate body 200 by a CVD method using a mask such as a resist pattern.
A second interlayer insulating film 18 such as an oxide film is selectively formed so as to cover the gate electrode 15 in a sufficient area except for the portion 7 (see FIG. 3 (e)).

Further, a third interlayer insulating film 19 is formed on the entire surface including the second interlayer insulating film 18 by a CVD method or the like, and at the same time, with respect to the third interlayer insulating film 19,
A contact hole 19a reaching the first drain electrode 17 is selectively opened (see FIG. 3 (f)), and the first drain electrode 17 and, as a result, an n ⁺ -type diffusion as the drain, are formed through the contact hole 19a. Area 1
A drain electrode 20 made of a conductor such as Al is connected to 3 (see FIG. 3 (g)).

That is, as described above, the semiconductor substrate body 2 formed by the steps of FIGS. 3 (a) to 3 (d)
No. 00, and through each step of FIGS. 3 (e) to 3 (g), the MOS-FET 10 having the intended configuration according to this embodiment.
Therefore, a semiconductor device having a desired structure is obtained.

Therefore, in this embodiment, the n ⁺ type diffusion regions 12 and 13 to be the source and drain and the gate oxide film 1 are previously formed on the surface of the p type silicon substrate 11.
Since the semiconductor substrate body 200 is configured by forming the gate electrode 15 via the gate electrode 4 and the first drain electrode 17 connected to the n ⁺ type diffusion region 13 corresponding to the drain, these are used here. In forming the multi-layered structure, there is an advantage that it is possible to avoid the inclusion of foreign matter or the like between the respective layers, and it is possible to prevent the occurrence of pattern defects due to the intervention of the foreign matter. In the MOS-FET 100 configured using 200, it is possible to effectively reduce the opening depth of the contact hole 19a to the third interlayer insulating film 19 during the subsequent formation of the element structure, and to form the contact hole 19a through the contact hole 19a. The coverage of the drain electrode 20 thus formed can be improved satisfactorily.

In the above embodiment, each of the n ⁺ and the source and drain is formed on the main surface of the p-type silicon substrate 11.
Although the case where the type diffusion regions 12 and 13 are selectively formed has been described, it is needless to say that these may have opposite conductivity types and similar operations and effects can be obtained.

[0033]

As described above in detail with reference to the embodiments,
According to the present invention, with respect to the surface portion of the semiconductor substrate, the diffusion regions serving as the source and the drain, the gate electrode via the gate oxide film, and the first drain connected to the diffusion region corresponding to the drain are formed in advance. Form electrodes and each,
Since the semiconductor substrate body is configured, it is possible to completely avoid the intervention of foreign matter between layers when forming the multilayer structure, and effectively prevent the occurrence of pattern defects due to the intervention of the foreign matter. In addition, when a semiconductor device is formed by using the semiconductor substrate body configured as described above, a multilayer film including an interlayer insulating film at the time of forming an element structure on the semiconductor substrate body is obtained. The opening depth of the contact hole can be easily reduced. As a result, according to the present invention, an effective semiconductor substrate body including a transistor structure can be obtained satisfactorily and extremely easily, and reliability is improved. It has excellent features such as easy provision of rich semiconductor devices.

[Brief description of drawings]

FIG. 1 is a MOS FET to which an embodiment of the present invention is applied.
FIG. 3 is a cross-sectional view schematically showing the schematic configuration of FIG.

FIG. 2 is a cross-sectional view schematically showing a semiconductor substrate body having a MOS • FET structure according to one embodiment of the same as above.

3 (a) to (g) are semiconductor substrate bodies according to one embodiment of the same as above, and MOS / FE using the semiconductor substrate bodies.
It is sectional drawing which shows each main process of the manufacturing method of T sequentially typically.

FIG. 4 is a sectional view schematically showing a schematic configuration of a MOS • FET according to a conventional example.

FIG. 5 is a cross-sectional view schematically showing a semiconductor substrate having a MOS-FET structure in the conventional example taken out.

6 (a) to (g) are the same as the conventional MOS.F.
It is each sectional drawing which shows typically the main processes of the manufacturing method of ET one by one.

[Explanation of symbols]

100 MOS • FET (semiconductor device) 200 Semiconductor substrate 11 p type silicon substrate 12, 13 n ⁺ type diffusion regions (source, drain) 14 gate oxide film 15 gate electrode 16 first interlayer insulating film 17 first drain electrode 18 Second Interlayer Insulating Film 19 Third Interlayer Insulating Film 19a Contact Hole 20 Second Drain Electrode

Claims (4)

[Claims] 1. A semiconductor substrate of a first conductivity type as a device substrate portion, a source selectively formed on a main surface of the semiconductor substrate,
And second diffusion type diffusion regions serving as a drain, a gate electrode selectively formed corresponding to each diffusion region via a gate oxide film, and a first drain region-connected diffusion region A drain electrode and a first interlayer insulating film that fills the periphery of each of these electrodes to form a semiconductor substrate body, and a second semiconductor substrate body is used to cover the gate electrode. An interlayer insulating film, a third interlayer insulating film including the second interlayer insulating film and covering the entire surface, and a contact hole formed in the third interlayer insulating film are connected to the first drain electrode. And a second drain electrode, which is provided at least. 2. A first conductivity type semiconductor substrate as a device substrate portion, a source selectively formed on a main surface of the semiconductor substrate,
And second diffusion type diffusion regions serving as a drain, a gate electrode selectively formed corresponding to each diffusion region via a gate oxide film, and a first drain region-connected diffusion region And a first interlayer insulating film filling the periphery of each of these electrodes, and a semiconductor substrate body. 3. A step of selectively forming each diffusion region of the second conductivity type, which is to be a source and a drain, on the main surface of the semiconductor substrate of the first conductivity type as the device substrate portion, A step of selectively forming a gate oxide film corresponding to the diffusion region and a gate electrode through the gate oxide film, and a step of selectively forming a first drain electrode connected to the diffusion region corresponding to the drain The step of forming and the step of burying the periphery of each of these electrodes with the first interlayer insulating film constitute the semiconductor substrate body, and
A step of covering the gate electrode with a second interlayer insulating film using the semiconductor substrate body; a step of covering the entire surface of the gate electrode with a third interlayer insulating film including the second interlayer insulating film; And a step of connecting the second drain electrode to the first drain electrode through a contact hole opened in the third interlayer insulating film. 4. A step of selectively forming each diffusion region of the second conductivity type, which serves as a source and a drain, on the main surface of the semiconductor substrate of the first conductivity type as the device substrate portion, A step of selectively forming a gate oxide film corresponding to the diffusion region and a gate electrode through the gate oxide film, and a step of selectively forming a first drain electrode connected to the diffusion region corresponding to the drain A method for manufacturing a semiconductor substrate body, comprising at least a step of forming and a step of embedding a periphery of each of these electrodes with a first interlayer insulating film.