JPH0535215A - Driving method for active matrix liquid crystal display - Google Patents

Abstract

PURPOSE:To suppress display unevenness due to the rounding of a gate address pulse by providing the gate address pulse, a data signal, and a common electrode signal with timing offsets and causing the data signal and common electrode signal to vary after a gate turns OFF. CONSTITUTION:A time difference of 3musec is provided between a signal which switches the output of a driver and a vertical synchronizing signal to place the vertical synchronizing signal in a phase advanced state. Namely, the vertical synchronizing signal is made to lead the switching signal for the H driver output in phase and then an (n)th gate address pulse Gn, etc., leads a data signal Dm applied to an (m)th source input terminal, so the same output of an H driver which turns OFF is obtained at both the input terminal and open terminal of the gate. Therefore, even if the gate pulse Gn is rounded owing to wiring resistance, the writing of the data signal Tn+1 of a next line Gn+1 can be suppressed to maintain the display uniformity of a screen.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving an active matrix liquid crystal display.

[0002]

2. Description of the Related Art An equivalent circuit of an active matrix liquid crystal display is shown in FIG. A display data signal is applied to the source input terminal 15, and a TFT is applied to the gate input terminal 16.
A pulse voltage for turning on / off 17 is line-sequentially applied. When the pulse voltage of the gate terminal becomes high level (typically about 20V), the TFT 17 is turned on and the display electrode 18 is charged by the data signal applied to the source input terminal 15.

FIG. 5 shows a timing chart of a driving method of a conventional active matrix liquid crystal display. In FIG. 5, Gn, Gn + 1, and Gn + 2 are gate address pulses applied to the n-th, n + 1-th, and n + 2-th gate input terminals, respectively, and Dm is a data signal applied to the m-th source input terminal. As shown in the figure, in the conventional driving method, the turn-off of the gate address pulse and the switching timing of the data signal coincide with each other.

[0004]

In this conventional method for driving an active matrix liquid crystal display, since the turn-off of the gate address pulse is synchronized with the switching of the data signal, the waveform of the gate address pulse is the open end side of the gate. Then, as shown by Gn 'in FIG. 5, if it is blunted due to the wiring resistance, the TFT cannot be turned off instantaneously, so that the data signal Tn + 1 of the next line Gn + 1 is written.

[0005]

A method of driving an active matrix liquid crystal display according to the present invention is driven at a timing when a gate address signal for writing a data signal applied to a liquid crystal panel is turned off before the data signal is switched. It is characterized by performing.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an active matrix liquid crystal display for explaining the present invention. The display signal from the personal computer 1 is sent to the gate array 2 where it is converted into a signal suitable for driving the liquid crystal panel 3. The signal timing supplied from the horizontal (H) driver 4 to the panel is given by the H output switching signal 7 which controls the dual sample hold circuit 6 at the output of the H driver 4. The timing of line-sequential scanning of the vertical (V) driver 8 is given by the rising edge of the vertical synchronizing signal 9. At this time, there is a time difference of 3 μsec between the signal 7 for switching the output of the H driver 4 and the vertical synchronizing signal 9 to bring the vertical synchronizing signal 9 into a phase advance state.

FIG. 2 shows a timing chart of drive signals of the liquid crystal display described in FIG. In FIG. 2, Gn, Gn + 1, and Gn + 2 are the nth and nth, respectively.
Gn 'is a gate address pulse applied to the + 1st and n + 2th gate input terminals, and Gn' is a pulse applied to the nth gate input terminal, propagates to an open end opposite to the input end, and is a wiring resistance. Shows a pulse that has become. That is, the timing of turning off Gn 'is delayed compared to Gn. On the other hand, Dm is a data signal applied to the m-th source input terminal.

By advancing the vertical synchronizing signal 9 from the switching signal 7 of the H driver output, the gate addle palace Gn etc. is advanced from the data signal Dm, and the H driver output in a state where both the input end and the open end of the gate are turned off Will be the same. Therefore, even if the gate pulse is blunted by the wiring resistance as shown by Gn ′ in FIG. 2, writing of the data signal Tn + 1 on the next line Gn + 1 can be suppressed and the display uniformity on the screen can be maintained.

FIG. 3 is a comparison of the display brightness between the input side and the open side of the gate in the 10.4 inch size amorphous silicon thin film transistor active matrix liquid crystal display, using the timing offset shown in FIG. 2 as a parameter. In FIG. 2, one abscissa indicates that the turn-off of the gate pulse precedes the timing of switching the source signal. The gate wiring is made of Cr and has a film thickness of 140 nm, a wiring width of 20 μm, and a wiring length of 2
It is 00 mm. As shown in FIG. 3, a shift of 1.5 μsec is shown on the gate input side and the open side. Therefore, in this case, by giving a timing offset of, for example, about 3 μsec, luminance, that is, display uniformity can be stably obtained. ..

[0010]

As described above, according to the present invention, a gate offset pulse, a data signal, and a common electrode signal are provided with a timing offset, and a data signal after the gate is turned off.
By causing the common electrode signal to change, it has an effect of suppressing display nonuniformity due to rounding of the gate address pulse.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display for explaining the present invention.

FIG. 2 is a timing chart of drive signals in the liquid crystal display shown in FIG.

FIG. 3 is data showing the relationship between the timing and brightness of the gate pulse and the data signal in the present invention.

FIG. 4 is a diagram showing an equivalent circuit of an active matrix liquid crystal display panel.

FIG. 5 is a timing chart of drive signals of a conventional active matrix liquid crystal display.

[Explanation of symbols]

 1 personal computer 2 gate array 3 liquid crystal panel 4 H driver 5 shift register 6 dual sample hold circuit 8 V driver 15 source input terminal 16 gate input terminal 17 TFT 18 display electrode

Claims (1)

Claim: What is claimed is: 1. An active matrix liquid crystal display, characterized in that driving is performed at a timing when an address signal for writing a data signal is turned off prior to switching of a data signal applied to a liquid crystal panel. Driving method.