JPH0534872B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an address code mixing device in a receiving device, and particularly to preventing unauthorized copying by a terminal receiving and reproducing device for paid information such as paid broadcasting. The present invention relates to a contributing address code mixing device.

[Prior Art] Currently, information provision services are being provided using paid communication systems, such as paid broadcasting through satellite broadcasting, CATV, etc., and provision of paid information using other personal computer communications. In these communication systems,
Only members who have paid a predetermined fee are provided with a terminal receiving device unique to the communication system that allows information to be provided, so that information is not available to anyone other than the members.

However, in the above case, the information obtained by a legitimate member may actually be provided to a third party by the member using a playback device, and such unauthorized use should not be allowed to occur. It is clear that this will result in a major economic loss for pay TV operators.

Therefore, in the past, measures such as inserting a copy prohibition code into the information data or including a screen displaying the unique address number assigned to the terminal in the video signal were taken to prevent the copying of paid information. I was trying to prevent it.

[Problems to be Solved by the Invention] However, the conventional means for preventing copying described above can generally be easily removed technically. That is, by using an easily available device such as an oscilloscope, it is possible to relatively easily remove the screen containing the copy prohibition code signal and the address number of the terminal.

An object of the present invention is to mix an address code uniquely assigned to a terminal device into a portion of a television signal other than a video signal, and to make this address code inseparable and difficult to detect. To provide an address code mixing device that enables a terminal device on which illegal copying has been made to be quickly and easily discovered when viewing is performed, and thereby prevents illegal copying.

[Means for Solving the Problems] An address code mixing device according to the present invention synchronizes a field counter with a vertical synchronizing signal and a horizontal synchronizing signal of a television signal.
The control means selects a plurality of fields for inserting each bit of the address code, and outputs each bit of the address code from the address ROM in synchronization with the field, and further includes an address code generating means for outputting each bit of the address code from the address ROM in synchronization with the field. The horizontal scanning period in which each bit of the address code is inserted in each field is pseudo-randomly determined by the PN code output by the generating means, and the address code mixing means inserts a part of the horizontal scanning period other than the video signal. The bit information is inserted by changing the bit information.

[Examples] Examples of the present invention will be described below based on the accompanying drawings.

FIG. 1 shows a receiving device for a terminal including an embodiment of the address code mixing device according to the present invention. This terminal receiving device is a receiving device for a terminal device that receives pay broadcast signals.

In Figure 1, 1 receives, amplifies and detects VHF, UHF or SHF television signals.
TV tuner, 2 is video signal descrambler, 3
4 is an audio signal descrambler; 4 extracts information for descrambling from the broadcast signal when the received television signal is a pay broadcast and the video signal and audio signal are sent scrambled; This is a descrambling control circuit for controlling the operations of the video signal descrambler 2 and the audio signal descrambler 3 based on this information. An audio signal is output from the audio signal descrambler 3. Further, the video signal descrambler 2 is housed in a circuit 5 indicated by a broken line. This circuit 5
is a video processing circuit integrally formed including an address mixing circuit. 6 is a video signal buffer amplifier, and the video signal is taken out to this output terminal.

In the video processing circuit 5, a normal television signal is output from the video signal descrambler 2, and this signal is processed by an FSC reproducing circuit 7 for extracting a color subcarrier (hereinafter referred to as FSC), and horizontal and vertical synchronization from the television signal. The signal is supplied to a synchronization signal separation circuit 8 that separates the signals. In fsc regeneration circuit 7, generally
Match the phase and frequency to the outgoing signal using AFPC. The fsc output from the fsc regeneration circuit 7 is given to a phase delay circuit 9 and a phase advance circuit 10. Slow phase circuit 9
has the effect of delaying fsc by 90 degrees, and phase advance circuit 1
0 has the effect of advancing fsc by 90 degrees. Further, the horizontal synchronization signal (hereinafter referred to as H pulse) output from the synchronization signal separation circuit 8 is generated by the fsc regeneration circuit 7, the phase shift gate pulse generation circuit 11 and the PN code (psudo
A vertical synchronizing signal (hereinafter referred to as V pulse) is supplied to a field counter/control circuit 13 and an address signal generating circuit 14. The PN code generation circuit 12 is a circuit for pseudo- ^randomly determining the horizontal scanning period in which each bit of the address code is mixed in each field.
It includes a shift register that generates an m-sequence PN code of 1, and after setting the initial value arbitrarily, the V pulse generates a PN code of 1.
Pseudo-randomly generate one number between 1 and 255 by clocking the shift register once in the field and then applying an H pulse to the vertical blanking interval VBI.
Count from the 11th hour. PN code generation circuit 1
The detailed configuration of 2 will be described later. The gate pulse Φ ₃ (see FIG. 3) output from the phase shift gate pulse generation circuit 11 and the PN code Φ _x (see FIG. 3) output from the PN code generation circuit 12 are input to the two-input NAND gate 15. , here the logical product of Φ ₃ and Φ _x is calculated. On the other hand, the field counter/control circuit 13 outputs a V pulse for, for example, 66 fields, supplies this V pulse to the PN code generation circuit 12 and the address signal generation circuit 14, and outputs a V pulse for the next 100 fields. operates to stop output. This operation is repeatedly performed in the field counter/control circuit 13. A circuit that performs such an operation can be easily created by combining counters, gates, and flip-flops, so a detailed explanation of the configuration will be omitted.
The address signal generation circuit 14 is a circuit that generates an address signal for outputting the contents of the ROM 16 that stores an address code.
Specify the address from ``65'' to ``65''. After output is made from address "65", it returns to address "0" again. The ROM 16 stores, for example, a 64-bit unique address code assigned to the terminal device, and sequentially designates and stores an address for each bit of the address code. Therefore, when addresses are sequentially output from the address signal generation circuit 14 in synchronization with the V pulse, the
Each bit of the address code is output from the output end of the ROM 16. In addition, addresses "0" and "65"
1 is written as a start bit and a stop bit, respectively, and a 64-bit terminal address code is written in addresses "1" to "64".

In the video processing circuit 5, there are also four analog
AND gates 17, 18, 19, 20, two analog OR gates 21, 22, two NOT circuits 2
3, 24, two buffer amplifiers 25, 26 each including a clamp for aligning DC levels
It is included. The output of the phase delay circuit 9 is input to one input terminal of the AND gate 17, the output of the phase advance circuit 10 is input to one input terminal of the AND gate 18, and the other inputs of the AND gates 17 and 18 are input. An address code output from the ROM 16 is input to the end. However, AND gate 1
The address code signal input to 7 is inverted by the NOT circuit 23. Further, the output of an OR gate 21 that performs the logical sum of both outputs of the AND gates 17 and 18 is inputted to one input terminal of the AND gate 19 via a buffer amplifier 25, and the output of an The video signal output from the signal descrambler 2 is input through a buffer amplifier 26 that fixes its pedestal level to a constant DC level, and the output of the NAND gate 15 is input to the other input terminal of the AND gates 19 and 20. is input. However, the output signal of the NAND gate 15 that is input to the AND gate 19 is inverted by the NOT circuit 24. After that, the output of AND gates 19 and 20 is OR gate 2
2 is logically summed and supplied to the buffer amplifier 6.

Next, the configuration of the PN code generating circuit 12 will be explained in detail with reference to FIG. In Figure 2, 10
1 is an m-sequence PN code generator composed of an 8-bit shift register and an EX-OR gate, and 102 is an H
H pulse counter that counts the 11th pulse as 1,
103 is an H pulse counter 10 using V pulses.
1 starts the operation from the 11th H, 104 is a first comparator, and when the m-sequence PN code generator 101 indicates "x", if the output of the H pulse counter 102 becomes "x", Its output becomes high level. m-sequence PN code generator 10
The outputs of the 1 and H pulse counters 102 are both 8 bits. 105 is an OR gate, which normally only transmits the V pulse to the m-sequence PN code generator 101. The output of the PN code generator 101 is 262−10=
252, comparator 1 is closed during the vertical retrace interval (VBI).
Since the output of PN code generator 101 is at a high level, there is no color burst and data cannot be loaded in the form of Φ ₁ and Φ ₂ as described later. the second comparator 1
06 and memory 107, the output is 252
If this is the case, the shift pulse generation circuit 108 generates a shift pulse, and the output of the shift pulse generation circuit 108 shifts the PN code generator 101 via the OR gate 105. Unless the output of the PN code generator 101 changes and the result becomes 251 or less,
The shift pulse is generated again by the shift pulse generation circuit 108.
is output from. Therefore, the output Φ _x of the comparator 104 is at a high level for a 1H width including the period of one cycle during the color burst from 11H to 261H.

Next, the operation of the receiving device having the above configuration will be explained. In this operation explanation, Figures 1 and 3
Reference is made to FIGS. FIG. 3 is a waveform diagram showing an example in which the phase of one cycle of color burst (fsc) Φ ₀ is changed according to the bit of the address code, and FIG. FIG. 5 is a waveform diagram showing the horizontal scanning period "x" for address code insertion and various methods of insertion. This is what is shown.

A composite video and audio signal (television signal) received by the TV tuner 1 is supplied to a video signal descrambler 2, an audio signal descrambler 3, and a descramble control circuit 4. Under the control of the descrambling control circuit 4, the video signal descrambler 2 and audio signal descrambler 3 output descrambled video and audio signals, respectively. The signal output from the video signal descrambler 2 is a composite video signal including a synchronization signal, and is then converted into a part other than the video signal in an appropriate horizontal scanning period within one field of this composite video signal, for example, in the phase of a color burst. Information related to each bit of the address code unique to this terminal stored in the ROM 16 will be inserted.

The fsc reproducing circuit 7 extracts fscΦ ₀ from the composite video signal, and this fscΦ ₀ is
The phase is shifted by -90 degrees and supplied to the AND gate 17, and on the other hand, the phase is shifted by +90 degrees by the phase advance circuit 10 and supplied to the AND gate 18. Further, the synchronization signal separation circuit 8 extracts the H pulse and the V pulse from the composite video signal, and the phase gate pulse generation circuit 11 outputs the gate pulse Φ ₃ as shown in FIG. 15, and the PN code generating circuit 12 outputs a PN code Φ _x consisting of a 255-bit bit string in which each bit is synchronized with the H pulse.
It is supplied to the other input of NAND gate 15.
NAND gate 15 takes the AND of Φ ₃ and Φ _x
Give to AND gates 19 and 20. The field counter/control circuit 13 inputs the V pulse, counts the field, outputs the V pulse for 66 fields, and repeatedly stops outputting the V pulse for the next 100 fields. The address signal generation circuit 14 inputs the V pulse from the synchronization signal separation circuit 8, synchronizes the generation of its output with this, and generates an address corresponding to the 66 V pulses output from the field counter/control circuit 13. Address signals from "0" to "65" are sequentially supplied to the ROM 16. The ROM 16 synchronizes with the 66 V pulses and stores each bit of the 64-bit address code corresponding to addresses "0" to "65" and the two before and after it.
Output bits. In addition, the field counter
The 66 V pulses output by the control circuit 13 are also given to the PN code generation circuit 12, and the PN code generation circuit 12 performs the above-mentioned V pulses corresponding to the predetermined 66 fields.
Generates PN code.

By the action of each circuit as described above, when 66-bit data is output from the ROM 16 in synchronization with the predetermined 66 fields, the AND gates 17 and 18
By the action of the NOT gate 23 and the OR gate 21, the phase is advanced or delayed depending on the content of each data, that is, "1" or "0".
fsc is selected, the level is adjusted by the buffer amplifier 25, and the signal is input to the AND gate 19. Also,
A normal composite video signal whose level has been adjusted by a buffer amplifier 26 is input to the AND gate 20. Since the output of the NAND gate 15 is normally in the "1" state, the composite video signal passes through the AND gate 20 and is supplied to the buffer amplifier 6 through the OR gate 22. Then, when the gate pulse Φ ₃ and "1" in the PN code Φ _x occur simultaneously, the output of the AND gate 15 becomes "0" between t ₁ and _{t 2} determined by Φ ₃ , and as a result As a result of the action of the NOT gate 24, the composite video signal output to the output terminal of the OR gate 22 contains one cycle of the color burst of 66 consecutive fields (defined by the gate pulse Φ ₃ above). ROM1
A phase signal corresponding to the data read from 6 is included. That is, as shown in FIGS. 3 and 4A, when the data read from the ROM 16 is "0" compared to the normal fscΦ ₀ , the phase is delayed fscΦ ₁ ,
When it is "1", a phase advance _fscΦ2 occurs during the horizontal scanning period x of each predetermined field. In this way, one of the 66 consecutive fields as shown in Figure 5.
ROM in the color burst part of two horizontal scanning periods
A start bit, an address code, and a stop bit which are sequentially read from 16 are mixed in. However, the horizontal scanning period x during which data is mixed in each field differs from field to field, and is determined pseudo-randomly by the PN code Φ _x .

Next, another embodiment of the address code mixing device according to the present invention will be described with reference to FIG. In this embodiment, the address code is mixed in by deleting the synchronization signal as shown in FIG. 4B. In FIG. 6, the same elements as those shown in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

30 is a synchronization signal deletion gate pulse generation circuit;
A gate pulse of Φ _3B shown in FIG. 7B is generated.
The AND of Φ _3B and Φ _x is output from the NAND gate 15. NAND gate 15 has 3 inputs in this case
In the NAND gate, only when the output of the ROM 16 is "1", a negative pulse (Φ _3B in FIG. 7B is inverted) is output, the analog AND gate 20 is cut off, and the output of the NOT circuit 24 is The signal becomes high level and the analog AND gate 19 becomes conductive. 31
is, the DC level of its output is buffer amplifier 26
This is a DC level matching circuit that is equal to the pedestal level of the output of the ROM 16, so there is no problem even if the output of the ROM 16 is not added. Even if one synchronization signal is missing in one field, it will not affect the TV screen, and it is easy to detect the address code because it is sufficient to monitor the state of the synchronization separation output. "1" for synchronization signal loss
In addition, if the presence of a synchronization signal corresponds to "0", one synchronization signal is always missing somewhere in each field of start bit and stop bit, so the presence or absence of a horizontal synchronization signal in between and the address code of the terminal It is easy to see that it is compatible.

It is also possible to make the missing color burst correspond to the data "1" in the address code, and in this case, the synchronizing signal deletion gate pulse generation circuit 30 in Figure 6 is changed to a color burst deletion gate pulse generation circuit _. should be Φ _3C in Figure 7C. Also,
When narrowing the width of the synchronization signal to mix the address code, change the synchronization signal deletion gate pulse generation circuit 30 in Figure 6 to a synchronization signal width change gate pulse generation circuit, and replace Φ _3B with Φ in Figure 7D. Just make it _3D . Furthermore, by changing the pedestal level only when the output of the ROM 16 is 1, it is possible to make the presence or absence of a change in the pedestal level correspond to the address code. In this case, AND gate 20 in Figure 6
If is omitted, part of the DC level, ie, the pedestal level, at the portion Φ _3C in Figure 7 changes.

Note that B, C, and D in Figure 7 are B, C, and D in Figure 4.
It corresponds to C and D.

As noted above, the present invention allows address codes to be incorporated into television signals in a manner that is not easily noticed. By putting the video processing circuit 5 shown in FIG. 1 into one chip or physically into one package, when the scrambled composite video signal is descrambled and output, the address code will always be the same as the composite video signal. The address code is mixed into the signal, and when the video signal is viewed on a normal television receiver, the address code is not noticed. Furthermore, since the mixing position is changed pseudo-randomly, it cannot be detected without using a special detector, and it is extremely difficult to remove the address code from the output signal of the video processing circuit 5 and record it on a VTR. .

[Effects of the Invention] As is clear from the above explanation, according to the present invention,
A PN code generation circuit is used in which an address code uniquely assigned to a terminal is mixed into a part of the television signal other than the video signal, and the address code is mixed in a special part of the television signal other than the video signal. Since the horizontal scanning period during which each bit of the address code in the field is inserted is changed pseudo-randomly, it is extremely difficult for outsiders to detect and separate the data, and if unauthorized viewing occurs, it is difficult to identify the source. can be quickly discovered,
This makes it possible to prevent unauthorized copying and unauthorized viewing.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a first embodiment of an address code mixing device according to the present invention, Fig. 2 is a basic circuit diagram of a PN code generation circuit, and Fig. 3 is a block diagram showing a first embodiment of an address code mixing device according to the present invention. FIG. 4 is a waveform diagram showing a color burst, FIG. 4 is a partial waveform diagram of a television signal to explain various methods of inserting address code information, FIG. 5 is an explanatory diagram showing the television signal divided by field, FIG. 6 is a block diagram showing another embodiment of the address code insertion device according to the present invention, and FIG. 7 is a waveform diagram showing various address code insertion methods. [Explanation of symbols], 1...TV tuner, 2...
Video signal descrambler, 7...fsc regeneration circuit,
8... Synchronous signal separation circuit, 9... Slow phase circuit, 10
... Phase advance circuit, 11 ... Transfer gate pulse generation circuit, 12 ... PN code generation circuit, 13 ... Field counter/control circuit, 14 ... Address signal generation circuit, 16 ... ROM.

Claims (1)

[Scope of Claims] 1. A terminal receiving device that outputs a television signal, comprising: a storage means for storing an address code assigned to the terminal receiving device; and a synchronization device for extracting a vertical synchronization signal and a horizontal synchronization signal from the television signal. signal separation means; field counter/control means for counting the vertical synchronization signals and generating the predetermined number of pulses corresponding to each of the predetermined number of vertical synchronization signals; accessing the storage means based on each of the pulses; Address code generation means for generating each bit of the address code in synchronization with the vertical synchronization signal of the television signal; and PN code generation means for generating a PN code in synchronization with the vertical synchronization signal based on each of the pulses. and inserting the contents of each bit of the address code into each of the predetermined number of fields specified by the predetermined number of pulses by changing a part other than the video signal in the horizontal scanning period specified by the PN code. and address code mixing means.