JPH05344168A - Four-phase modulator - Google Patents

Abstract

PURPOSE:To reduce the orthogonal deviation of the modulator by forming a roll-off filter with an FIR digital filter and expressing a carrier with the PCM signal of four-times sampling. CONSTITUTION:The roll-off filter is composed of the FIR digital filter for which the number of taps is M (an odd number). Then, nTb [(n)=integral value and Tb=one symbol period)] and preceding and following (M-1)/2 pieces of data D1 are calculated by a shift register 1, a sample clock is frequency divided into four (signal D3) by a frequency divider 2, this clock is inputted to a binary counter 3 so as to obtain an N-bit parallel signal D2, and these signals are addressed to memories 4A and 4B. Concerning data in a ROM corresponding to the signals D1 and D2, the calculated value of the FIR filter is recorded. The same value is obtained for four clock cycle periods corresponding to the sample clock. The signal D3 is divided into +1 and -1 times values and + or -1 times data are obtained for every two clock cycle periods. Then, these two outputs are alternately applied and the four-phase modulator is constituted.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a quadrature phase modulator.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional four-phase modulator has two P-channel signals 14 and Qch signals 15 and roll-off filters 9A and 9B for removing intersymbol interference. 9 of the baseband signal and carrier signal of
The 0 ° phase shifter 11 converts two sine wave signals and cosine wave signals, which are 90 degrees out of phase with each other, into an analog multiplier 10
Multiply by A and 10B. A quadrature phase modulation (QPSK) signal 16 was output by combining these two signals by the combiner 12.

[0003]

In the conventional four-phase phase modulator described above, since the modulation is performed by the analog signal, the analog multiplier of the analog multiplier may be changed due to the fluctuation of the power supply voltage and the temperature and the difference of the electric characteristics of the individual devices. Due to the imbalance, there is a drawback that the deviation of orthogonality is likely to occur due to the amplitude error and the phase error of the two two-phase PSK modulation signals which are the outputs of the analog multiplier.

[0004]

A four-phase phase modulator of the present invention is a shift register 1A, 1B for converting the binary code of each of the P channel and Q channel to be input into an M (M is an integer) bit parallel signal. And a binary counter 3 for outputting an N (N is an integer) bit parallel signal by the sample clock divided by 4 by the frequency divider 2, and two memories 4 in which the calculated values of the roll-off filter are written in advance.
A and 4B, a data selector 5 that alternately outputs one of the outputs of the two memories 4A and 4B by a sampling clock, a D / A converter 6 that converts this data into an analog signal, and removes harmonic components. And a low pass filter 8 for

[0005]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. The input binary code Pch and Qch signals must be subjected to a roll-off filter that suppresses intersymbol interference. Let these two calculated values be P [nT _s ] and Q [nT _s ] respectively.
Here, n is an integer value. T _s represents the period of the sample clock.

In addition, a carrier signal (called carrier) is
When a PCM signal of double sampling is used (the frequency of the carrier is a quarter frequency of the sample clock f _s , that is, f _s / 4 and the period is 4 T _s ), the waveform (value) of one period of the carrier is as shown in FIG. Like When FIG. 2 is viewed digitally, the two carriers are A [nT _s ] and A ₋₁ [nT
_s ], the outputs of the multipliers 10A and 10B are MUP [n
T _s ], and the output of the multiplier 12 is MUQ [nT _s ], MUP [nT _s ] and MUQ [nT _s ] are (1),
It is represented by (2).

MUP [nT _s ] = A [nT _s ] × P [nT _s ] ... (1) MUQ [nT _s ] = A ₋₁ [nT _s ] × Q [nT _s ] ... (2) Here Thus, A [nT _s ] and A _-1 [nT _s ] are represented as follows.

A [nT _s ] = mod {(mod (n / 4) -1) / 2} = (0,1,0, -1,0,1,0, -1, ...) A _-1 [NT _s ] = mod {(mod ((n + 1) / 4) -1) / 2} = (1,0, -1,0,1,0, -1,0, ...) Note that mod (a / B) indicates the remainder when a is divided by b.
These two are combined, that is, the result of addition is S0
If [nTs] is given, the equation (3) is obtained.

S ₀ [nT _s ] = MUP [nT _s ] + MUQ [nT _s ] ... (3) This state is schematically shown in FIG. The above calculation is configured by the memories (for example, ROM) 4A and 4B and the data selector 5 as shown in FIG. First, only Pch will be described. Number of taps of roll-off filter M (M is an odd number)
FIR (Finite Impulse Response)
nse) A digital filter is used. For this, the calculation result is written in the memory 4A in advance. That is, since the calculated value of the FIR filter at the time of nT _b (T _b is one symbol period) is calculated by looking at (M−1) / 2 pieces of data before and after that, nT _b is calculated by the shift register 1.
_b and before and after (M-1) / 2 data (this data is D1
Then, the sample clock is divided by 4 by the frequency divider 2 (this signal is D3) and is input to the binary counter 3 with this clock to obtain an N-bit parallel signal (this signal is D2). And). These D1, D2 and D3 are stored in the memory 4
Address. This state is shown in FIG. Also, M =
FIG. 6 shows the timings of the three signals in the case of 3 and N = 3. Further, the relationship between the symbol rate f _b and the sample clock f _s is expressed by the equation (4) in this embodiment. f _s = f _b × 2 ^{N + 2} (4) The ROM data for the addresses D1 and D2 records the calculated values of the FIR filter with the number of taps M and the number of samples N (the number of samples N is 1 It is shown that the symbol period is represented by N calculated values). For sample clock, four clock cycles (4T _s) identical P [n
T _s ]. Then, it is divided into a value that is +1 times and a value that is -1 times that of D3.
Data that is multiplied by ± 1 is obtained every two clock cycle periods. The Qch has the same configuration. Two ROMs
R [nT _s ] and R _-1 [nT _s ] which are the data of are represented by the formula (5).

R [nT _s ] = C [nT _s ] × P [nT _s ] R ₋₁ [nT _s ] = C [nT _s ] × Q [nT _s ] ... (5) where C [nT _s] ] = (1,1, -1, -1, -1,1,1,
-1, ...) Next, when the output data selectors 5 of the two ROMs alternately output, the output S [nTs of the data selector 5 is output.
] Is represented like Formula (6).

S [nT _s ] = D [nT _s ] × R [nT _s ] + D ₋₁ [nT _s ] × R ₋₁ [nT _s ] ... (6) where D [nT _s ] = mod ( (N + 1) / 2) = (0,1,0,1,0,1, ...) D _-1 [nT _s ] = mod (n / 2) = (1,0,1,0,1,0 , ...) Here, the formula (6) is obtained from the formula (5) as follows: S [nT _s ] = D [nT _s ] × C [nT _s ] × P [nT _s ] + D ₋₁ [nT _s ] × C [nT _s ] × Q [nT _s ] ... (7) where D [nT _s ] × C [nT _s ] = (0, 1, 0, -1,
0, 1, ...) D _-1 [nT _s ] × C [nT _s ] = (1, 0, -1, 0,
1,0, ...) Equation (8) is derived from Equations (1), (2), (3), and (7).

S [nT _s ] = S ₀ [nT _s ] ... (8) Further, the relationship between the frequency of the sample clock (f _s ) and the frequency of the carrier (f _c ) and the symbol rate (f _b ) is ( Equation 9) is obtained.

F _c = f _s / 4 = 2 ^N × f _b (9) As described above, the values calculated by the roll-off filter multiplied by ± 1 are written in the two memories in advance, and the two cycles are written. A QPSK modulator can be constructed by alternately outputting the forces by the data selector.

Since the signal obtained above is equal to the PCM signal of the QPSK modulated wave, it can be converted into an analog signal by the D / A converter 6. FIG. 7 shows a spectrum of an analog signal, and harmonics are cut by the low pass filter 7. Further, the frequency converter 8 converts the frequency to a desired frequency.

[0015]

As described above, the present invention processes the digital signal by forming the roll-off filter of the conventional example of the four-phase phase modulator by the FIR digital filter, and in particular, the carrier of 4 times sampling is used. By expressing it as a PCM signal, the calculation of modulation can be composed of a memory and a data selector. This has the effect of reducing the deviation of orthogonality in the conventional modulator using an analog signal. Also, because it can be processed with digital signals, IC
There is an effect that the miniaturization of the device can be achieved by downsizing.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional four-phase modulator.

FIG. 3 is a waveform diagram of the present embodiment.

FIG. 4 is an operation explanatory diagram of the present embodiment.

FIG. 5 is a block diagram of a main part of this embodiment.

FIG. 6 is a waveform diagram of the present embodiment.

FIG. 7 is a spectrum explanatory diagram of the present embodiment.

[Explanation of symbols]

 1A, 1B shift register 2 frequency divider 3 binary counter 4A, 4B memory (ROM) 5 data selector 6 D / A converter 7 low-pass filter 8 frequency converter 9A, 9B roll-off filter 10A, 10B analog multiplier 11 90 Degree phase shifter 12 Combiner

Claims (2)

[Claims] 1. A shift register 1A, 1B for converting a binary code of each of P channel and Q channel input into an M (M is an integer) bit parallel signal, and a sample clock divided by 4 by a frequency divider 2. A binary counter 3 for outputting an N (N is an integer) bit parallel signal, two memories 4A and 4B in which the calculated values of the roll-off filter are written in advance, and these two memories 4A and 4B.
A data selector 5 for alternately outputting one of the outputs of the above-mentioned by a sampling clock, a D / A converter 6 for converting this data into an analog signal, and a low-pass filter 8 for removing harmonic components. 4 phase modulator. 2. The quadrature phase modulator according to claim 1, wherein the frequencies of carrier signals which are 90 degrees out of phase with each other are expressed by a PCM code of quadruple sampling.