JPH0533833B2 - - Google Patents
Info
- Publication number
- JPH0533833B2 JPH0533833B2 JP62119372A JP11937287A JPH0533833B2 JP H0533833 B2 JPH0533833 B2 JP H0533833B2 JP 62119372 A JP62119372 A JP 62119372A JP 11937287 A JP11937287 A JP 11937287A JP H0533833 B2 JPH0533833 B2 JP H0533833B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- wire
- film forming
- forming apparatus
- tray
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Description
[産業上の利用分野]
本発明は製膜装置に関する。さらに詳しくは、
アモルフアスシリコン系太陽電池の半導体層もし
くは裏面電極を形成する際に用いられる製膜装置
であつて、基板の膜形成面に密着するよう細線の
ワイヤが設けられているので、製膜と同時にパタ
ーン化を行なうことができ、パターニング工程を
不要とし、それにより大幅なコストダウンを図る
ことのできる製膜装置に関する。
[従来の技術および発明が解決しようとする問題
点]
従来より、集積化のためにレーザ光などのエネ
ルギービームを利用してアモルフアスシリコン層
や裏面電極のパターン化が実施されている。
しかしながら、アモルフアスシリコン層にレー
ザパターニングを行なうばあい、透明電極へのダ
メージにより太陽電池の性能が低下したり、レー
ザスクライブ部分での透明電極と裏面電極との接
触抵抗が経時的に変化(抵抗の増加)したりする
などの問題があつた。また、裏面電極のレーザパ
ターニングは作業難度が高く、安定生産ができな
いという欠点がある。したがつて、エツチング法
やリフトオフ法といつた他の方法を採用せざるを
えず、このばあいには処理工程の増大、生産性の
低下による製造コストの上昇および歩留りの低下
という別の問題を発生していた。さらに、前記い
ずれのばあいにおいても、アモルフアスシリコン
層または裏面電極を形成したのちにパターニング
が行なわれるため、工程が多くなるとともにそれ
に起因して製造コストが増大していた。
本発明は、前記の点に鑑み、太陽電池の性能を
低下させることがなく、製膜工程とパターニング
工程とを同時に行なうことのできる製膜装置を提
供することを目的とする。
[問題点を解決するための手段]
本発明の製膜装置は、アモルフアスシリコン系
太陽電池の半導体層または裏面電極を形成する際
に用いられる製膜装置であつて、基板を収容する
本体と、基板を該本体に固定しかつ位置決めする
手段と、基板の膜形成面側に設けられ該基板の膜
形成面に実質的に密着されるべき複数の細線のワ
イヤとからなることを特徴としている。
[実施例]
つぎに図面に基づき本発明の製膜装置を説明す
る。
第1図は基板をセツトする前の本発明の製膜装
置の一実施例の平面図、第2図は第1図の製膜装
置に基板をセツトした状態のA−A線拡大断面図
である。
以下、プラズマCVD装置に適用するばあいの
本発明の製膜装置の実施例について説明するが、
本発明はプラズマCVD装置に限らず他のスパツ
タ装置、蒸着装置などの膜形成用装置にも広く適
用が可能である。
第1〜2図において、1は半導体層および裏面
電極がその上に形成される、たとえば板ガラスか
らなる基板である。この基板上には酸化スズなど
からなる透明電極がCVD法などにより形成され、
そののち該透明電極はレーザースクライブ法また
はエツチング法などによつてパターン化される。
2は製膜装置の本体に取り付けるCVDトレー
本体3であり、該トレー本体2の基板1収容部の
上方には複数の細線のワイヤ3が張設されてい
る。ワイヤ3は一端がトレー本体2に固定されて
おり、他端が張力調節ねじ8に固定されている。
第2図はCVDトレー本体2に基板1がセツト
されている状態を示しており、ワイヤ3側に膜形
成面がくるようにセツトされた基板1は、背板
4、ばね5、背板押え6および背板押え治具7か
らなる固定手段によつてトレー本体2に固定、位
置決めされるとともにワイヤ3に押しつけられ
る。この押しつけは、ばね5の弾性力を利用して
行なわれ、これによりワイヤ3は膜形成面に実質
的に密着した状態に保たれる。そして、ワイヤ3
を膜形成面に密着させることで、プラズマCVD
のような廻り込みの多い装置においても透明電極
面が完全に露出したパターンをうることができ
る。
本実施例の製膜装置では、ワイヤ3の一端が張
力調節ねじ8に固定されており、基板1をトレー
本体2にセツトする前に、またはセツトしたあと
に、この張力調節ねじ8によりワイヤ3の張力を
調節することでワイヤ3と基板1の膜形成面との
密着性をより一層確実にすることができる。
ワイヤ3は一種のマスクの役割を果たし、その
線径を0.08〜2.0mmのあいだで選定することで、
パターン幅を適宜調整することができる。ワイヤ
3の材質は、とくに制限はなく、プラズマCVD、
スパツタリングなどによる製膜処理に耐えうるも
のであればどのようなものをも用いることがで
き、たとえば、ピアノ線A種またはB種、ニツケ
ル−チタン合金線などが用いられる。
また、製膜工程中の熱によるワイヤ3のたるみ
が問題となるばあいは、すべてのワイヤに、また
は何本かのワイヤごとに、さらには各ワイヤごと
に張力調整用のおもりをワイヤ端部に取り付け、
それによつてワイヤ3の張力を一定に保つように
することもできる。さらには、調節ねじにばねを
組み込むことでも、ワイヤ3のテンシヨンをある
程度の範囲に保つことができる。
以上、プラズマCVD装置について述べたが同
じグロー放電装置であるスパツタリング装置にお
いても、まつたく同様の方法で実施することがで
きることは前記したとおりである。また、蒸着装
置では、膜の廻り込みが少なく、同様の方法で充
分実施が可能である。
つぎに本発明の製膜装置を用いて膜を形成する
と同時にパターンニングを行なつた実施例を示
す。
実施例 1
厚さ2.0mmで大きさが150mm×440mmの青板ガラ
ス上に6000Åの酸化スズの透明電極を設け、この
透明電極をレーザビームを用いて所定のパターン
に分離した。このようにしてパターンを形成した
基板1を第1図に示すCVDトレー2に固定した。
基板1の位置決めは、4カ所の基板位置決め治具
9によつて行なつた。細線のワイヤ3は全部で17
本であり、線径(直径)0.3mmのピアノ線B種を
用いた。なお、基板1をCVDトレー2に固定す
る前に張力調節ねじ8によつて各ワイヤの張力を
調整しておいた。基板1を固定した状態を第2図
に示す。
基板1を固定した状態のCVDトレー2をプラ
ズマCVD装置に配置し、基板温度130℃、圧力
1.0Torrにてp型アモルフアスシリコンカーバイ
ドを150Å、基板温度180℃、圧力0.5Torrにてi
型アモルフアスシリコンを6000Å、基板温度180
℃、圧力1.0Torrにてn型微結晶シリコンを300
Å形成した。そののち、CVDトレーを取り出し、
該トレーから基板をはずして、ワイヤによつてマ
スキングされた部分を観察した。半導体層を分離
した17本の分離線の各々について、多少の廻り込
みが認められたものの、えられたデバイスの性能
に影響を及ぼす可能性のある廻り込みは認められ
なかつた。精密投影機を用いて透明電極が完全に
露出している部分について各分離線毎に最小のパ
ターン幅を測定した。結果を第1表に示す。
[Industrial Field of Application] The present invention relates to a film forming apparatus. For more details,
This is a film forming device used to form the semiconductor layer or back electrode of an amorphous silicon solar cell, and because it is equipped with a thin wire so that it is in close contact with the film forming surface of the substrate, it is possible to form a pattern at the same time as film forming. The present invention relates to a film forming apparatus that can perform a patterning process, eliminate the need for a patterning process, and thereby significantly reduce costs. [Prior Art and Problems to be Solved by the Invention] Conventionally, an amorphous silicon layer and a back electrode have been patterned using an energy beam such as a laser beam for integration. However, when laser patterning is applied to an amorphous silicon layer, the performance of the solar cell may deteriorate due to damage to the transparent electrode, and the contact resistance between the transparent electrode and the back electrode at the laser scribed portion may change over time (resistance There were problems such as an increase in Further, laser patterning of the back electrode is difficult to perform and has the disadvantage that stable production cannot be achieved. Therefore, other methods such as the etching method or the lift-off method have to be adopted, and in this case, there are other problems such as an increase in processing steps, an increase in manufacturing costs due to a decrease in productivity, and a decrease in yield. was occurring. Furthermore, in any of the above cases, patterning is performed after forming the amorphous silicon layer or the back electrode, which increases the number of steps and increases the manufacturing cost. In view of the above-mentioned points, an object of the present invention is to provide a film forming apparatus that can simultaneously perform a film forming process and a patterning process without deteriorating the performance of a solar cell. [Means for Solving the Problems] The film forming apparatus of the present invention is a film forming apparatus used for forming a semiconductor layer or a back electrode of an amorphous silicon solar cell, and includes a main body that houses a substrate, and a main body that accommodates a substrate. , comprising a means for fixing and positioning the substrate to the main body, and a plurality of thin wires provided on the film forming surface side of the substrate and to be substantially closely attached to the film forming surface of the substrate. . [Example] Next, a film forming apparatus of the present invention will be explained based on the drawings. FIG. 1 is a plan view of an embodiment of the film forming apparatus of the present invention before a substrate is set, and FIG. 2 is an enlarged sectional view taken along the line A-A of the film forming apparatus of FIG. 1 with a substrate set therein. be. Examples of the film forming apparatus of the present invention when applied to a plasma CVD apparatus will be described below.
The present invention is widely applicable not only to plasma CVD apparatuses but also to other film forming apparatuses such as sputtering apparatuses and evaporation apparatuses. In FIGS. 1 and 2, reference numeral 1 denotes a substrate made of, for example, plate glass, on which a semiconductor layer and a back electrode are formed. On this substrate, a transparent electrode made of tin oxide etc. is formed by CVD method etc.
Thereafter, the transparent electrode is patterned by laser scribing or etching. Reference numeral 2 denotes a CVD tray main body 3 that is attached to the main body of the film forming apparatus, and a plurality of thin wires 3 are stretched above the substrate 1 accommodating portion of the tray main body 2. The wire 3 has one end fixed to the tray body 2 and the other end fixed to the tension adjustment screw 8. Figure 2 shows the substrate 1 set on the CVD tray main body 2, with the substrate 1 set so that the film forming surface is on the wire 3 side, the back plate 4, the spring 5, and the back plate presser. 6 and a back plate holding jig 7, it is fixed and positioned on the tray body 2 and pressed against the wire 3. This pressing is performed using the elastic force of the spring 5, and thereby the wire 3 is kept in substantially close contact with the film forming surface. And wire 3
By bringing the film into close contact with the film formation surface, plasma CVD
Even in devices that involve a lot of turning, it is possible to obtain a pattern in which the transparent electrode surface is completely exposed. In the film forming apparatus of this embodiment, one end of the wire 3 is fixed to a tension adjustment screw 8, and the tension adjustment screw 8 is used to adjust the wire 3 before or after setting the substrate 1 on the tray body 2. By adjusting the tension, the adhesion between the wire 3 and the film-forming surface of the substrate 1 can be further ensured. The wire 3 plays the role of a kind of mask, and by selecting the wire diameter between 0.08 and 2.0 mm,
The pattern width can be adjusted as appropriate. The material of the wire 3 is not particularly limited, and may be plasma CVD,
Any material can be used as long as it can withstand film forming treatment such as sputtering. For example, piano wire of type A or B, nickel-titanium alloy wire, etc. are used. In addition, if sagging of the wire 3 due to heat during the film forming process is a problem, add weights for tension adjustment to all the wires, to each several wires, or even to each wire at the end of the wire. Attach it to
Thereby, it is also possible to keep the tension of the wire 3 constant. Furthermore, by incorporating a spring into the adjustment screw, the tension of the wire 3 can be maintained within a certain range. Although the plasma CVD apparatus has been described above, it is possible to carry out the same method in a sputtering apparatus, which is also a glow discharge apparatus, as described above. In addition, in the vapor deposition apparatus, there is little wraparound of the film, and the same method can be used satisfactorily. Next, an example will be shown in which a film was formed and patterned simultaneously using the film forming apparatus of the present invention. Example 1 A 6000 Å tin oxide transparent electrode was provided on a blue plate glass with a thickness of 2.0 mm and a size of 150 mm x 440 mm, and this transparent electrode was separated into a predetermined pattern using a laser beam. The substrate 1 on which the pattern was formed in this way was fixed to the CVD tray 2 shown in FIG.
The substrate 1 was positioned using substrate positioning jigs 9 at four locations. Thin wire 3 is 17 in total
A type B piano wire with a wire diameter (diameter) of 0.3 mm was used. Note that before fixing the substrate 1 to the CVD tray 2, the tension of each wire was adjusted using the tension adjustment screw 8. FIG. 2 shows a state in which the substrate 1 is fixed. The CVD tray 2 with the substrate 1 fixed is placed in a plasma CVD device, and the substrate temperature is 130°C and the pressure is
p-type amorphous silicon carbide at 150 Å at 1.0 Torr, substrate temperature 180℃, pressure 0.5 Torr
Type amorphous silicon at 6000 Å, substrate temperature 180 Å
N-type microcrystalline silicon at 300 °C and 1.0 Torr pressure.
A was formed. After that, take out the CVD tray and
The substrate was removed from the tray and the portion masked by the wire was observed. Although some amount of wraparound was observed for each of the 17 separation lines that separated the semiconductor layers, no wraparound that could affect the performance of the resulting device was observed. Using a precision projector, the minimum pattern width was measured for each separation line in the part where the transparent electrode was completely exposed. The results are shown in Table 1.
【表】
なお、透明電極のパターン線の端部と半導体層
の分離線の透明電極パターン線に近い方の端部と
の間隔は約150μmであつた。
こうしてえられた半導体分離基板を半導体面を
ワイヤ側にして第1図と同方式のスパツタトレー
に固定した。このスパツタトレーでは、17本のワ
イヤはそれぞれ第1図に示すワイヤに対して直角
方向に0.25mmだけずれた位置にあるように配置し
た。さらに、ワイヤの線径を0.2mmに設定した。
なお、基板をスパツタトレーに固定する前に、調
節ねじによつて各ワイヤの張力を調整しておい
た。
つぎに、基板をセツトしたトレーをマグネトロ
ンスパツタ装置に配置し、Ar圧力を6×
10-3Torrに調整し、基板温度80℃にて、5000Å
の厚さのAlを形成した。そののち、基板を取り
出し、裏面電極のAlの分離線を前述の方法で測
定した。Alがマスキングされ完全に半導体層が
露出している部分の最小パターン幅を各分離線毎
に第2表に示す。[Table] Note that the distance between the end of the pattern line of the transparent electrode and the end of the separation line of the semiconductor layer closer to the transparent electrode pattern line was about 150 μm. The semiconductor separation substrate thus obtained was fixed on a sputter tray of the same type as in FIG. 1 with the semiconductor side facing the wire. In this sputter tray, each of the 17 wires was arranged at a position shifted by 0.25 mm in the perpendicular direction with respect to the wire shown in FIG. Furthermore, the wire diameter was set to 0.2 mm.
Note that before fixing the substrate to the sputter tray, the tension of each wire was adjusted using the adjustment screw. Next, place the tray with the substrate set in a magnetron sputtering device, and apply Ar pressure to 6×
Adjusted to 10 -3 Torr, substrate temperature 80℃, 5000Å
Al was formed to a thickness of . Thereafter, the substrate was taken out, and the Al separation line on the back electrode was measured using the method described above. Table 2 shows the minimum pattern width of the portion where Al is masked and the semiconductor layer is completely exposed for each separation line.
【表】
第2表に示すように、裏面電極の分離が不完全
な部分もなく、良好な結果がえられた。
以上のようにしてえられた太陽電池の性能を
AM−1.5近似のパルスシミユレーターで測定し
た。結果を第3表に示す。[Table] As shown in Table 2, there were no parts where the back electrode was incompletely separated, and good results were obtained. The performance of the solar cell obtained in the above manner is
Measured using a pulse simulator approximating AM-1.5. The results are shown in Table 3.
【表】
比較例
実施例と同様にして透明電極をパターン化した
基板を、細線のワイヤが配置されていないという
点を除いて第1図と同様のCVDトレーにセツト
し、ほぼ全面に実施例と同様の条件で半導体層を
形成した。半導体層の分離はYAGレーザを用い
て行なつた。また、Alのスパツタリングについ
ても細線のワイヤは使用せず、ほぼ全面に実施例
と同様の条件で裏面電極を形成し、そののちAl
の分離を化学エツチングにより行なつた。
えられた太陽電池の性能を実施例と同様の方法
で測定した。測定結果を第3表に示す。
[発明の効果]
以上説明したとおり、本発明の製膜装置により
半導体層などの製膜をするときは、レーザなどに
よりパターニングをする必要がないので太陽電池
の性能の低下が防止できるとともに、製膜工程と
パターニング工程とを同時に行なうことができる
ので工程が簡略化され、それにより太陽電池の製
造コストをダウンさせることができるという効果
を奏することができる。[Table] Comparative Example A substrate patterned with transparent electrodes in the same manner as in the example was set in the same CVD tray as in Fig. 1 except that the thin wires were not arranged, and almost the entire surface was coated with the example. A semiconductor layer was formed under the same conditions as above. Separation of the semiconductor layer was performed using a YAG laser. In addition, for Al sputtering, a thin wire was not used, but a back electrode was formed on almost the entire surface under the same conditions as in the example, and then the Al
The separation was carried out by chemical etching. The performance of the obtained solar cell was measured in the same manner as in the example. The measurement results are shown in Table 3. [Effects of the Invention] As explained above, when forming a film such as a semiconductor layer using the film forming apparatus of the present invention, there is no need for patterning using a laser or the like, so deterioration in the performance of solar cells can be prevented, and the production speed can be improved. Since the film process and the patterning process can be performed at the same time, the process is simplified, and the manufacturing cost of the solar cell can thereby be reduced.
第1図は基板をセツトする前の本発明の製膜装
置の一実施例の平面図、第2図は第1図の製膜装
置に基板をセツトした状態のA−A線拡大断面図
である。
図面の主要符号、1…基板、2…CVDトレー、
3…ワイヤ、8…張力調節ねじ。
FIG. 1 is a plan view of an embodiment of the film forming apparatus of the present invention before a substrate is set, and FIG. 2 is an enlarged sectional view taken along the line A-A of the film forming apparatus of FIG. 1 with a substrate set therein. be. Main symbols in the drawing: 1...Substrate, 2...CVD tray,
3...Wire, 8...Tension adjustment screw.
Claims (1)
または裏面電極を形成する際に用いられる製膜装
置であつて、基板を収容する本体と、基板を該本
体に固定しかつ位置決めする手段と、基板の膜形
成面側に設けられ該基板の膜形成面に実質的に密
着されるべき複数の細線のワイヤとからなること
を特徴とする製膜装置。 2 前記ワイヤの張力を調整する機構が設けられ
てなることを特徴とする特許請求の範囲第1項記
載の装置。 3 前記ワイヤの線径が0.08〜2.0mmであること
を特徴とする特許請求の範囲第1項または第2項
記載の装置。[Claims] 1. A film forming apparatus used for forming a semiconductor layer or a back electrode of an amorphous silicon solar cell, which comprises a main body that accommodates a substrate, and a substrate that is fixed to and positioned in the main body. 1. A film forming apparatus comprising: means; and a plurality of fine wires provided on the film forming surface side of a substrate and to be brought into substantially close contact with the film forming surface of the substrate. 2. The device according to claim 1, further comprising a mechanism for adjusting the tension of the wire. 3. The device according to claim 1 or 2, wherein the wire has a wire diameter of 0.08 to 2.0 mm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62119372A JPS63283173A (en) | 1987-05-15 | 1987-05-15 | Film forming apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62119372A JPS63283173A (en) | 1987-05-15 | 1987-05-15 | Film forming apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63283173A JPS63283173A (en) | 1988-11-21 |
JPH0533833B2 true JPH0533833B2 (en) | 1993-05-20 |
Family
ID=14759875
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62119372A Granted JPS63283173A (en) | 1987-05-15 | 1987-05-15 | Film forming apparatus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63283173A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002083984A (en) * | 2000-09-08 | 2002-03-22 | National Institute Of Advanced Industrial & Technology | Solar cell and method of manufacturing the same |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2782273B2 (en) * | 1990-09-07 | 1998-07-30 | 鐘淵化学工業株式会社 | Substrate holding jig for forming patterned thin film |
CN102484156A (en) * | 2009-06-30 | 2012-05-30 | Lg伊诺特有限公司 | Solar cell device and manufacturing method thereof |
-
1987
- 1987-05-15 JP JP62119372A patent/JPS63283173A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002083984A (en) * | 2000-09-08 | 2002-03-22 | National Institute Of Advanced Industrial & Technology | Solar cell and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JPS63283173A (en) | 1988-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4713518A (en) | Electronic device manufacturing methods | |
US4351894A (en) | Method of manufacturing a semiconductor device using silicon carbide mask | |
US6278053B1 (en) | Decals and methods for providing an antireflective coating and metallization on a solar cell | |
US4680855A (en) | Electronic device manufacturing methods | |
JPH0394476A (en) | Manufacture of substrate for selective crystal growth and selective crystal growth method and manufacture of solar cell by using these substrates | |
US5089293A (en) | Method for forming a platinum resistance thermometer | |
JPH0533833B2 (en) | ||
US4719442A (en) | Platinum resistance thermometer | |
US6184058B1 (en) | Integrated thin film solar battery and method for fabricating the same | |
EP0373221A1 (en) | Fabrication method for semiconductor device and film formation apparatus for said method | |
JPS56100451A (en) | Manufacture of electrode of semiconductor device | |
JP2513900B2 (en) | Method for manufacturing semiconductor device | |
JP3182323B2 (en) | mask | |
AU584632B2 (en) | Platinum resistance thermometer | |
JPH0210719A (en) | Method for manufacturing polycrystalline layer with coarse crystal structure for thin film semiconductor devices | |
JPS58182822A (en) | Thin film internal stress relief device | |
JPH0666276B2 (en) | Mask for thin film production | |
JPS60117684A (en) | Method for manufacturing amorphous silicon solar cells | |
JPS6216509A (en) | Manufacture of substrate for semiconductor device | |
JPS63274183A (en) | Patterning method for metal film on transparent substrate | |
JPS6246074B2 (en) | ||
JPH04157720A (en) | Sputtering method | |
JPS62254466A (en) | Method for manufacturing thin film semiconductor devices | |
JPS6017920A (en) | Formation of fine pattern | |
JPS6341083A (en) | Manufacture of thin-film semiconductor device |