JPH05335964A - Delta sigma demodulator - Google Patents

Abstract

PURPOSE:To provide a delta sigma modulator applying dither processing to a square wave in which an optimum square wave to the dither is added to an input signal thereby sufficiently suppressing deterioration in a distortion factor. CONSTITUTION:A variable frequency divider circuit 11 frequency-divides an output of a square wave generating circuit 9. A frequency division ratio of the variable frequency divider circuit 11 is controlled by a control signal being an output of a control circuit 10. Then the output of the variable frequency divider circuit 11 is inputted as a dither signal to an adder 1, in which the signal is added to an input signal inputted from an input terminal and subtracted by an output from a D/A converter 8. The output of the adder 1 is outputted to an output terminal via an integration circuit 2, a quantizer 6 and a delay circuit 7 as an output of the delta signal modulator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delta sigma modulator, and more particularly to a delta sigma modulator having a square wave generating circuit.

[0002]

2. Description of the Related Art As a conventional delta-sigma modulator, there is a circuit shown in the block diagram of FIG. 4 (for example, Ever
ard, JD, “A Single Channel PCM Codec”, IEEE Trans.C
ommunication, vol.COM27, no.2, pp283-295, 1979). Figure 4
The conventional delta-sigma modulator shown in (1) is composed of an adder 1, an integrating circuit 2, a quantizer 6, a delay circuit 7, a D / A converting circuit 8 and a square wave generating circuit 9. The adder 1 uses the analog signal input from the input terminal as the first input, and D
The output of the A / A conversion circuit 8 is input as the second input from the minus end, and the output of the square wave generation circuit 9 is used as the third input, and the value obtained by adding the first input and the third input to the second Is subtracted (that is, a signal obtained by inverting the output of the D / A conversion circuit 8 is added), and the result is output. The integrating circuit 2 inputs the output of the adder 1. The quantizer 6 inputs the output of the integrating circuit 2. The delay circuit 7 inputs the output of the quantizer 6. The D / A conversion circuit 8 inputs the output of the delay circuit 7 and performs D / A conversion. The output of the delay circuit 7 is sent to the output terminal and becomes the output of the conventional delta-sigma modulator.

By the way, when an analog signal is A / D converted, when the input signal is small, noise concentrates on harmonics having a frequency that is an integral multiple of the signal frequency, and the total harmonic distortion ratio at a specific input level is reduced. make worse. In such a case, by mixing a signal with a frequency lower than the Nyquist frequency (hereinafter referred to as dither) into the input signal, the apparent input signal is increased and the noise spectrum concentrates at a specific frequency within the signal band. It is possible to suppress the phenomenon.

The delta sigma modulator is a circuit for A / D converting by mixing dither in the input signal as described above.
The square wave dither output from the square wave generation circuit 9 is added to the input signal input from the input terminal in the adder 1, and the output of the delay circuit 7 which is the output of the delta sigma modulator is subtracted. The output of the adder 1 is output to the output terminal via the integrating circuit 2, the quantizer 6 and the delay circuit 7, and becomes the output of the delta-sigma modulator.

The dither mixed in the input signal through the delta-sigma modulator is also included in the data after A / D conversion. However, in the case of an oversampling A / D converter equipped with a decimation filter that is a digital filter that lowers the sampling frequency after the delta-sigma modulator, the dither is set to a period of "2 to the nth power" times the sampling period, Moreover, if a square wave having a frequency higher than the signal frequency is used, the dither can be easily removed by the above decimation filter. Further, the square wave generating circuit 9 for generating the square wave can be easily manufactured.

FIG. 5 is a graph showing frequency characteristics of a 1/32 decimation filter which is an example of the above-mentioned decimation filter. As shown in FIG. 5, 1/32
The decimation filter has a transmission zero at a frequency that is an integral multiple of the final sampling frequency (fs).
If the square wave of the frequency at the transmission zero point is input to the delta-sigma modulator as dither, the dither can be easily removed by the decimation filter.

[0007]

However, in the above-mentioned conventional delta-sigma modulator, the frequency of the square wave output from the square wave generating circuit 9 is constant. Then, the deterioration of the distortion rate at a specific input level depends on the accuracy of the D / A conversion circuit 8 in the feedback loop in the delta-sigma modulator, and the accuracy of the D / A conversion circuit 8 depends on that accuracy. Is hard to predict before manufacturing. Therefore, in the above-mentioned conventional delta-sigma modulator, it is impossible to add a square wave having an optimum frequency to the input signal, and there is a problem that the deterioration of the distortion factor cannot be sufficiently suppressed at a specific input level. is there.

The present invention has been made in view of the above problems, and in a delta-sigma modulator having a square wave as a dither, it is possible to generate an optimum square wave as a dither and sufficiently reduce distortion. It is an object of the present invention to provide a delta-sigma modulator that can be suppressed.

[0009]

A delta-sigma modulator according to the present invention comprises a first input terminal which is an addition terminal for inputting an analog signal from the outside, a second input terminal which is a subtraction terminal and an addition terminal. An adder having a third input terminal, an integrating circuit for inputting the output of the adder, a quantizer for inputting the output of the integrating circuit, and an output for the quantizer for outputting the delta A delay circuit serving as an output of the sigma modulator, a D / A converter for inputting the output of the delay circuit and D / A converting the same to output to a second input end of the adder, and a square wave outputting a square wave. A wave generating circuit, a variable frequency dividing circuit that divides the output of the square wave generating circuit and outputs the result to the third input terminal of the adder, and a control circuit that controls the frequency dividing ratio in the variable frequency dividing circuit. It is characterized by having.

[0010]

In the delta-sigma modulator according to the present invention,
In a delta-sigma modulator having a square wave generation circuit,
The square wave that is the output of the square wave generation circuit is divided by the division ratio controlled by the control circuit in the variable frequency division circuit,
It is input to the adder. Then, the output of the present delta-sigma modulator is evaluated for characteristics such as total harmonic distortion and SN ratio through a decimation filter, and the control circuit is adjusted based on this evaluation to determine the dither of the optimum frequency. It can be added to the input signal at the adder in the delta-sigma modulator. Therefore, the delta-sigma modulator according to the present invention can sufficiently suppress the deterioration of the distortion factor in the output signal.

Further, for example, a variable attenuator is provided between the variable frequency divider circuit and the adder, and the amplitude of the output signal (that is, dither) of the variable frequency divider circuit is adjusted based on the output of the decimation filter. By controlling, the dither is further optimized, and the characteristics such as the distortion rate can be further improved.

[0012]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a delta-sigma modulator according to the first embodiment of the present invention. In FIG. 1, the same components as those of the conventional delta-sigma modulator shown in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

In the delta-sigma modulator according to the first embodiment shown in FIG. 1, a control circuit 10 and a variable frequency dividing circuit 11 are added to the components different from the conventional delta-sigma modulator shown in FIG. It is the part that is being done. The variable frequency dividing circuit 11 is provided at the subsequent stage of the square wave generating circuit 9, and its output serves as the third input of the adder 1. Control circuit 10
The control signal, which is the output of, is input to the variable frequency dividing circuit 11.

Next, the operation of the delta-sigma modulator according to the first embodiment constructed as described above will be described.
The variable frequency dividing circuit 11 divides the output of the square wave generating circuit 9. The frequency division ratio of the variable frequency dividing circuit 11 is controlled by a control signal output from the control circuit 10. Then, the output of the variable frequency dividing circuit 11 is input to the adder 1 as dither and added to the analog input signal input from the input terminal, and further subtracted by the output of the D / A converter 8. The output of the adder 1 is output to the output terminal via the integrating circuit 2, the quantizer 6 and the delay circuit 7 as in the conventional delta-sigma modulator shown in FIG. 4, and becomes the output of the present delta-sigma modulator.

The output of the delta-sigma modulator according to the first embodiment is evaluated through a decimation filter provided in the subsequent stage of the delta-sigma modulator for characteristics such as total harmonic distortion and SN ratio, and based on this evaluation. Variable divider 1
By adjusting the control circuit 10 that controls the frequency division ratio at 1, it is possible to determine the optimum frequency dither.
Then, the control circuit 10 stores the frequency division ratio in the variable frequency dividing circuit 11 and controls the variable frequency dividing circuit 11 so that the output of the variable frequency dividing circuit 11 becomes the dither of the optimum frequency.

As a result, the delta-sigma modulator according to the first embodiment can add an optimum square wave as dither to the input signal, and can sufficiently suppress the deterioration of the distortion factor in the output signal. The characteristics can be obtained.

Next, a delta-sigma modulator according to the second embodiment of the present invention will be described. FIG. 2 is a block diagram showing a delta-sigma modulator according to the second embodiment.
Note that, in FIG. 2, the same components as those of the delta-sigma modulator according to the first embodiment shown in FIG.

In the delta-sigma modulator according to the second embodiment shown in FIG. 2, different constituent parts from the delta-sigma modulator according to the first embodiment shown in FIG. 1 are an attenuator 3 and a second part. The adder 4, the second integrating circuit 5, the second control circuit 12, and the second variable frequency dividing circuit 13 are added. The attenuator 3 is provided after the integrating circuit 2. The second adder 4 adds the output of the attenuator 3 and the output of the second variable frequency dividing circuit 13 and outputs the result to the second integrating circuit 5. The second integrating circuit 5 integrates the output of the adder 4 and outputs it to the quantizer 6. Second control circuit 1
The control signal which is the output of 2 is input to the second variable frequency dividing circuit 13. The second variable frequency dividing circuit 13 receives the square wave signal output from the square wave generating circuit 9, and divides this signal at a frequency division ratio according to the control signal of the second control circuit 12.

The delta-sigma modulator according to the second embodiment is an example in which the present invention is applied to a second-order delta-sigma modulator. A variable frequency dividing circuit 11 and a second variable frequency dividing circuit 13 are provided in front of the integrating circuit 2 and the second integrating circuit 5, respectively, and the variable frequency dividing circuit 11 and the second variable frequency dividing circuit 13 are further provided.
The frequency division ratio is controlled by the control circuit 10 and the second control circuit 12, respectively. Therefore, the dither added to the input signal in the adder 1 and the dither added to the input signal in the second adder 4 are independently controlled by the control circuit 10.
And can be optimized by the second control circuit 12.

As a result, the delta-sigma modulator according to the second embodiment can add a more optimal square wave to the input signal as dither, and can obtain better characteristics.

Next explained is a delta-sigma modulator according to the third embodiment of the invention. FIG. 3 is a block diagram showing a delta-sigma modulator according to the third embodiment.
Note that, in FIG. 3, the same components as those of the delta-sigma modulator according to the first embodiment shown in FIG.

In the delta-sigma modulator according to the third embodiment shown in FIG. 3, the components different from those of the delta-sigma modulator according to the first embodiment shown in FIG. That is, a terminal and a voltage amplitude control terminal are provided, and a variable attenuation circuit 12 is added. The control circuit 10 outputs a frequency control signal and a voltage amplitude control signal from the frequency control terminal and the voltage amplitude control terminal, respectively, based on the output of the decimation filter provided in the subsequent stage of the present delta sigma modulator. The variable frequency dividing circuit 11 frequency-divides the square wave signal output from the square wave generating circuit 9 based on the control signal (frequency control signal) output from the control circuit 10, as in the first embodiment. ..
In addition, the variable attenuator circuit 12 is an attenuation amount based on the voltage amplitude control signal output from the control circuit 10, and the variable frequency divider circuit 1
Attenuate the voltage amplitude of the 1 output signal.

In the present embodiment, the amplitude of the output of the variable frequency dividing circuit 11 can be attenuated to an arbitrary voltage amplitude by the variable attenuating circuit 12, so that the optimum dither amplitude can be determined. That is,
In the present embodiment, the signal output from the output terminal is passed through a decimation filter to evaluate characteristics such as total harmonic distortion and SN ratio, and the frequency and amplitude of dither are adjusted based on the results. Then, when the frequency and amplitude of the dither become optimum, the state at that time is changed to the control circuit 10.
Memorized in. As a result, the delta-sigma modulator according to the present embodiment can obtain even better characteristics than the first embodiment.

[0025]

As described above, according to the delta-sigma modulator of the present invention, the variable frequency dividing circuit for dividing the output of the square wave generating circuit and the control for controlling the frequency dividing ratio in the variable frequency dividing circuit. Circuit, the optimum dither can be added to the input signal by externally controlling the control circuit based on the output of the delta-sigma modulator. Therefore, the delta-sigma modulator according to the present invention can obtain good characteristics such that deterioration of the distortion factor in the output signal can be sufficiently suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a delta-sigma modulator according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a delta-sigma modulator according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a delta-sigma modulator according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional delta-sigma modulator.

FIG. 5 is a graph showing an example of frequency characteristics of a decimation filter added after the delta-sigma modulator.

[Explanation of symbols]

 1; adder 2; integration circuit 6; quantizer 7; delay circuit 8; D / A conversion circuit 9; square wave generation circuit 10; control circuit 11; variable frequency divider circuit 12; variable attenuation circuit

Claims (2)

[Claims] 1. An adder having a first input terminal, which is an addition terminal for inputting an analog signal from the outside, a second input terminal, which is a subtraction terminal, and a third input terminal, which is an addition terminal, and the addition. Circuit for inputting the output of the quantizer, a quantizer for inputting the output of this integrating circuit, and a delay circuit for inputting the output of this quantizer and the output being the output of the present delta-sigma modulator,
A D / A converter for inputting the output of the delay circuit, D / A converting it and outputting it to the second input terminal of the adder, a square wave generating circuit for outputting a square wave, and a square wave generating circuit for the square wave generating circuit. A delta-sigma modulator having a variable frequency dividing circuit for frequency-dividing an output and outputting it to a third input terminal of the adder, and a control circuit for controlling a frequency dividing ratio in the variable frequency dividing circuit. .. 2. A variable attenuator circuit is provided between the variable frequency divider circuit and the third input terminal of the adder to attenuate the output signal of the variable frequency divider circuit to control the amplitude. The delta-sigma modulator according to claim 1, wherein: