JPH0533532B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor devices, and particularly to integrated circuit chips (hereinafter referred to as LSI chips) having multiple terminals.
The present invention relates to a semiconductor device having an improved bump structure.

[Conventional technology]

Conventionally, electrical inspection and terminal connection of this type of LSI chip have been carried out by forming a single row of connection bumps around the periphery of the LSI chip, and using the well-known TAB ( Tape
This was done using Automated Bonding technology.

[Problem that the invention seeks to solve]

3 and 4 are a sectional view and a plan view of a conventional example. 1 has a single row of connection bumps on the periphery
This is an LSI chip, and gold-plated input/output terminals 4 formed on an insulating film 7 with a width of 35 mm are connected to connection bumps 2. As shown in FIG. 3, the gold-plated terminal 4 is in the state of a cantilever without the support of the insulating film 7 at the connection part with the LSI chip. On the other hand, if the terminal pitch is narrowed for multi-terminal connection, the terminal width must also be narrowed. As a result, the terminal strength becomes weak, and the terminal becomes deformed, making it easy to cause electrical shoots at the ends of the LSI chip.

Furthermore, as shown in Fig. 4, the connection bump 2 is connected to the LSI
In an LSI chip that requires many input/output terminals to be formed in a single row around the chip, the spacing between the connection bumps 2 must be narrowed. Therefore, in an LSI chip that requires many input/output terminals, if you want to secure the necessary distance between connection bumps and form many connection bumps in a single row around the LSI chip, , LSI chip size increases, yield decreases, and cost increases.

In this way, since the connection bumps of conventional LSI chips are formed in a single row around the periphery of the LSI chip, it is difficult to form the necessary input/output terminals in semiconductor devices that require many input/output terminals. The disadvantage was that it was difficult to It also had the disadvantage of causing electrical shoots at the edges of the LSI chip (between the connection bump and the LSI chip edge).

[Means for solving problems]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to provide a semiconductor device having a large number of input/output connection bumps and shot prevention bumps.

The semiconductor device of the present invention includes a plurality of first connection bumps in one row substantially parallel to each side of the four peripheral parts on the surface, and two rows of first connection bumps provided in parallel to one side of the peripheral part. an integrated circuit chip comprising: a plurality of second connection bumps disposed substantially centrally; and a plurality of shot prevention bumps provided on the outside of the first and second connection bumps; an insulating film in which test electrodes and electrical conductors are connected, and a center line of each of the second connection bumps in a direction perpendicular to the one side is between the first connection bumps. It is characterized by being located.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a plan view showing the embodiment.

As shown in Figures 1 and 2, LSI chip 1
Gold-plated connection bumps 2 and shot prevention bumps 3 are formed on the inside of the surface and around the four sides by a well-known plating technique. Connection bump 2 is
Each peripheral part has one row, and the central one has two rows.
The rows are parallel to and perpendicular to one peripheral row and are arranged such that a centerline perpendicular to that row is located between the peripheral rows.

On the other hand, the LSI chip accommodating portion 8 of the insulating film 7 is punched out from the front, copper foil is closely adhered onto the insulating film 7, and a plurality of predetermined input/output terminals 4, wiring patterns 5, and test electrodes 6 are attached. It is formed using well-known etching and gold plating techniques.

Furthermore, the plurality of connection bumps 2 arranged and formed as described above and the plurality of input/output terminals 4 are aligned one-to-one, and the two are connected by a well-known connection technique (for example, thermocompression bonding).

Further, at least one shot prevention bump 3 (one in this embodiment) is formed below the input/output terminal 4 between the connection bump and the chip edge.

In this way, a semiconductor device having many input/output terminals is realized.

〔Effect of the invention〕

As explained above, the present invention firstly provides a large number of input/output terminals by arranging a plurality of connection bumps formed inside and on the periphery of an LSI chip in a staggered manner in columns so that they do not overlap. Second, by forming at least one shot prevention bump on the chip surface between the connection bump and the chip edge and on each input/output terminal connected to the connection bump, This prevents the input/output terminals from coming into contact with the LSI chip and causing electrical shock, and thirdly, the connection bumps are also present inside the LSI chip.
This has the effect of making it easier to design the connection between input/output terminals and internal circuits on an LSI chip, that is, layout design.

[Brief explanation of the drawing]

FIGS. 1 and 2 are cross-sectional views of an embodiment of the present invention,
The plan view, FIGS. 3 and 4 are a sectional view and a plan view of the conventional example. 1... LSI chip, 2... Connection bump, 3... Shoot prevention bump, 4... Input/output terminal, 5... Wiring pattern, 6... Test electrode, 7... Insulating film, 8...
LSI chip storage section.

Claims (1)

[Claims] 1. A plurality of first connection bumps in one row provided substantially parallel to each side of the four peripheral portions on the surface, and arranged approximately in the center in two rows parallel to one side of the peripheral portion. an integrated circuit chip comprising a plurality of second connection bumps, and a plurality of shot prevention bumps provided on the outside of the first and second connection bumps; and a plurality of test electrodes on the surface thereof. an insulating film connected to an electrical conductor, and a center line of each of the second connection bumps in a direction perpendicular to the one side is located between the first connection bumps. semiconductor devices.