JPH05333829A - Information processor - Google Patents

Abstract

PURPOSE:To perform reduction processing by thinning out display data with no delay of display processing without depending upon software. CONSTITUTION:A bus 20 is connected to a CPU and supplies a chip select signal and an address strobe signal to a display system and also supplies an address and display data as well. The display system returns an ACK signal indicating the end of access to the bus 20. A subcontroller 11 processes and transmits an address to be sent to a buffer memory 12, a synchronizing signal, a CPU cycle for reading and writing display data through the bus 20, a refreshment cycle for refreshing the buffer memory 12, and a transfer cycle for transferring display data in the buffer memory 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device.

[0002]

2. Description of the Related Art In an information processing apparatus, the following two methods are currently implemented for the case where a physical screen is smaller in resolution than a logical screen.

(1) A part of the logical screen is cut out and displayed on the physical screen.

Some of the cutout portions are designed so that the user can specify them. In this case, the cutout portion of the screen can be determined by an input device such as a mouse.

(2) The screen is thinned and reduced to 1 / n.

In (1), there is a display controller having such a function in terms of hardware. It is known that (2) is realized by software.

FIG. 17 shows an example of the method (1). The physical screen can move within the logical screen like a window.

FIG. 18 shows an example of the method (2). In this example, the physical screen is 1 / horizontal in the logical screen
It is thinned out to 2.

[0009]

According to the prior art, the method of thinning out a screen and reducing it to 1 / n is a method by software, and it is a function possessed by a specific application and any application can be used. Do not mean.

As an example of the method, there is a method of transferring display data to the main memory, reducing the size of the display data, and transferring to the display buffer memory. Therefore, there is a problem that the processing speed of data display is reduced, and the user-usable area in the main memory is reduced.

Therefore, the present invention provides an information processing apparatus which does not depend on software and is therefore effective for any application software, and can reduce display data by thinning display data without delay in display processing. To do.

[0012]

According to the present invention, a buffer memory, a display device for displaying display data stored in the buffer memory, and a CPU via a bus are connected to display the buffer memory. First control means for controlling writing and reading of data and controlling output of display data from the buffer memory to the display device, and a logical screen in the display device which is connected to the first control means. To reduce the display data to meet
Address sent from the control means of to the buffer memory,
A buffer memory is processed by processing a synchronization signal, a CPU cycle for reading and writing display data via a bus, a refresh cycle for refreshing a buffer memory, and a transfer cycle for transferring display data in the buffer memory. An information processing apparatus having a second control means for transmitting the information is provided.

[0013]

When the display data stored in the buffer memory is thinned and reduced, the second control means reduces the display data so that the logical screen fits the physical screen.
Address sent from the control means of to the buffer memory,
A buffer memory is processed by processing a synchronization signal, a CPU cycle for reading and writing display data via a bus, a refresh cycle for refreshing a buffer memory, and a transfer cycle for transferring display data in the buffer memory. Send to. Specifically, the address is thinned out, and the processing of the transfer cycle for thinning out the horizontal lines and the processing of the refresh cycle and the CPU cycle are executed.

[0014]

Embodiments of the information processing apparatus according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a display system of an embodiment of an information processing apparatus according to the present invention, and FIG. 2 is a block diagram corresponding to FIG. 1 and showing terminal names in detail. Is.

The display system of the information processing device is a bus 20.
The display controller 10 corresponding to the first control means and the sub-controller 1 corresponding to the second control means connected to the
1, a buffer memory 12, a color palette 13 and a display device 14.

This display system is a dumb frame buffer type display system, and a C system is provided via a bus 20.
It is connected to a PU (not shown) and operates as a slave to the bus 20. A chip select signal and an address strobe signal are supplied to the display system via the bus 20, and an address and display data are also supplied.

The display system is an AC indicating the end of access.
Return the K signal to bus 20. The display controller 10 allocates a plurality of bits per pixel, and the host controls the buffer memory 1
Writing / reading to / from the memory 2 is supported, an interface with the bus 20 is performed, and output of display data from the buffer memory 12 to the display device 14 is controlled. As the buffer memory 12, for example, a dual port memory is used. The display device 14 is a device that converts the display data from the buffer memory 12 into colors. A flat panel or a CRT is used as the display device 14.

The display controller 10 controls the buffer memory 12 by defining the upper left corner of the screen as the address 0 of the buffer memory 12 and increasing the address from left to right and from top to bottom. Also, the buffer memory 12
Are arranged in parallel so that display data for four pixels can be output at one time. The length of the serial access memory of the dual port memory used as the buffer memory 12 is, for example, 512, and the resolution of the screen is 1 for the logical screen.
152 × 900, and the physical screen is 640 × 480, for example. In this case, the buffer memory 12 is accessed 1152/4 = 288 times during one horizontal scanning of the logical screen. Decimation for reduction is 1 / horizontal and vertical
If it is set to 2, the pixels are thinned out as shown in FIG.
The number string described in each pixel indicates the vertical coordinate in front and the horizontal coordinate in the rear.

As shown in FIG. 2, the sub-controller 11
Among the signals transmitted between the display controller 10 and the buffer memory 12, are address and control signals (low active row address selection signal RAS, low active column number selection signal CAS, low active OE, low active The write activation signals WE and SC) are fetched, processed, and sent to the buffer memory 12. The sub-controller 11 also sends the signal ACK originally attributed to the display controller 10 to the bus 20 to the bus at a different timing. The sub controller 11 and the display controller 10 are R
Timing signal (HSYN) sent to AMDAC16
C, VSYNC, low active BLANK, XC
K) also changes the timing and sends it to the RAMDAC 16.

As the buffer memory 12, what is called a dual port memory as described above can be used. The buffer memory 12 has a DRAM and an SRAM (SAM) having a small capacity in addition to the DRAM (not shown). Both data ports are separate and DR
The display data transfer between the AM and the SRAM is executed by a kind of cycle called a transfer cycle. The size of the SAM is, for example, 512 × n (n = 4 or 8).

FIG. 4 shows a synchronization signal generated by the display controller 10 and the sub controller 11.

VSYNC, HSYNC, and BLANK
Is a synchronization signal similar to the conventional one, which is generated by the display controller 10. VSYNC is a signal that becomes active once per frame, and becomes active during the blanking period in the vertical direction.
HSYNC is a signal that becomes active during each horizontal blanking period. BLANK is a signal that becomes active during the horizontal and vertical blanking periods.

VS and HS are signals generated by the sub-controller 11 and are HSYNC, VSYNC, and BLANK.
It is made based on. However, this does not need to be synchronized except for the start of the vertical blanking period. Display controller 1 during vertical blanking period
Since 0 often has a function of returning its state in an internal register, this period is adjusted.

FIG. 5 shows the timing of the dot lock signal SXCK before and after HS and the display data DATA of the signals output from the sub controller 11.

In DATA, the first number 637 indicates the vertical coordinate, and the number after the HS signal active indicates the horizontal coordinate in the physical screen. In the horizontal direction, since four pixels are output at one time, the numbers are every four.
Note that this does not correspond to the numbers shown in FIG.

6 to 8 are used in this embodiment,
The timings of three types of cycles in the buffer memory are shown.

FIG. 6 shows a CPU cycle, which is a cycle used for reading and writing display data from the bus side to the buffer memory. RAS becomes active before CAS, and OE is at high level when RAS falls.

FIG. 7 shows a refresh cycle in which the contents of the buffer memory are refreshed. RAS becomes active after CAS, and CAS
RAS is at the high level at the trailing edge of.

FIG. 8 shows a transfer cycle. Used when transferring display data from DRAM in buffer memory to SAM. When OE falls, RAS is at high level.

As shown in FIG. 2, the buffer memory 12
The data bus latch switching circuit 15 connected between the RAMDAC 16 and the RAMDAC 16 is used for horizontal thinning. The buffer memory 12 uses four pixels of display data in parallel for the SAM.
Although output from the port, the pixels actually required for thinning out as shown in FIG. 3 are the first and third pixels, or the second and fourth pixels. Since the RAMDAC 16 is of a type that inputs 4 pixels at a time, the outputs from the buffer memory 12 twice are collected together.
To enter. In order to realize this, it is necessary to latch the output from the buffer memory 12 the first time. Each port is switched or latched as shown in FIG. 9 depending on whether the screen is reduced or not.

FIG. 10 shows the timing for the port A shown in FIG.

SCK is a SAM clock and PAI is S
This is the output data from the AM. PAI is output with a delay from the rising edge of SCK. This is read into the latch by the LAT signal. The output of the latch is shown at PAI (latch). RAM for this PAI (latch) and PAI together
Input to DAC and SCLK to LD terminal of RAMDAC. The type of RAMDAC having analog outputs R, G, B is used when connected to a CRT, and the type having a digital output without passing through the RAMDAC is used when connected to a flat panel. ..

FIG. 11 is a detailed block diagram of the sub-controller.

The sub-controller is a generation circuit and detection circuit for the three types of cycles in the above-mentioned buffer memory, that is, a CPU access detection circuit 30, a CPU cycle generation circuit 31, a refresh detection circuit 32, a refresh cycle generation circuit 33, And transfer cycle /
An address generating circuit and a synchronizing signal generating circuit 34 are provided.

The CPU access detection circuit 30 has a VRA
S, VCAS, VOE, and VWE are input, and HSYNC, VSYNC, BLANK, and XCK are input to the transfer cycle / address generation circuit and synchronization signal generation circuit 34.
Is entered.

The three types of cycles have priorities. It is (1) transfer cycle (2) refresh cycle (3) C
It is in the order of PU access cycles. Here, the transfer cycle occurs in the sub-controller, but this is given the highest priority because the display is destroyed if the timing is deviated. Therefore, neither the refresh cycle nor the CPU cycle is enabled during this transfer cycle. Next, the refresh detection circuit 32 of the sub-controller detects a refresh cycle and if it is not a transfer cycle, the refresh cycle generation circuit 3
At 3, the refresh cycle is generated. If it is in a transfer cycle, it is generated after that. The CPU access cycle is detected by the CPU access detection circuit 30, and the CPU cycle generation circuit 31 generates a CPU cycle if it is not in the other two types of cycles, and if so, it is inserted after that. Since the CPU access cycle notifies the bus of the end of the cycle by the ACK signal, the cycle can be made to wait by using this.

FIG. 12 is a block diagram showing details of the transfer cycle / address generating circuit and the synchronizing signal generating circuit 34 shown in FIG. This circuit also includes a synchronizing signal generating circuit.

The transfer cycle / address generation circuit and the synchronization signal generation circuit 34 are provided in the vertical blank start detection circuit 4
0, a vertical display period counter 41, a vertical synchronization signal generation circuit 42, a vertical blank period counter 43, a horizontal display period counter 44, a horizontal synchronization signal generation circuit 45, and a horizontal blank period counter 46, and a serial access. A memory cycle 47, a horizontal start address adding circuit 48, a subtracting circuit 49, a transfer address selecting circuit 50, a row address incrementing / column address clearing circuit 51, and a transfer cycle / address generating circuit 52 are provided. ..

The sync signal generating circuit has a function of counting and generating a predetermined display period, blanking period, and sync signal period for horizontal and vertical directions. The vertical blank start detection circuit 40 is a circuit that synchronizes with the timing on the display controller side, and detects the vertical blanking timing for each frame for synchronization.

Next, the transfer cycle timing and address will be described.

FIG. 13 shows the location of the transfer cycle when the screen is not reduced. 9 lines from the top of the screen are shown, and the shaded portion is the position of the transfer cycle. The SAM transfers display data 1152/4 = 288 times during one line, and the transfer occurs even in the middle of the line because the SAM has a size of 512 × n. However, since the display data is continuous, it is not necessary to insert a transfer cycle for each line. The numbers in the figure indicate the SAM address at that position.

FIG. 14 is an explanatory diagram showing the position of the transfer cycle when the screen is reduced by the display system of this embodiment. This corresponds to the extracted odd line in FIG. In this case, a transfer cycle is required because the addresses are discontinuous for each line. This is realized by the transfer cycle / address generation circuit shown in the block diagram of FIG.

The horizontal start address adding circuit 48 reads 0 at the beginning of the frame and outputs 1152/4 for each line.
× 2 = Add 576 each. This is the start address of the line. At the same time, the lower 9 bits of the horizontal start address adder circuit subtracted from 512 are set in the serial access memory counter and counted down for each pixel, and if it becomes 0 in the middle of the line, a transfer cycle is generated. The transfer address at this time is 1 for the row address of the horizontal start address addition circuit by the row address increment / column address clear circuit.
Becomes the row address, and the SAM address is output as 0 on the VAX bus. The above two types of transfer cycles are selected by the transfer address selection circuit. The transfer cycle generating circuit is triggered by the above-mentioned two types of transfer signals to generate control signals (RAST, CAST, O
ET, WET) is generated.

FIGS. 15 and 16 show how the timing of each cycle of the buffer memory changes on the bus side, the display control side and the sub control side.

FIG. 15 is a timing chart when the access from the bus side and the transfer cycle of the buffer memory from the sub controller overlap. AS, CS or REA to access the buffer memory from the bus
D becomes active, and accordingly, the display controller sets VRAS, VCAS, and VOE in the read mode, and these signals are input to the sub controller. At this time, in the sub controller, the refresh and CPU cycle prohibition XC signals indicating the transfer cycle are active. XC has been active shortly before the actual transfer cycle. This is because even if a transfer cycle is already inserted when a CPU cycle or a refresh cycle is about to start, a malfunction will occur if the CPU cycle or the refresh cycle is interrupted, and if the transfer cycle is moved backward, the display screen collapses. , C
This is because it is necessary to activate the XC signal that inhibits the PU cycle and the refresh cycle at least one cycle earlier. The sub-controller detects that the display controller has started a CPU cycle at point A in FIG. 15, but since XC is active at this time, it does not send a CPU cycle to the buffer memory but first issues a transfer cycle to issue a CPU cycle. Record that there was After the end of the transfer cycle, XC is made inactive and the CPU cycle stored previously is issued. During this CPU cycle, the ACK signal is returned to the bus to terminate the CPU access of the bus. As a result, AS, CS, and READ
Becomes inactive.

FIG. 16 is a timing chart when the access from the bus side, the refresh cycle from the display controller and the transfer cycle from the sub controller overlap. AS, CS, and READ become active in order to access the buffer memory from the bus, but it is assumed that the display controller is executing the refresh mode at this time. Further, this timing chart shows the case where the sub controller is executing the transfer cycle. The refresh cycle from the display controller is detected by the sub controller at point A in the figure (VCA
(VRAS is at high level when S falls). However, at this time, since XC is active, the sub-controller remembers that a refresh cycle is necessary and executes the transfer cycle. After the completion of the fresh cycle from the display controller, the CPU cycle is executed in response to the request from the bus. The start of the CPU cycle is detected by the sub-controller at point B in the figure (VCAS and V
OE is high level). At this time, XC and RC are active. RC is a signal that becomes active during a refresh cycle or a transfer cycle, and like XC, it must be active at least one cycle earlier. XC is included in RC. Since RC is active at point (B), the sub-controller remembers that there was a CPU cycle. After the transfer cycle ends, the sub controller stores the stored refresh cycle, CPU
Cycle in sequence.

[0048]

As described in detail above, the information processing apparatus according to the present invention is connected to the buffer memory, the display device for displaying the display data stored in the buffer memory, and the CPU via the bus. And a first control means for controlling writing and reading of display data to and from the buffer memory and controlling output of display data from the buffer memory to the display device, and a display device connected to the first control means. For reading and writing the display data via at least the address, the synchronization signal, the bus transmitted from the first control means to the buffer memory in order to reduce the display data to fit the logical screen in the physical screen into the physical screen. CPU
And a second control means for processing a cycle, a refresh cycle for refreshing the buffer memory, and a transfer cycle for transferring display data in the buffer memory, and transmitting the processed data to the buffer memory. Can be executed using these means, and is also effective for application software. Further, since the reduction processing of the display data is performed on the display data of the first control means and the second control means, there is no delay in the display and the main memory is not affected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a display system of an embodiment of an information processing apparatus according to the present invention.

FIG. 2 is a block diagram corresponding to the block diagram shown in FIG. 1 in which terminal names are described in detail.

FIG. 3 is an explanatory diagram showing an example of reduction by thinning out a screen.

FIG. 4 is a timing chart showing sync signals generated by a display controller and a sub controller.

FIG. 5 shows H out of signals output from the sub controller
Dot lock signal SXCK before and after S and display data DAT
It is a timing chart figure which shows the timing with A.

FIG. 6 shows RAS, CAS, O in the CPU cycle.
It is a timing chart figure of E and an address.

FIG. 7: RAS and C in a refresh cycle
It is a timing chart figure of AS.

FIG. 8 shows RAS, CAS, OE in a transfer cycle.
FIG. 6 is a timing chart of an address and an address.

FIG. 9 is an explanatory diagram showing a signal state of each output port of the buffer memory during non-reduction and reduction in an embodiment of the information processing apparatus according to the present invention.

10 is a timing chart showing the timing for port A shown in FIG.

FIG. 11 is a detailed block diagram of a sub controller of an embodiment of the information processing apparatus according to the present invention.

12 is a block diagram showing details of the transfer cycle / address generation circuit and the synchronization signal generation circuit shown in FIG. 11. FIG.

FIG. 13 is an explanatory diagram showing a location of a transfer cycle when the screen is not reduced.

FIG. 14 is an explanatory diagram showing a position of a transfer cycle when a screen is reduced in an embodiment of the information processing apparatus according to the present invention.

FIG. 15 shows how each cycle of the buffer memory changes in timing on the bus side, the display control side, and the sub control side. Access from the bus side and transfer of the buffer memory from the sub controller It is a timing chart figure when a cycle overlaps.

FIG. 16 shows how each cycle of the buffer memory changes the timing on the bus side, the display control side, and the sub-control side. Access from the bus side and refresh cycles from the display controller and sub-cycles are shown. It is a timing chart figure when the transfer cycle from a controller overlaps.

FIG. 17 is an explanatory diagram showing a relationship between a physical screen and a logical screen according to a conventional method of reducing the screen by hardware.

FIG. 18 is an explanatory diagram showing a relationship between a physical screen and a logical screen according to a conventional method of reducing a screen by software.

[Explanation of symbols]

 10 Display Controller 11 Sub Controller 12 Buffer Memory 13 Color Palette 14 Display Device 20 Bus

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G09G 5/18 8121-5G 5/36 9177-5G H04N 1/393 4226-5C

Claims (1)

[Claims] 1. A buffer memory, a display device for displaying display data stored in the buffer memory, and a CPU connected via a bus to control writing and reading of display data in the buffer memory, First control means for controlling output of display data from the buffer memory to the display device, and display data for connecting a logical screen in the display device to a physical screen, which is connected to the first control means. In order to reduce the address, the address transmitted from the first control means to the buffer memory, the synchronization signal, the CPU cycle for reading and writing the display data via the bus, and the refreshing the buffer memory Of the refresh cycle and the transfer cycle for transferring the display data in the buffer memory to process the buffer cycle. An information processing apparatus, comprising: a second control means for transmitting to a far memory.