JPH05328389A - Y/c delay correction circuit - Google Patents

Abstract

PURPOSE:To set appropriate delay correction corresponding to the selection of the various kinds of input video signals by shifting the write reset pulses of Y and C memories corresponding to the delay between luminance signals and signals. CONSTITUTION:This Y/C delay correction circuit is constituted of three processing systems corresponding to Y, R-Y and B-Y. The respective processing systems are constituted of LPFs 10, 20 and 30, A/D converters 11, 21 and 31 and line memories 12, 22 and 32, etc., respectively and they are controlled by a timing controller 41. A system clock is generated with HSYNC as reference and the timing controller 41 forms required pulses. The write reset pulse WR1 is added to the line memory 12 for Y channel and the delayed write reset pulse WR2 is added to the line memories 22 and 32 for R-Y and B-Y channels. The pulse WR2 is shifted to the WR1 corresponding to the delay between the luminance signals and the chrominance signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a Y / C delay correction circuit,
Specifically, the present invention relates to a circuit for correcting the delay between the luminance component Y and the chroma component C in the processing of a color television video signal.

[0002]

2. Description of the Related Art In a video signal processing unit of a color television receiver, when separating a luminance component Y / chroma component C from a composite video signal, an appropriate low pass filter LPF and band filter for Y and C respectively. BPF processing is being performed. Since these filters having different bands have different group delay characteristics, a time delay (chroma delay) occurs in C with respect to Y. Conventionally, the characteristics of the filter are sacrificed so that this C delay is minimized,
Therefore, when the correction is insufficient, a method of delaying Y by an analog delay filter has been adopted.

[0003]

However, in such a method, when a large amount of delay correction is used, a plurality of filters are used. Therefore, the number of amplifiers for gain compensation is increased, the number of parts is increased and the signal deterioration is increased. Was the cause of. Further, there is a difference in delay amount between various input signals such as an internal tuner and an external video signal, and setting an appropriate delay correction amount for each of these differences results in a huge circuit configuration. Moreover, since the amount of delay varies depending on the connected device, it is virtually impossible to satisfy all the combinations by the conventional method.

In addition, especially in recent large-screen TV receivers, the Y / C delay correction is an indispensable function. Therefore, an object of the present invention is to provide a delay correction circuit that can appropriately cope with various input conditions.

[0005]

According to the present invention, a Y memory for storing a digitized luminance signal separated from an input video signal and a color signal also separated and demodulated from the input video signal and digitized. At least one to remember
C memory and a timing controller for supplying write and read clock signals, write reset pulse and read reset pulse to the Y memory and C memory, and the timing controller supplies write reset pulse for the Y memory and C memory. A Y / C delay correction circuit is configured so that a delay corresponding to the amount of signal delay between the luminance signal and the chrominance signal is provided therebetween and the read reset pulses are in phase.

The delay given to the write reset pulse can be arbitrarily set from the outside, and a delay correction amount setting means is provided to previously determine the delay correction amount corresponding to the type of the input video signal. It can also be set based on. It is possible to use a line memory for two lines as the Y and C memories, and to use write and read reset pulses having a cycle of two lines and having phases substantially opposite to each other. Further, as these memories, a line memory for aspect conversion or a field memory for double speed processing can be used. Further, according to the present invention, the delay correction processing unit in the television receiver is configured to change the delay correction amount in response to the selection of the input video signal.

[0007]

According to the above construction, the write reset pulses of the Y and C memories are shifted in correspondence with the delay between the luminance signal and the chrominance signal, so that the delay between the two signals is eliminated on the address of the memory. Therefore, if the read operation is performed based on the read reset pulse having the same phase, the delay between the two signals is corrected. Further, since the delay correction amount can be set from the outside, it is possible to set an appropriate delay correction corresponding to selection of various input video signals.

[0008]

1 is a block diagram showing a basic configuration of a signal processing section of a TV receiver which employs a Y / C delay correction circuit according to the present invention. 1 is a tuner, 2 is a Y / C separation section, and 3 is a block diagram. Is a color demodulation unit (chroma decoder), 4 is a delay correction processing unit, 5
Is an RGB decoder, 6 is a video amplifier, 7 is a CRT display, and 8 and 9 are first and second input selection switches. As input signal source, VHF, UHF, B
There are tuner outputs such as S and CATV, and video signals 1 and 2 from an external signal source. The latter has a composite signal Composite and a separate signal S (Y), respectively.
There are two types of / C).

Either the tuner 1 or the composite video signal input is selected by the first input selection switch 8 and separated into Y (luminance) and C (chromaticity) in the Y / C separation unit 2. There are various separation methods,
In any case, filters having different characteristics are usually used for Y / C, which causes a delay between Y / C. In addition, by the second input selection switch 9, this Y
Either the Y / C signal separated in the / C separation unit 2 or the S (Y / C) input from the outside is selected, and the color demodulation unit 3
In, the color difference signals RY and BY are demodulated and formed from the chromaticity signal C. A filter that causes a delay is also used in this portion.

In this way, Y, R-Y after color demodulation,
In the BY signal, different delays are introduced between them depending on the input condition. The delay correction processing unit 4
It receives a correction amount control through a microcomputer bus and gives a delay correction according to such an input condition. Here, by the delay correction process using the line memory, the delayed RY and BY are relatively advanced and matched with Y. In this process, the entire signal is delayed by 1H, but the deviation between Y / C is eliminated. The corrected signals are converted into RGB by the RGB decoder, amplified by the video amplifier 6, and then driven by the CRT display 7,
An image without deviation between Y / C is displayed.

FIG. 2 is a block diagram showing the configuration of the delay correction processing unit 4 to which the present invention is applied, which is Y, RY, B-.
It is composed of three processing systems (channel ch) for Y. Each processing system has a low-pass filter LPF.
(10, 20, 30), A / D converter (11, 21, 3)
1), line memory (12, 22, 32), D / A converter (13, 23, 33), low-pass filter LPF (14,
24, 34), which are controlled by the timing controller 41. The system clock (for example, 4f _sc = 14.3 MHz) is HSYN
The pulse is generated by 910 multiplication by the PLL 40 with reference to C, and the timing controller 41 creates the necessary pulse from the microcomputer via the system bus at the set timing.

FIG. 3 is a block diagram showing the configuration of the line memories 12, 22, and 32. From the memory cell array 50, the write address counter 51, the read address counter 52, the write port 53, and the read port 54, respectively. It is a dual port line memory configured and capable of asynchronous read / write. In this example,
910 bytes x 2 = 1820 bytes, that is, 4f _sc
It has a capacity of 2H.

When writing data, the write address counter 51 is stepwise driven in synchronization with the rising edge of the write clock CK, and the data is written to the address in the memory cell array 50 which is accessed. The write address counter 51 is reset by the write reset pulse WR, but as shown in FIG. 2, the write reset pulse WR1 is applied to the line memory 12 for the Y channel (ch-Y), and the write reset pulse WR2 delayed therefrom is applied. For RY and BY channels (ch-R-
(Y, BY) line memories 22 and 32.
For reading data, the read address counter 52 is stepwise driven in synchronization with the rising edge of the read clock CK, and the memory cell array 50 to be accessed thereby.
Is read from the address inside. The read address counter 52 is reset by the read reset pulse RR, and the line memories 12, 22, 3 of all the channels are reset.
Added to 2 at the same time.

FIG. 4 shows addresses and write / read reset pulses W in the line memories 12, 22, 32.
9A and 9B are graphs and time charts for explaining the relationship between R and RR, in which the horizontal axis indicates the number of clocks, and thus the elapsed time, and the vertical axis indicates the address. Write reset pulse WR and read reset pulse RR
Is, as shown in the time chart at the bottom of the figure,
It is generated in 1820 clocks, that is, in a period of 2H (2 lines), WR2 is delayed from WR1 by d (an integer multiple of clock period 70 ns) set from the microcomputer bus, and RR is a write / read access collision. To prevent it, it is deviated from WR1 by 1H (one line). Therefore, if the delay amount d corresponds to the delay (chroma delay) between the Y, RY, and BY signals, those signals on the n line and the n + 1 line are respectively indicated by solid lines in the graph. It is written in the line memory, and the delay between Y and RY, BY on the address of the line memory is eliminated. And when reading,
Y and R-Y, B-
The Y signal is simultaneously read from the corresponding addresses and the delay between them is corrected. The same applies to the lines after n + 2.

FIG. 5 is a schematic diagram for explaining a method of canceling the chroma delay by changing the timing of the write reset pulse WR, and is a schematic diagram showing the timing of the write / read reset pulse and the state of the internal address. For simplicity, only the Y and RY channels will be described. In the figure, 60 is a digitized Y signal, 61 is a ch-Y write address string, 62 is a ch-Y read address string, 63 is a ch-Y read output, 64 is a digitized RY signal, 65 Is c
An h-RY write address string, 66 is a ch-RY read address string, and 67 is a ch-RY read output.

In FIG. 5, d is a delay between Y and RY, that is, a delay corresponding to chroma delay, which is set by a delay correction amount control signal supplied via the microcomputer bus. Here, RY is 3CK with respect to Y
It is delayed by (70 × 3 = 210 ns), and WR2 is also delayed by 3 CK from WR1 correspondingly. That is, the reset at the time of writing is equal to the chroma delay d.
By delaying as much as possible, the write address is adjusted and the delay is offset on the address. After that, since the same RR pulse is used for both at the time of reading, it is read as digital data without deviation. In addition, the A / D converter used here,
Since the D / A converter and the low-pass filter LPF all have the same characteristics, the delay correction is collectively achieved by the above-mentioned function.

As described above, the entire signal is delayed by 1H, but the deviation between Y / C is improved. In this example,
The system clock is set to 4 f _sc , but the present invention is not limited to this, and an arbitrary value can be taken depending on the required accuracy and memory conditions. Further, here, for the sake of convenience of description, delay correction is performed between the line memories 12 and 22, but thereafter, there are elements that cause a Y / C shift, such as a filter and a delay line type aperture control circuit for adding sharpness. In some cases, it goes without saying that it is necessary to set the delay correction amount so that all the delay corrections are achieved at the input section of the RGB decoder 5.

The amount of Y / C delay of the input signal largely depends on the input signal source. For example, B in the example of FIG.
S, VHF, UHF, Composite Video 1/2, S Vid
At least 6 kinds of correction amounts are required like eo,
These have microcomputers 8 and 9 (SW1 /
The setting value is changed in synchronism with the switching in 2).

FIG. 6 is an operation flow chart for explaining the process of setting the delay correction amount in the microcomputer. First, the microcomputer determines the type of the input signal based on the state of the switch 8 (SW1) (step a), and largely changes the processing depending on whether it is the internal tuner or the external video signal source. That is, "Y
es ”, the internal tuner is BS, UHF, VHF,
It is discriminated which one of the CATV is selected (steps i, j, k), and the delay correction amount corresponding to each is set (steps l, m, n, p). For example, these distinctions can be judged by the status information held by the microcomputer itself.

If the determination at step a is "No", that is, if the video signal source is an external video signal source, the process is branched by Video 1 or 2 (step b). In each case, Composite or S (Y) is selected depending on the state of the switch 9 (SW2). /
C) is distinguished (step c or f), and the delay correction amount is set accordingly (step d or g in the case of Composite, step e or h in the case of S).

Here, in the case of the internal tuner, each delay correction amount can be set in advance, but in the case of an external video signal, it depends on the connected device, and therefore, when strict correction is required. , 8 mm, β, VHS, LD, etc., an average delay correction amount for each Composite / S can be prepared, and the user can select it when connecting the device. When the strictness is not required, only these two average values, that is, Composite / S, may be automatically set. Further, in the case of the internal tuner, it is also possible to perform correction for each broadcast channel in each broadcast band. Although these setting values are set in the timing controller 41 by the microcomputer bus, the setting method is not particularly limited.

The most effective application example of the Y / C delay correction circuit according to the present invention is a configuration incorporated in an aspect conversion section of an HDTV or a wide television. Normally, time axis compression processing using a line memory is adopted for aspect conversion, and Y / C according to the present invention is used in this portion.
If a delay correction circuit is incorporated, processing can be performed on the writing side, so that accurate correction can be realized without being affected by display modes such as ZOOM and NORMAL.

Further, in the above description, only the correction by the line memory is explained, but the field memory used in the EDTV, the field double speed processing, etc. has the same internal structure, that is, the C field for Y field. Even when a structure including a unit for advancing the write address of the memory is adopted, the present invention can be applied and the same effect can be obtained.

[0024]

According to the Y / C delay correction circuit of the present invention,
Since it is possible to correct an arbitrary delay amount within 1H, it is possible to design each filter used for Y and C by focusing only on the frequency characteristic and the pulse response characteristic without depending on the delay characteristic. The transmission characteristics are improved, and an analog delay filter, a gain correction amplifier, etc. are not required, which is effective in reducing the number of parts. In addition, since an arbitrary correction amount can be set by an external control means such as a microcomputer, it is possible to realize appropriate correction processing for all signal sources.
Therefore, various modern input functions, namely VHF, UH
F, BS, external composite video input, external S input,
The present invention is extremely effective for a large-screen TV set having an input function such as NTSC, PAL, SECAM, and HDTV.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a T employing a Y / C delay correction circuit according to the present invention.
It is a block diagram which shows the basic composition of the signal processing part of a V receiver.

FIG. 2 is a block diagram showing a configuration of a Y / C delay correction circuit according to the present invention.

FIG. 3 is a block diagram showing a configuration of a line memory.

FIG. 4 is a graph and a time chart for explaining a relationship between an address inside a line memory and a write / read reset pulse.

FIG. 5 is a diagram for explaining a method of canceling chroma delay by changing the timing of a write reset pulse.

FIG. 6 is an operation flow diagram illustrating a process of setting a delay correction amount by a microcomputer.

[Explanation of symbols]

 1 Tuner 2 Y / C Separation Section 3 Chroma Decoder 4 Delay Correction Processing Section 5 RGB Decoder 6 Video Amplifier 7 CRT Display 8, 9 Selection Switch 10, 20, 30 Low-pass Filter 11, 21, 31 A / D Converter 12, 22, 32 Line memory 13, 23, 33 D / A converter 14, 24, 33 Low-pass filter 40 PLL 41 Timing controller 50 Memory cell array 51 Write address counter 52 Read address counter 53 Write port 54 Read port

Claims (8)

[Claims] 1. A Y memory for storing a digitized luminance signal separated from an input video signal, and at least one C memory for storing a digitized color signal separated from the input video signal and demodulated. A timing controller for supplying a write / read clock signal, a write reset pulse, and a read reset pulse to the Y memory and the C memory, wherein the timing controller has the luminance between the write reset pulses supplied to the Y memory and the C memory. Gives a delay corresponding to the amount of signal delay between the signal and the color signal,
A Y / C delay correction circuit, which is in phase between read reset pulses. 2. The Y / C delay correction according to claim 1, further comprising delay correction amount setting means capable of externally setting a delay amount given to the write reset pulse in the timing controller. circuit. 3. The input video signal is selected from among tuner outputs of various broadcast radio wave reception signals in a television receiver and various external video signal inputs, and the delay correction amount setting means is the above various input video signals. The Y / C delay correction circuit according to claim 2, wherein the delay amount is set on the basis of a predetermined delay correction amount for each of the signals. 4. A Y memory stores a digitized luminance signal separated from an input video signal, and a C memory stores two color difference signals separated and demodulated from the input video signal and digitized, respectively. 2. The Y / C delay correction circuit according to claim 1, wherein two Y / C delay correction circuits are provided. 5. The Y memory and the C memory are line memories having a storage capacity of two lines, and the timing controller outputs a write reset pulse and a read reset pulse which are in a two-line cycle and are in substantially opposite phases to each other. The Y / C delay correction circuit according to claim 1, wherein the Y / C delay correction circuit supplies the Y / C delay correction circuit. 6. The Y memory according to claim 1, wherein the Y memory and the C memory are time axis compression processing line memories for aspect conversion.
/ C delay correction circuit. 7. The Y / C delay correction circuit according to claim 1, wherein the Y memory and the C memory are field memories for field double speed processing. 8. A first selection means for selecting a composite video signal input from a tuner output for selectively receiving various broadcast radio waves and various external composite video signal inputs, and a luminance signal from the composite video signal input. Y / C separation unit for separating the component and the chromaticity signal component, the output of the Y / C separation unit and various externally separated video signals S
Second selection means for selecting a separated video signal (Y / C) input from the (Y / C) input, and a color demodulation unit for demodulating a luminance signal and a color difference signal from the separated video signal (Y / C) input. A delay correction processing unit that corrects a delay between the luminance signal and the color difference signal; and a video signal processing unit that performs processing for displaying an image based on the delay corrected luminance signal and the color difference signal. The correction processing unit includes means for setting a delay correction amount based on a delay correction amount predetermined for each video signal input in accordance with the selection of the first and second selection units. Television receiver to do.