JPH05327806A - Phase judgment control method - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding a phase determination control method for determining the phase of a received signal by detecting a unique word, even if a unique word is detected in a plurality of phases, the phase that can be regarded as the most correct is determined. A unique configuration including a pattern comparison unit 4 for comparing a received signal and a unique word pattern, a mismatch bit number counting unit 5, and a tolerance comparison unit 6 for comparing the mismatch bit number and a tolerance value to determine a unique word detection phase. The word detection unit 1, the mismatch bit number comparison unit 2, and the phase determination unit 3 are provided. When the unique word detection phase is plural, the phase determination unit 3 sets the phase of the minimum mismatch bit number as the current judgment phase, If the number of bits does not match, the same phase as the previous judgment phase among the multiple phases is set as the current judgment phase, and if there is no same phase, one of the multiple phases is randomly selected. This is the determination phase.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase judgment control system for detecting the reception phase of a unique word in a reception signal to judge the phase of the reception signal. On the receiving side in a satellite communication system or the like, a modulated wave such as QPSK is received and a carrier is regenerated, and this regenerated carrier is used for demodulation. In that case, for example, four-phase phase modulation Since the reproduced carrier wave for the signal has a lead-in phase for every 90 °, it is necessary to determine the received signal phase for the reproduced carrier wave and process the demodulated signal. Therefore, a method of determining the received signal phase by unique word detection is adopted.

[0002]

2. Description of the Related Art In satellite communication systems and the like, a method is known in which a unique word is inserted at regular intervals and transmitted, and the phase of a received signal is determined by detecting the unique word. The phase determination of the received signal by such unique word detection is performed, for example, as shown in FIG.
The pattern comparison unit 71 compares the received signal S _in with the unique word pattern UW, and counts the number of unmatched bits in the comparison result of bit correspondence between the unique word _in the received signal S _in and the unique word pattern UW. Part 7
2 and the tolerance value set in advance is compared in a tolerance comparing unit 73. If the count value is less than or equal to the tolerance value, it is determined that a unique word is detected, and the unique word pattern UW is detected. The received signal phase is determined from the phase of. In this case, if the tolerance value is set to 0, only when the unique word pattern UW and the unique word _{in the} received signal S _in completely match,
It is determined that the unique word is detected, and the phase determination output corresponding to the phase of the unique word pattern UW is obtained.

For example, the phase of a received signal S _{in obtained} by synchronously detecting and demodulating a four-phase phase-modulated signal by a reproduced carrier wave is drawn into one of four phases of the reproduced carrier wave every 90 °. The reproduction carrier phase cannot be uniquely determined. To remove such phase uncertainty,
Although a method of applying operation logic on the transmitting side is known, it has a drawback that the code error rate deteriorates. Therefore, as described above, the phase of the received signal S _in is determined by detecting the unique words inserted at regular intervals, and the code conversion processing for performing the correct received code is performed based on the determination result. The method is adopted.

When the received signal S _in obtained by synchronously detecting and demodulating such a 4-phase phase-modulated signal is input, the unique word pattern UW is regarded as a pattern corresponding to the four phases of the received signal S _in. In parallel, the number of unmatched bits of each comparison result is counted in the unmatched bit number counting unit 72, and each count value and the tolerance value are compared in the tolerance comparing unit 73, and the phase is compared. Judgment output signals IQ, * QI, Q * I, * I * Q
When any one of the two becomes "1", the phase of the received signal is determined. It should be noted that I and Q indicate that the I and Q phases are orthogonal to each other, and * I and * Q indicate the I and Q phases by 180 °.
Indicates that the phase is inverted.

When the phase determination output signal IQ is output from the tolerance comparing section 73, the reception signals S _in of the I phase and the Q phase are added and processed as they are by a reception processing circuit (not shown). .. This case corresponds to the case where the reproduced carrier wave is pulled into the correct phase. When the phase determination output signal * 1 * Q is output, it corresponds to the case where the reproduced carrier wave is pulled in 180 ° out of the correct phase,
The reception signals S _in of the I-phase and the Q-phase are respectively inverted and added to the reception processing circuit. Also, the phase judgment output signal Q * I
Is output, the I-phase signal of the received signal S _in is inverted into the Q-phase and the Q-phase signal is inverted by 180 ° to be replaced with the I-phase. When the phase determination output signal * QI is output, the I-phase signal of the reception signal S _in is inverted by 180 ° and the Q-phase signal is replaced with the I-phase signal.

[0006]

When the number of bits of the unique word is reduced and the tolerance value is set to less than 1/4 of the number of bits of the unique word, even if the configuration of the conventional example described above is used, The phase judgment output of is obtained.
However, as in satellite communication systems, S / N of wireless circuits
If the value is low, the bit number of the unique word is set to, for example, 32 bits or more, and the tolerance value is also less than 1/2 of the bit number of the unique word and 1 /
For example, it may be set to 4 or more, for example, 10. That is, it may be set so that the unique word can be detected even with some code error. In this way, if the tolerance value is set to ¼ or more of the number of bits of the unique word, it will be determined as a unique word even if the number of mismatch bits is large.
The probability that a plurality of phase determination outputs can be obtained simultaneously from the tolerance comparison unit 73 increases. When a plurality of phase determination outputs are obtained in this way, the code conversion processing becomes confused, and there is a drawback that normal reception processing cannot be performed. It is an object of the present invention to determine one phase that can be considered to be the most correct, even if the received signal phase is determined by unique word detection for a plurality of phases.

[0007]

A phase determination control system of the present invention will be described with reference to FIG. 1. A pattern comparison unit 4 for comparing a received signal with a unique word pattern and a comparison by the pattern comparison unit 4 will be described. It comprises a non-matching bit number counting section 5 for counting the number of non-matching bits, and a tolerance comparing section 6 for comparing the number of non-matching bits by the non-matching bit number counting section 5 with a tolerance value to judge whether or not the word is a unique word. The phase determination unit 1 includes a unique word detection unit 1, a mismatch bit number comparison unit 2 that compares the mismatched bit numbers corresponding to each phase of the received signal to determine the phase corresponding to the smallest value, and a phase determination unit 3. The unit 3 corresponds to the detected phase information of the unique word from the unique word detection unit 1 and the value with the smallest number of mismatched bits from the mismatched bit number comparison unit 2. The group and phase information, and the previous determination phase information, is to determine the current optimal phase.

Further, when the unique word detection phase information from the unique word detection unit 1 indicates a plurality of phases, the phase determination unit 3 determines the phase corresponding to the value with the smallest number of mismatched bits by the mismatched bit number comparison unit 2. If the phase corresponding to the value with the smallest number of mismatch bits is multiple phases, the same phase as the previous determination phase among the multiple phases is set as the current determination phase, and If the previous determination phase is not included therein, any one of the plurality of phases is randomly selected as the current determination phase.

Further, when the unique word detection phase information from the unique word detection unit 1 indicates the same phase as the previous determination phase, the phase determination unit 3 sets this phase as the current determination phase and determines the previous determination phase. If it is not the same as, the phase corresponding to the value with the smallest number of unmatched bits by the unmatched bit number comparison unit 2 is set as the current judgment phase, and if the phase corresponding to the value with the smallest number of unmatched bits is a plurality of phases,
Any one of the plurality of phases is randomly selected as the current judgment phase.

[0010]

The mismatch bit number comparing unit 2 compares the mismatch bit numbers with respect to the unique word pattern corresponding to each phase in the mismatch bit number counting unit 5, and determines the phase having the smallest mismatch bit number. The phase determination unit 3 includes the detected phase information of the unique word from the unique word detection unit 1, the phase information corresponding to the smallest value of the number of mismatch bits from the mismatch bit number comparison unit 2, and the previous determination phase information. Even if the input phase information of the unique word indicates multiple phases after inputting, it determines one optimal phase based on the phase information corresponding to the value with the smallest number of mismatch bits and the previous phase determination information. Is.

Further, when the unique word detection phase information from the unique word detection unit 1 indicates a plurality of phases, the phase determination unit 3 determines that the phase corresponding to the value with the smallest number of mismatched bits by the mismatched bit number comparison unit 2 is detected. It is determined that it is the closest to the detection phase of the unique word, and the current judgment phase is set. In that case, the phase corresponding to the value having the smallest number of mismatch bits may be a plurality of phases. In that case, any of the plurality of phases may be selected, but it is determined that the previous determination phase is correct, and the same phase as the previous determination phase is set as the current determination phase. If the previous determination phase is not included in the plurality of phases, there is no determination criterion, and therefore one of the plurality of phases is randomly selected as the current determination phase.

Further, the phase judging unit 3 judges whether or not the detected phase information of the unique word from the unique word detecting unit 1 is the same as the previous judging phase. The judgment phase of. If they are not the same, it is judged whether or not the phase corresponding to the smallest value of the number of mismatch bits in the mismatch bit number comparing unit 2 is a plurality of phases. In the case of a plurality of phases, one of the plurality of phases is randomly selected as the current judgment phase.

[0013]

2 is a block diagram of a unique word detecting section and a mismatch bit number comparing section according to an embodiment of the present invention.
1 is a unique word detection unit, 12 is a mismatch bit number comparison unit, 14 is a pattern comparison unit, 15 is a mismatch bit number counting unit, 16 is a tolerance comparison unit, 17, 18, 25 are comparison circuits, 19-22, 26- 29 is an AND circuit (&), 2
3, 24, 30a, 30b are OR circuits (OR).

[0014] unique word detector 11, like the prior art, the received signal S _in and the unique word pattern UW is input, received at the pattern comparator 14 signal S _in and the unique word pattern UW and each phase It is compared correspondingly, the number of unmatched bits is counted in the unmatched bit number counting unit 15, the number of unmatched bits is compared with the tolerance value in the tolerance comparison unit 16, and is unique when the number of unmatched bits is less than or equal to the tolerance value. It is determined that the word has been detected, and the tolerance comparison output signals D _{A to} D _D corresponding to the unique word detection phase are output.

When the received signal S _in is, for example, a demodulated signal of four-phase phase modulation, the received signal S _{in with} respect to the unique word pattern UW corresponding to each phase in the mismatch bit number counting section 15
The number of unmatched bits B _{A to} B _D is compared with the tolerance value in the tolerance comparing unit 16 to detect a unique word. Normally, IQ, * I * Q, Q * are detected.
I, * QI four tolerance comparison output signals D _{A to} D _D
Any one of the above is output. As mentioned above,
When the unique word length is 32 bits or more and the tolerance value is 10 or more, a plurality of tolerance comparison output signals may be output simultaneously.

The unmatched bit number comparison unit 12 receives the unmatched bit numbers B _{A to BD} corresponding to each phase from the unmatched bit number counting unit 15 of the unique word detection unit 11, and receives the unmatched bit number B corresponding to the IQ phase. _a and * I * Q phase corresponding mismatch bits B _B are compared by comparator circuit 17, Q *
The number of mismatch bits B _C corresponding to the I phase and the number of mismatch bits B _D corresponding to the * QI phase are compared by the comparison circuit 18.
The comparator circuits 17 and 18 add "1" to the AND circuits 19 and 21 when the input signals A and B are A <B, and conversely add "1" to the AND circuits 20 and 22 when A> B.

Therefore, the number of unmatched bits B corresponding to the IQ phase
_A and * I * Q phase corresponding one small OR it is from the AND circuits 19 and 20 of the value circuits with mismatched bits B _B 23
Is input to the comparison circuit 25 via the AND circuit, and the smaller of the unmatched bit number B _C corresponding to the Q * I phase and the unmatched bit number B _D corresponding to the * QI phase is the smaller value from the AND circuits 21 and 22. It is input to the comparison circuit 25 via 24. The comparison circuit 25 outputs the comparison result as "1" for the relationship of A <B, A = B, A> B. Therefore, the AND circuits 26 to 29 output the minimum mismatch bit number signals S _{A to} S. _D is output. Further, A = B shows a case where there are a plurality of phases where the number of mismatch bits is minimum, and the output signal S ₀ in that case is a plurality of minimum mismatch bit number signals.

FIG. 3 is a block diagram of a phase determination circuit according to an embodiment of the present invention, in which 31 and 32 are AND circuits (&) and 3
3 to 38 are three-state buffers, 39 to 42 are OR circuits (OR), 43 to 45, 48a to 48d are inverters (IV), 46 is a random signal generating circuit (PNG),
Reference numeral 47 is a latch circuit, which corresponds to the phase determination unit 3 in FIG.

The phase determination circuit includes tolerance comparison output signals D _{A to} D _D from the unique word detection section 11 and a minimum mismatch bit number signal S from the mismatch bit number comparison section 12.
_{A to} S _D , a plurality of minimum mismatch bit number signals S _0, and the previous phase determination output signals L _{A to} L _D are input. And
Phase determination output signals IQ, * I * Q, Q * I, * QI are output from any of the three-state buffers 33 to 38.

The three-state buffers 33 to 38 are
The output impedance is set to high impedance when the control signal of "1" is input, the output is enabled when the control signal of "0" is input, and the input signal is output as it is. Further, the phase determination output signals IQ, * I * Q, Q * I, * QI are latched in the latch circuit 47 and added to the AND circuit 32 as the previous phase determination output signals L _{A to} L _D.

When only one of the tolerance comparison output signals D _{A to} D _D from the tolerance comparison unit 16 is output, the mismatch bit numbers B _{A to} B _D from the mismatch bit number counting unit 15 are compared. The minimum mismatch bit number is only one. For example, when the tolerance comparison output signal D _B becomes “1”, the minimum mismatch bit number signal S _B from the AND circuit 27 of the mismatch bit number comparison unit 12 becomes “1”.

At that time, since the plurality of minimum mismatch bit number signals S ₀ corresponding to A = B of the comparison circuit 25 become “0”,
Since the output of the three-state buffer 33 is enabled and the control signal of "1" is applied to the three-state buffer 34 via the inverter 43 and the OR circuit 40, the output of the three-state buffer 34 becomes high impedance. Become. Also, the three-state buffer 3 is connected via the inverter 43 and the OR circuits 39 and 42.
Since the control signal of "1" is added to 5 to 38, the outputs of the three-state buffers 35 to 38 become high impedance. Therefore, the phase determination output signals * I * Q are output via the three-state buffer 33,
And it is latched by the latch circuit 47.

Further, for example, when the tolerance comparison output signals D _B and D _C are simultaneously output from the tolerance comparison unit 16, when the comparison circuit 25 of the non-coincidence bit number comparison unit 12 compares the non-coincidence bit numbers B _B and B _C. , B _B <B _C , the AND circuit 27 outputs the minimum mismatch bit number signal S _B. In the case of the input signal S _in which the 4-phase phase modulation signal is demodulated, the tolerance ≧ (UW
Since it is not 1/2 of the length, a combination in which a plurality of phase determinations are performed at the same time is Q * I or * Q with respect to IQ.
It becomes Q * I or * QI for I and * 1 * Q. That is,
The combinations of the tolerance comparison output signals simultaneously output from the tolerance comparison unit 16 are D _A and D _C or D _D , D _B and D _C or D _D , and the combination of D _A and D _B and D _C and D _D. The combination with does not occur.

The AND circuit 31 of the phase determination circuit is D _A
Since the logical product of B _A , D _B · B _B , D _C · B _C , and D _D · B _D is obtained, the minimum unmatched bit number signal S from the unmatched bit number comparison unit 12 is obtained. _{According to B} , the tolerance comparison output signal D _B is output as the phase determination output signal * I * Q via the three-state buffer 33. Therefore, even if a plurality of tolerance comparison output signals that occur when the number of unique word bits is increased and the tolerance value is increased, one of the tolerance comparison output signals with the smallest number of mismatched bits is selected. Will be done.

Further, a plurality of tolerance comparison output signals D _{A to} D _D simultaneously become "1", and the number of unmatched bits B _{A to} B _D.
If there are a plurality of minimum values among the above, the plurality of minimum mismatch bit number signals S ₀ from the comparison circuit 25 become “1”. As a result, the output of the three-state buffer 33 becomes high impedance. Further, the AND circuit 31 outputs a plurality of "1".

The AND circuit 32 ANDs the previous phase determination output signals L _{A to} L _D from the latch circuit 47 and the output signal of the AND circuit 31 to obtain the current determination phase and the previous determination phase. Determines whether there are the same. If they are the same, the output of the AND circuit 32 corresponding to the same phase becomes "1", and the output signal of the OR circuit 41 also becomes "1". Thereby, the OR circuits 39 and 42
A control signal of "1" is applied to the three-state buffers 35 to 38 via the, and their outputs become high impedance. Moreover, since the control signal of “0” is applied from the OR circuit 40 to the three-state buffer 34, the output of the three-state buffer 34 is enabled, and the previous phase determination output signal from the AND circuit 32 is passed through the three-state buffer 34. Phase determination output signal IQ, * I
One of * Q, Q * I, and * QI is output and latched by the latch circuit 47.

If the current determination phase does not include the same as the previous determination phase, the output signals of the AND circuits 32 are all "0" and the output signals of the OR circuit 41 are also "0". From the three-state buffer 34 via the inverter 44 and the OR circuit 40.
In addition, the output of the three-state buffer 34 becomes high impedance. Further, the OR circuit 42 outputs to the OR circuit 39 an output signal of "0", a signal obtained by inverting the output signal of the AND circuit 31 by the inverters 48a to 48d, a random signal generation circuit 46 or a random signal via the inverter 45. Signal and are input.

For example, if the previous phase determination output signal is L
_If the tolerance comparison output signal is D _A , D _C and the minimum mismatch bit number signal is S _A, S _C in D, the current determination phase does not include the same one as the previous determination phase. The outputs of the buffers 33 and 34 have high impedance. The output signals of the inverters 48a and 48c become "0", and the output signals of the inverters 48b and 48d become "1". If the output signal of the random signal generation circuit 46 is "1", the inverters 45, 4
Only the output signal of the OR circuit 42 to which the output signal of 8c and the output signal of the OR circuit 39 are added becomes "0", and only the output of the three-state buffer 37 is enabled,
Tolerance comparison output signal D _C is phase judgment output signal Q *
It is output as I and is latched by the latch circuit 47. In this case, one of the phase determination output signals Q * I and IQ is randomly selected and output.

FIG. 4 is a flow chart of an embodiment of the present invention, which summarizes the operation in the case of the phase determination circuit shown in FIG. 3, in which the unique word detection (UW detection) is performed in the unique word detection section 11. ) Is performed (a), and it is determined whether or not there are a plurality of phases having the smallest number of mismatch bits in the mismatch bit number comparison unit 12 (b). When the tolerance comparison output signals D _{A to} D _D are single, the minimum mismatch bit number signals S _{A to} S _D are also single, so the AND circuit 3
A phase determination output signal corresponding to the detection phase of the unique word by the unique word detection unit 11 is obtained via 1 and the three-state buffer 33. Further, when there are a plurality of tolerance comparison output signals D _{A to} D _D and if the minimum mismatch bit number signals S _{A to} S _D are single, the most mismatch bit number is passed through the AND circuit 31 and the three-state buffer 33. The smaller phase is output as the determination phase (f).

When there are a plurality of phases with the smallest number of mismatch bits, it is judged whether or not the same phase as the previous judgment phase is included (c), and the same phase as the last judgment phase is included. If so, the same phase as the previous time is output as the current judgment phase via the AND circuit 32 and the three-state buffer 34 with reference to the previous phase judgment (d). If the same phase is not included, there is no determination criterion, so the three-state buffers 35 to 38 are selected according to the random signal from the random signal generation circuit 46, and output as the determination phase via the selected three-state buffer. (E). Therefore, even in a worst case condition in which the detection phase of the unique word is plural and the minimum number of mismatch bits is also plural, it is possible to make one judgment phase without any confusion _in the reception processing of the reception signal S _in. It can be processed.

FIG. 5 is a block diagram of a phase determination circuit according to another embodiment of the present invention, in which 51 and 52 are AND circuits (&),
53 to 58 are three-state buffers, 59 to 62 are OR circuits (OR), 63 to 65 and 68a to 68d are inverters (IV), and 66 is a random signal generating circuit (PN).
G) and 67 are latch circuits, which are the phase determination unit 3 of FIG.
Corresponding to.

Also in this embodiment, the tolerance comparison output signal D from the unique word detecting section 11 in FIG.
_{A to DD} , the minimum unmatched bit number signals S _{A to} S _D from the unmatched bit number comparison unit 12, the plurality of minimum unmatched bit number signals S _0, and the previous phase determination output signals L _{A to} L _D are input. Then, the AND circuit 51 determines whether or not the present determination phase and the previous determination phase are the same by the logical product of the tolerance comparison output signals D _{A to} D _D and the previous phase determination output signals L _{A to} L _D. To judge.

Single or multiple tolerance comparison output signals D
_{When A to} D _D are output from the tolerance comparison unit 16 and include the same phase as the previous determination phase, the output signal of the AND circuit 51 corresponding to the previous determination phase is "1". The output signal of the OR circuit 61 becomes "1", which is inverted by the inverter 63, the control signal of "0" is added to the three-state buffer 53, and its output is enabled. Therefore, the output signal of "1" of the AND circuit 51 is the phase determination output signals IQ, * I * Q, Q * I, * Q.
It becomes I and is latched by the latch circuit 67. Also, since the output signals of the OR circuits 59 and 60 are "1", the outputs of the three-state buffers 54 to 58 have high impedance.

If the current judgment phase does not include the same as the previous judgment phase, the output signals of the AND circuit 51 are all "0", so that the three-state buffer 5 is used.
The output of 3 becomes high impedance. At that time, if only the single minimum mismatch bit number signal is “1” and the plurality of minimum mismatch bit number signals S ₀ is “0”, the output of the three-state buffer 54 is enabled. And
Since the output signal of the AND circuit 52 becomes "1" corresponding to the minimum mismatch bit number signal, the three-state buffer 5
4 becomes a phase determination output signal via 4 and latch circuit 6
Latched to 7. That is, even when different from the previous determination phase and a plurality of tolerance comparison output signals are obtained,
One phase having the smallest number of mismatch bits can be set as the determination phase.

When the plurality of minimum mismatch bit number signals S _{A to} S _D become a plurality of "1", the plurality of minimum mismatch bit number signals S ₀ become a "1".
Output becomes high impedance. At that time, the output signal of "1" of the AND circuit 52 becomes plural, but as described above, the combinations that may have plural judgment phases are Q * I and * QI, * I * Q with respect to IQ. Against Q * I and * Q
I, and for the tolerance comparison output signal, D _C and D _D relative to D _A, also the D _C and D _D relative to D _B.
That is, the combination of D _A and D _B and the combination of D _C and D _D do not occur.

Therefore, the random signal from the random signal generating circuit 66 is applied to the OR circuit 62 together with the outputs of the inverters 68a and 68b, and the random signal inverted by the inverter 65 is applied to the OR circuit 62 together with the outputs of the inverters 68c and 68d. As a result, only one output signal of the OR circuit 62 becomes "0", and the outputs of the three-state buffers 55 to 58 to which the control signal of "0" is added are enabled. For example, the minimum mismatch bit number signals S _A and S _C are “1”, and the tolerance comparison output signals D _A and D
_When the output signal of the random signal generation circuit 66 is "1" when _C is "1", only the control signal of the three-state buffer 57 becomes "0", and the output of the three-state buffer 57 is enabled. Then, the phase determination output signal Q * I corresponding to the tolerance comparison output signal D _C becomes “1”.

FIG. 6 is a flow chart of another embodiment of the present invention, which summarizes the operation in the case of the phase determination circuit shown in FIG. 5, in which the unique word detection (UW) in the unique word detection section 11 is performed. (Detection) is performed (1), and the AND circuit 51 determines whether the phase is the same as the previous determination phase (2). If the phases are the same, the output of the three-state buffer 53 is enabled, and the same judgment phase as the previous one is output as the current judgment phase (4).

If the phase determined by detecting the unique word by the unique word detecting unit 11 is different from the previously determined phase, the mismatching bit number comparing unit 12 determines whether there are a plurality of phases having the smallest number of mismatching bits. It is determined (3). When a single minimum mismatch bit number signal is obtained, the phase corresponding to the minimum mismatch bit number signal is output as the current determination phase (6). Further, when a plurality of minimum mismatch bit number signals are obtained, one phase is randomly selected from a plurality of phases corresponding to the minimum mismatch bit number signal, and is output as the current judgment phase (5).

In each of the above-described embodiments, the comparison circuit, the gate circuit and the like constitute the mismatch bit number comparison unit and the phase judgment circuit. The judgment and selection functions are controlled by a program such as a microprocessor. It is also possible to realize. Also, although the case of a received signal obtained by demodulating a 4-phase phase modulated signal is shown, it is also possible to make a phase determination of a received signal obtained by demodulating a multi-phase phase modulated signal such as 8-phase or 16-phase or a quadrature amplitude modulated signal (QAM). Applicable.

[0040]

As described above, according to the present invention, the unique word detection phase information from the unique word detection unit 1 and the phase information corresponding to the smallest value of the number of mismatch bits from the mismatch bit number comparison unit 2 are obtained. The optimum phase is determined in the phase determination unit 3 based on the previous determination phase information. Even when a unique word is detected in a plurality of phases, the phase determination unit 3 determines one determination phase. Can be output. In this case, the previous determination phase or the phase having the smallest number of mismatch bits is selected as the determination phase, and the irrelevant phase is not selected. Therefore, there is an advantage that the reception process can be stabilized.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a unique word detection unit and a mismatch bit number comparison unit according to an embodiment of the present invention.

FIG. 3 is a block diagram of a phase determination circuit according to an embodiment of the present invention.

FIG. 4 is a flowchart of an embodiment of the present invention.

FIG. 5 is a block diagram of a phase determination circuit according to another embodiment of the present invention.

FIG. 6 is a flowchart of another embodiment of the present invention.

FIG. 7 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 1 Unique word detection unit 2 Mismatch bit number comparison unit 3 Phase determination unit 4 Pattern comparison unit 5 Mismatch bit number counting unit 6 Tolerance comparison unit

Claims (3)

[Claims] 1. A pattern comparing section (4) for comparing a received signal with a unique word pattern in a phase determination control system for detecting a received phase of a unique word in a received signal and determining a phase of the received signal. ) And a mismatch bit number counting section (5) for counting the number of comparison mismatch bits by the pattern comparing section (4)
And a tolerance comparison unit (6) that compares the number of unmatched bits by the unmatched bit number counting unit (5) with a tolerance value to determine whether the word is a unique word, and a unique word detection unit (1). A phase discriminating unit comprising a discrepancy bit number comparing unit (2) for discriminating a phase corresponding to the smallest value by comparing the discrepancy bit numbers corresponding to respective phases of the received signal; According to (3), the detected phase information of the unique word from the unique word detection unit (1), the phase information corresponding to the smallest number of mismatched bits from the mismatched bit number comparison unit (2), and the previous A phase determination control method characterized by determining the optimum phase this time based on the determination phase information. 2. The phase determining section (3), when the unique word detection phase information from the unique word detecting section (1) indicates a plurality of phases, the mismatch bit comparing section (2) compares the mismatch bits. When the phase corresponding to the smallest number of values is the current judgment phase, and the phase corresponding to the value with the smallest number of mismatch bits is a plurality of phases, the same phase as the previous judgment phase among the plurality of phases is set. If the same phase as the previous determination phase among the plurality of phases is not included as the determination phase of this time, any one of the plurality of phases is randomly selected and set as the determination phase of this time. The phase determination control method according to claim 1, wherein 3. The phase determination unit (3) determines the phase when the unique word detection phase information from the unique word detection unit (1) indicates the same phase as the previous determination phase. If the phase is not the same as the previous determination phase, the phase corresponding to the value having the smallest number of mismatch bits by the mismatch bit number comparison unit (2) is set as the current determination phase, and the value having the smallest number of mismatch bits is set. 2. The phase determination control method according to claim 1, wherein when the corresponding phases are a plurality of phases, any one of the plurality of phases is randomly selected and set as the current determination phase.