JPH05326619A - Semiconductor chip - Google Patents
Semiconductor chipInfo
- Publication number
- JPH05326619A JPH05326619A JP4130743A JP13074392A JPH05326619A JP H05326619 A JPH05326619 A JP H05326619A JP 4130743 A JP4130743 A JP 4130743A JP 13074392 A JP13074392 A JP 13074392A JP H05326619 A JPH05326619 A JP H05326619A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- light
- parallelism
- mounting surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 81
- 239000000758 substrate Substances 0.000 claims description 50
- 230000005484 gravity Effects 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims 1
- 239000000523 sample Substances 0.000 description 21
- 230000003287 optical effect Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 238000005259 measurement Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Length Measuring Devices By Optical Means (AREA)
- Wire Bonding (AREA)
- Led Device Packages (AREA)
Abstract
(57)【要約】
【目的】 本発明は、基板に実装する際の歩留まりが高
い半導体チップを提供することを目的とする。
【構成】 光反射用の平坦領域（１３）に照射された光
は、正しい角度で反射する。この反射光の反射角度か
ら、基板（１４）に対する半導体チップ（１０）の相対
的な傾きが測定できる。
(57) [Summary] [Object] An object of the present invention is to provide a semiconductor chip having a high yield when mounted on a substrate. [Structure] Light applied to a light reflecting flat area (13) is reflected at a correct angle. From the reflection angle of this reflected light, the relative inclination of the semiconductor chip (10) with respect to the substrate (14) can be measured.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、Ｓｉ−ＬＳＩ、ＧａＡ
ｓ−ＬＳＩ、および液晶ディスプレイ（ＬＣＤ）等に用
いられる半導体チップに関する。The present invention relates to Si-LSI and GaA.
The present invention relates to semiconductor chips used for s-LSIs, liquid crystal displays (LCDs), and the like.
【０００２】[0002]
【従来の技術】フリップチップの実装方法は、半導体チ
ップに設けられた全てのバンプを基板上のパッドに接続
して行う。このため、半導体チップと基板の平行度を保
つ技術が極めて重要である。このように半導体チップと
基板とを平行に保つための従来の技術としては、例えば
光学プローブ装置を用いる方法がある。この方法は、半
導体チップおよび基板にプローブ光を照射し、その反射
光から半導体チップと基板との相対的な傾きを測定し、
これらの測定値から両者の平行度を調整するものであ
る。2. Description of the Related Art A flip chip mounting method is performed by connecting all bumps provided on a semiconductor chip to pads on a substrate. For this reason, the technique of maintaining the parallelism between the semiconductor chip and the substrate is extremely important. As a conventional technique for keeping the semiconductor chip and the substrate parallel to each other in this way, there is a method using an optical probe device, for example. This method irradiates the semiconductor chip and the substrate with probe light, measures the relative tilt between the semiconductor chip and the substrate from the reflected light,
The parallelism between the two is adjusted from these measured values.
【０００３】[0003]
【発明が解決しようとする課題】ところで、近年の半導
体チップは高度に集積化されているので、半導体チップ
表面には微細な凹凸が数多く存在する。このため、光学
プローブ装置を用いて半導体チップにプローブ光を照射
しても、半導体チップ表面の微細な凹凸で光が錯乱する
ために、基板に対する半導体チップの相対的な傾きを測
定することは困難であった。By the way, since recent semiconductor chips are highly integrated, there are many fine irregularities on the surface of the semiconductor chip. Therefore, even if the semiconductor chip is irradiated with the probe light using the optical probe device, it is difficult to measure the relative inclination of the semiconductor chip with respect to the substrate because the light is confused by the fine irregularities on the surface of the semiconductor chip. Met.
【０００４】本発明は、表面に微細な凹凸を有していて
も、照射されたプローブ光が錯乱することのない半導体
チップを提供することを目的とする。An object of the present invention is to provide a semiconductor chip in which the probe light emitted does not cause confusion even if it has fine irregularities on its surface.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体チップは、実装面の中央に、あるい
は実装面の重心に対して点対称な位置に、または実装面
の周縁に光反射用の平坦領域を有する。In order to solve the above-mentioned problems, the semiconductor chip of the present invention has a semiconductor chip at the center of the mounting surface, at a position symmetrical with respect to the center of gravity of the mounting surface, or at the periphery of the mounting surface. It has a flat area for light reflection.
【０００６】[0006]
【作用】本発明の半導体チップによれば、実装面の中
央、あるいは実装面の重心に対して点対称な位置、また
は実装面の周縁に有する光反射用の平坦領域に照射され
た光は、正しい角度で反射する。この反射光の反射角度
から、基板に対する半導体チップの相対的な傾きが測定
できる。According to the semiconductor chip of the present invention, the light radiated to the center of the mounting surface, the point-symmetrical position with respect to the center of gravity of the mounting surface, or the flat area for light reflection at the periphery of the mounting surface is Reflect at the correct angle. From the reflection angle of this reflected light, the relative inclination of the semiconductor chip with respect to the substrate can be measured.
【０００７】[0007]
【実施例】以下、本発明の一実施例について、添付図面
を参照しつつ説明する。図１は本実施例の半導体チップ
の外観を示す斜視図である。半導体チップ１０は、実装
面１０ａに金属配線１１が形成されており、この金属配
線１１の複数箇所にバンプ１２が設けられている。ま
た、半導体チップ１０の実装面１０ａの中央には、１０
〜２００μｍ2 の面積の平坦領域１３が設けられてい
る。この平坦領域１３は半導体チップ１０と基板１４と
の平行度を測定する際に利用される。具体的には、図２
に示すように、半導体チップ１０と基板１４との平行度
の測定は光学プローブ１５を用いて行うが、光学プロー
ブ１５からのプローブ光を反射する反射面として平坦領
域１３が用いられているのである。平坦領域１３は、例
えば金属層の上に絶縁膜を積層させて形成する。絶縁膜
には、ＳｉＮ（ｎ＝１．９程度（ｎ：屈折率））、Ｓｉ
ＯＮ（ｎ＝１．８５程度）または、ＳｉＯ2 （ｎ＝１．
４程度）などを用いる。この場合、プローブ光の波長を
λとすると、λ／２×ｍ＝ｎ×ｄ（ｍ：整数、ｄ：膜
厚）の関係を満たす膜厚で絶縁膜を積層させるとよい。
この関係を満たす膜厚であれば、平坦領域１３の金属層
で反射するプローブ光の反射率は極大となり、絶縁膜で
のプローブ光の光量減少を防止できるからである。また
平坦領域１３は半導体チップ１０の実装面１０ａの中央
に設けられているので、実装面１０ａの周辺に歪みや反
りがあっても、半導体チップ１０と基板１４との平行度
を正確に調整することができる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a perspective view showing the appearance of the semiconductor chip of this embodiment. The semiconductor chip 10 has metal wirings 11 formed on the mounting surface 10a, and bumps 12 are provided at a plurality of locations on the metal wirings 11. Further, in the center of the mounting surface 10a of the semiconductor chip 10, 10
A flat region 13 having an area of 200 μm 2 is provided. The flat region 13 is used when measuring the parallelism between the semiconductor chip 10 and the substrate 14. Specifically, FIG.
As shown in FIG. 3, the parallelism between the semiconductor chip 10 and the substrate 14 is measured by using the optical probe 15, but the flat region 13 is used as a reflecting surface for reflecting the probe light from the optical probe 15. .. The flat region 13 is formed by stacking an insulating film on a metal layer, for example. For the insulating film, SiN (n = 1.9 (n: refractive index)), Si
ON (n = 1.85) or SiO 2 (n = 1.
4) is used. In this case, when the wavelength of the probe light is λ, it is preferable to stack the insulating films with a film thickness that satisfies the relationship of λ / 2 × m = n × d (m: integer, d: film thickness).
This is because if the film thickness satisfies this relationship, the reflectance of the probe light reflected by the metal layer in the flat region 13 becomes maximum, and a decrease in the amount of probe light in the insulating film can be prevented. Further, since the flat region 13 is provided at the center of the mounting surface 10a of the semiconductor chip 10, even if there is distortion or warpage around the mounting surface 10a, the parallelism between the semiconductor chip 10 and the substrate 14 can be accurately adjusted. be able to.
【０００８】本実施例の応用例を図３、図４に示す。図
３（ａ）は、半導体チップ１０の実装面１０ａの重心１
０ｂに点対称な１対の平坦領域２１、２２を設けた例で
ある。平坦領域２１、２２を用いて２か所で半導体チッ
プ１０と基板１４との平行度を測定すれば、実装面１０
ａ全体に歪みや反りがあっても、正確に平行度を調整す
ることができる。図３（ｂ）は、半導体チップ１０の実
装面１０ａの重心１０ｂに点対称な２対の平坦領域２
３、２４および平坦領域２５、２６を設けた例である。
この応用例は、４か所の平坦領域２３〜２６で半導体チ
ップ１０と基板１４との平行度を測定するので、上述し
た例に比べて、いっそう正確に平行度を調整することが
できる。さらにこの例では、対となる平坦領域を結ぶ直
線がほぼ直交するように、平坦領域２３〜２６がそれぞ
れ配置されているので、実装面１０ａ全体に歪みや反り
があっても正確に平行度を調整することができる。An application example of this embodiment is shown in FIGS. FIG. 3A shows the center of gravity 1 of the mounting surface 10 a of the semiconductor chip 10.
This is an example in which a pair of point-symmetrical flat regions 21 and 22 are provided in 0b. If the parallelism between the semiconductor chip 10 and the substrate 14 is measured at two locations using the flat regions 21 and 22, the mounting surface 10
Even if there is distortion or warpage in the whole a, the parallelism can be accurately adjusted. FIG. 3B shows two pairs of flat regions 2 that are point-symmetric with respect to the center of gravity 10 b of the mounting surface 10 a of the semiconductor chip 10.
This is an example in which 3, 24 and flat regions 25, 26 are provided.
In this application example, since the parallelism between the semiconductor chip 10 and the substrate 14 is measured at the four flat regions 23 to 26, the parallelism can be adjusted more accurately as compared with the above-mentioned example. Further, in this example, since the flat regions 23 to 26 are arranged so that the straight lines connecting the pair of flat regions are substantially orthogonal to each other, the parallelism can be accurately obtained even if the entire mounting surface 10a is distorted or warped. Can be adjusted.
【０００９】図４（ａ）は、半導体チップ１０の実装面
１０ａの中央に十字型の平坦領域３１を設けた例であ
る。平坦領域３１の先端部３１ａ〜３１ｄの中から複数
の測定点を選択して、半導体チップ１０と基板１４との
平行度を測定することによって、実装面１０ａ全体に歪
みや反りがあっても正確に平行度を調整することができ
る。図４（ｂ）は、半導体チップ１０の実装面１０ａの
周縁部に帯状の平坦領域３２を設けた例である。平坦領
域３２上の複数の測定点を選択して、半導体チップ１０
と基板１４との平行度測定することによって、正確に平
行度を調整することができる。図４（ｃ）の例は、図４
（ｂ）の例の変形であり、半導体チップ１０の実装面１
０ａの周縁部に複数の平坦領域３３〜３６を設けた例で
ある。これらの平坦領域３３〜３６を用いても、図４
（ｂ）の例と同様、正確に平行度を調整することができ
る。FIG. 4A shows an example in which a cross-shaped flat region 31 is provided in the center of the mounting surface 10a of the semiconductor chip 10. By selecting a plurality of measurement points from the tip portions 31a to 31d of the flat area 31 and measuring the parallelism between the semiconductor chip 10 and the substrate 14, even if the entire mounting surface 10a is distorted or warped, it is accurate. The parallelism can be adjusted. FIG. 4B is an example in which a strip-shaped flat region 32 is provided on the peripheral portion of the mounting surface 10 a of the semiconductor chip 10. The semiconductor chip 10 is selected by selecting a plurality of measurement points on the flat region 32.
By measuring the parallelism between the substrate 14 and the substrate 14, the parallelism can be accurately adjusted. An example of FIG. 4C is shown in FIG.
It is a modification of the example of (b), and is the mounting surface 1 of the semiconductor chip 10.
This is an example in which a plurality of flat regions 33 to 36 are provided in the peripheral portion of 0a. Using these flat regions 33-36, FIG.
Similar to the example of (b), the parallelism can be adjusted accurately.
【００１０】次に、本実施例の半導体チップ１０を基板
１４に実装する実装装置について、図５を用いて説明す
る。実装装置は、半導体チップ１０の実装面１０ａを下
にして上から真空吸着により装着した半導体チップ装着
部５１と、基板１４を真空吸着により上面に装着した基
板装着部５２とを備え、半導体チップ装着部５１は枠体
５３の上部に、基板装着部５２は枠体５３の下部に固定
されている。半導体チップ装着部５１と基板装着部５２
の間には、半導体チップ１０と基板１４の平行度を測定
する平行度測定装置５４とが備えられている。Next, a mounting apparatus for mounting the semiconductor chip 10 of this embodiment on the substrate 14 will be described with reference to FIG. The mounting apparatus includes a semiconductor chip mounting portion 51 mounted by vacuum suction from above with the mounting surface 10a of the semiconductor chip 10 downward, and a substrate mounting portion 52 mounting the substrate 14 on the upper surface by vacuum suction. The portion 51 is fixed to the upper portion of the frame body 53, and the board mounting portion 52 is fixed to the lower portion of the frame body 53. Semiconductor chip mounting portion 51 and substrate mounting portion 52
A parallelism measuring device 54 for measuring the parallelism between the semiconductor chip 10 and the substrate 14 is provided between them.
【００１１】平行度測定装置５４は、半導体チップ１０
および基盤１４にプローブ光を照射する光学プローブ５
４ａと、半導体チップ１０および基盤１４で反射したプ
ローブ光の反射角度を測定する測定部５４ｂと、光学プ
ローブ５４ａおよび測定部５４ｂを支持する支持台５４
ｃとを備えている。The parallelism measuring device 54 includes the semiconductor chip 10.
And optical probe 5 for irradiating the substrate 14 with probe light
4a, a measuring section 54b for measuring the reflection angle of the probe light reflected by the semiconductor chip 10 and the substrate 14, and a support 54 for supporting the optical probe 54a and the measuring section 54b.
and c.
【００１２】半導体チップ装着部５１は、半導体チップ
１０を吸着する吸着ブロック５１１と、この吸着ブロッ
ク５１１が固定され揺動自在の揺動ステージ５１２と、
この揺動ステージ５１２が固定され水平な２次元方向に
可動な水平移動ステージ５１３とを有している。この水
平移動ステージ５１３の側面部の直交する２つの面に
は、半導体チップ１０の上面と平行な方向の調整を行う
アクチュエータ５１ａ、５１ｂが設けられ、揺動ステー
ジ５１２の側面部の直交する２つの面には、半導体チッ
プ１０の傾きの調整を行うアクチュエータ５１ｃ、５１
ｄが設けられている。The semiconductor chip mounting portion 51 has a suction block 511 for sucking the semiconductor chip 10, and a swing stage 512 to which the suction block 511 is fixed and which can swing.
The swing stage 512 is fixed and has a horizontal movement stage 513 which is movable in a horizontal two-dimensional direction. Actuators 51a and 51b for adjusting in a direction parallel to the upper surface of the semiconductor chip 10 are provided on two orthogonal surfaces of the side surface of the horizontal movement stage 513, and two orthogonal side surfaces of the swing stage 512 are provided. Actuators 51c, 51 for adjusting the inclination of the semiconductor chip 10 are provided on the surface.
d is provided.
【００１３】基板装着部５２は基板１４を吸着する吸着
ブロック５２１と、この吸着ブロック５２１が固定され
てこれを上下動するボンディング機構部５２２と、この
ボンディング機構部５２２が固定され揺動自在の揺動ス
テージ５２３と、この揺動ステージ５２３が固定され水
平な２次元方向に可動な水平移動ステージ５２４とを有
している。水平移動ステージ５２４の側面部の直交する
２つの面には、基板１４の上面と平行な方向の調整を行
うアクチュエータ５２ａ、５２ｂが設けられ、揺動ステ
ージ５２３の側面部の直交する２つの面には、基板１４
の傾きの調整を行うアクチュエータ５２ｃ、５２ｄが設
けられている。The board mounting portion 52 has a suction block 521 for sucking the board 14, a bonding mechanism 522 for fixing the suction block 521 and moving the block up and down, and a swinging swing for fixing the bonding mechanism 522. It has a moving stage 523 and a horizontal moving stage 524 to which the swinging stage 523 is fixed and is movable in a horizontal two-dimensional direction. Actuators 52a and 52b for adjusting in a direction parallel to the upper surface of the substrate 14 are provided on the two orthogonal surfaces of the side surface of the horizontal moving stage 524, and the two orthogonal surfaces of the lateral surface of the swing stage 523 are provided. Is the substrate 14
Actuators 52c and 52d for adjusting the inclination of are provided.
【００１４】さらに、実装装置には、半導体チップ１０
と基板１４の平行度を調整するコントローラ５５が備え
られている。コントローラ５５は光学プローブ５４ａか
らの測定結果のデータを入力し、このデータに基づい
て、アクチュエータ５１ａ〜５１ｄおよびアクチュエー
タ５２ａ〜５２ｄに対し必要な指令を出力している。Further, the mounting device includes a semiconductor chip 10.
And a controller 55 for adjusting the parallelism of the substrate 14. The controller 55 inputs the data of the measurement result from the optical probe 54a, and outputs necessary commands to the actuators 51a to 51d and the actuators 52a to 52d based on this data.
【００１５】次に、図６を用いて、光学プローブ５４ａ
の測定原理を説明する。同図より、光源から平行に入射
した入射光Ａ1 、Ｂ1 はライトガイド６１を通過して反
射鏡６２、６３で反射し、半導体チップ１０の下面と基
板１４の上面に照射する。そして、これらの照射光
Ａ2 、Ｂ2 が半導体チップ１０の下面と基板１４の上面
で反射して、反射鏡６２、６３を介して出射する。これ
らの出射光Ａ3 、Ｂ3 の出射位置を、例えば半導体位置
検出器を用いて測定することによって、半導体チップ１
０の下面と基板１４の上面の角度のずれが判定できる。Next, referring to FIG. 6, the optical probe 54a
The measurement principle of is explained. As shown in the figure, incident lights A 1 and B 1 incident in parallel from the light source pass through the light guide 61, are reflected by the reflecting mirrors 62 and 63, and are applied to the lower surface of the semiconductor chip 10 and the upper surface of the substrate 14. Then, these irradiation lights A 2 and B 2 are reflected by the lower surface of the semiconductor chip 10 and the upper surface of the substrate 14 and emitted through the reflecting mirrors 62 and 63. By measuring the emission positions of these emission lights A 3 and B 3 using, for example, a semiconductor position detector, the semiconductor chip 1
A deviation of the angle between the lower surface of 0 and the upper surface of the substrate 14 can be determined.
【００１６】次に、実装装置を用いた実装方法につい
て、図５に戻って説明する。まず半導体チップ１０を半
導体チップ装着部５１の吸着ブロック５１１に吸引装着
させ、基板１４を基板装着部５２の吸着ブロック５２１
に吸引装着させる。そして、平行度測定装置５４を用い
て、半導体チップ１０と基板１４との平行度を測定す
る。このとき、半導体チップ１０へのプローブ光は、半
導体チップ１０の平坦領域１３に照射されるので、プロ
ーブ光が平坦領域１３で反射した反射光を測定すれば、
半導体チップ１０と基板１４との傾きが正確に検出でき
る。Next, a mounting method using the mounting apparatus will be described by returning to FIG. First, the semiconductor chip 10 is attached to the suction block 511 of the semiconductor chip mounting portion 51 by suction, and the substrate 14 is attached to the suction block 521 of the substrate mounting portion 52.
Suction it on. Then, the parallelism measuring device 54 is used to measure the parallelism between the semiconductor chip 10 and the substrate 14. At this time, since the probe light to the semiconductor chip 10 is applied to the flat area 13 of the semiconductor chip 10, if the reflected light of the probe light reflected by the flat area 13 is measured,
The inclination between the semiconductor chip 10 and the substrate 14 can be accurately detected.
【００１７】平行度測定装置５４での測定結果は、コン
トローラ５５に与えられ、半導体チップ１０と基板１４
との平行度が検討される。この検討の結果、半導体チッ
プ１０の角度調整が必要であるとコントローラ５５が判
定した場合には、半導体チップ装着部５１のアクチュエ
ータ５１ｃ、５１ｄに指令が送られ、必要な角度調整が
行われる。また、基板１４の角度調整が必要であるとコ
ントローラ５５が判定した場合には、基板装着部５２の
アクチュエータ５２ｃ、５２ｄに指令が送られ、必要な
角度調整が行われる。The measurement result of the parallelism measuring device 54 is given to the controller 55, and the semiconductor chip 10 and the substrate 14 are
The parallelism with is examined. As a result of this examination, when the controller 55 determines that the angle adjustment of the semiconductor chip 10 is necessary, a command is sent to the actuators 51c and 51d of the semiconductor chip mounting portion 51, and the necessary angle adjustment is performed. Further, when the controller 55 determines that the angle adjustment of the board 14 is necessary, a command is sent to the actuators 52c and 52d of the board mounting portion 52, and the necessary angle adjustment is performed.
【００１８】以上の角度調整処理が終了した後に、平行
度測定装置５４を後退させる。そして、基板装着部５２
を持ち上げて、基板１４上に半導体チップ１０を実装す
る。前工程の角度調整処理で半導体チップ１０と基板１
４との平行度が十分に保たれているので、半導体チップ
１０上の全てのバンプ１２を基板１４上のパッドに接続
することができる。したがって、高い実装歩留りを確保
することができる。After the above angle adjustment processing is completed, the parallelism measuring device 54 is retracted. Then, the board mounting portion 52
And the semiconductor chip 10 is mounted on the substrate 14. The semiconductor chip 10 and the substrate 1 are processed by the angle adjustment process in the previous process.
Since the parallelism with 4 is sufficiently maintained, all the bumps 12 on the semiconductor chip 10 can be connected to the pads on the substrate 14. Therefore, a high mounting yield can be secured.
【００１９】[0019]
【発明の効果】本発明の半導体チップであれば、光反射
用の平坦領域に照射された光は、正しい角度で反射す
る。この反射光の反射角度を測定すれば、基板に対する
半導体チップの相対的な傾きが測定できる。そして、こ
の測定値を用いれば、基板と半導体チップとの平行度を
正確に調整することができる。With the semiconductor chip of the present invention, the light applied to the flat area for light reflection is reflected at the correct angle. By measuring the reflection angle of this reflected light, the relative inclination of the semiconductor chip with respect to the substrate can be measured. Then, by using this measured value, the parallelism between the substrate and the semiconductor chip can be accurately adjusted.
【図１】本実施例の半導体チップの外観を示す斜視図で
ある。FIG. 1 is a perspective view showing the appearance of a semiconductor chip of this embodiment.
【図２】半導体チップと基板の平行度を測定する状態を
示す斜視図である。FIG. 2 is a perspective view showing a state of measuring parallelism between a semiconductor chip and a substrate.
【図３】応用例の半導体チップの外観を示す斜視図であ
る。FIG. 3 is a perspective view showing an appearance of a semiconductor chip of an application example.
【図４】応用例の半導体チップの外観を示す斜視図であ
る。FIG. 4 is a perspective view showing an appearance of a semiconductor chip of an application example.
【図５】実装装置の構成を示す平面図である。FIG. 5 is a plan view showing a configuration of a mounting apparatus.
【図６】光学プローブの測定原理を示す斜視図である。FIG. 6 is a perspective view showing the measurement principle of the optical probe.
１０…半導体チップ、１１…金属配線、１２…バンプ、
１３…平坦領域、１４…基板、１５…光学プローブ。10 ... Semiconductor chip, 11 ... Metal wiring, 12 ... Bump,
13 ... Flat area, 14 ... Substrate, 15 ... Optical probe.
Claims (7)
を測定する測定手段を用いて基板との平行度を調整した
後にこの基板に実装する半導体チップにおいて、 実装面の中央に光反射用の平坦領域を有することを特徴
とする半導体チップ。1. A semiconductor chip to be mounted on a substrate after adjusting the parallelism with the substrate by using a measuring means for measuring the inclination of an object to be measured from the reflection angle of the irradiated light, for light reflection at the center of the mounting surface. A semiconductor chip having a flat region of.
を測定する測定手段を用いて基板との平行度を調整した
後にこの基板に実装する半導体チップにおいて、 実装面の重心に対して点対称な少なくとも１対の光反射
用の平坦領域を実装面に有することを特徴とする半導体
チップ。2. A semiconductor chip mounted on a substrate after adjusting the parallelism with the substrate by using a measuring means for measuring the inclination of the object to be measured from the reflection angle of the radiated light, in a point relative to the center of gravity of the mounting surface. A semiconductor chip having at least one pair of symmetrical flat regions for light reflection on a mounting surface.
を測定する測定手段を用いて基板との平行度を調整した
後にこの基板に実装する半導体チップにおいて、 実装面の重心に対して点対称な２対の光反射用の平坦領
域を実装面に有し、対応する平坦領域の中心間を結ぶ２
本の直線がほぼ直交することを特徴とする半導体チッ
プ。3. A semiconductor chip mounted on a substrate after adjusting the parallelism with the substrate by using a measuring means for measuring the inclination of the object to be measured from the reflection angle of the irradiated light, and a point relative to the center of gravity of the mounting surface. It has two symmetrical flat areas for light reflection on the mounting surface and connects the centers of the corresponding flat areas to each other.
A semiconductor chip characterized in that the straight lines of a book are substantially orthogonal.
を測定する測定手段を用いて基板との平行度を調整した
後にこの基板に実装する半導体チップにおいて、 実装面の中央に十字型の光反射用の平坦領域を有するこ
とを特徴とする半導体チップ。4. A semiconductor chip mounted on a substrate after adjusting the parallelism with the substrate by using a measuring means for measuring the inclination of the object to be measured from the reflection angle of the irradiated light, and forming a cross shape at the center of the mounting surface. A semiconductor chip having a flat region for light reflection.
を測定する測定手段を用いて基板との平行度を調整した
後にこの基板に実装する半導体チップにおいて、 実装面の周縁に帯状の光反射用の平坦領域を有すること
を特徴とする半導体チップ。5. A semiconductor chip to be mounted on a substrate after adjusting the parallelism with the substrate by using a measuring means for measuring the inclination of the object to be measured from the reflection angle of the radiated light, and strip-shaped light on the periphery of the mounting surface. A semiconductor chip having a flat area for reflection.
して形成したものであることを特徴とする請求項１から
請求項５のいずれかに記載の半導体チップ。6. The semiconductor chip according to claim 1, wherein the flat region is formed by laminating an insulating film on a metal layer.
とすると（λ／２）×ｍ＝ｎ×ｄ（ｍは整数、ｎは前記
絶縁膜の屈折率）の関係を有することを特徴とする請求
項６記載の半導体チップ。7. The film thickness d of the insulating film has a wavelength of incident light of λ
7. The semiconductor chip according to claim 6, wherein the relationship of (λ / 2) × m = n × d (m is an integer, n is a refractive index of the insulating film) is satisfied.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4130743A JPH05326619A (en) | 1992-05-22 | 1992-05-22 | Semiconductor chip |
| CA002096551A CA2096551A1 (en) | 1992-05-22 | 1993-05-19 | Semiconductor device |
| AU38674/93A AU659002B2 (en) | 1992-05-22 | 1993-05-20 | Semiconductor device |
| TW082104030A TW214018B (en) | 1992-05-22 | 1993-05-21 | Semiconductor device |
| US08/064,658 US5536974A (en) | 1992-05-22 | 1993-05-21 | Semiconductor device with light reflecting substrate area |
| KR1019930008727A KR940006231A (en) | 1992-05-22 | 1993-05-21 | Semiconductor device |
| EP93108270A EP0570971A1 (en) | 1992-05-22 | 1993-05-21 | Flip-clip-bonding alignment structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4130743A JPH05326619A (en) | 1992-05-22 | 1992-05-22 | Semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05326619A true JPH05326619A (en) | 1993-12-10 |
Family
ID=15041574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4130743A Pending JPH05326619A (en) | 1992-05-22 | 1992-05-22 | Semiconductor chip |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH05326619A (en) |
| KR (1) | KR940006231A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019160933A (en) * | 2018-03-09 | 2019-09-19 | 日本電気株式会社 | Adjustment device, adjustment method, and adjustment program |
-
1992
- 1992-05-22 JP JP4130743A patent/JPH05326619A/en active Pending
-
1993
- 1993-05-21 KR KR1019930008727A patent/KR940006231A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019160933A (en) * | 2018-03-09 | 2019-09-19 | 日本電気株式会社 | Adjustment device, adjustment method, and adjustment program |
Also Published As
| Publication number | Publication date |
|---|---|
| KR940006231A (en) | 1994-03-23 |
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