JPH05324500A - Test facilitating circuit for microcomputer - Google Patents

Abstract

PURPOSE:To guarantee high quality by detecting a fault even when there is any hidden fault at one part of an internal bus in the case of a test at the time of the massive production of one-chip microcomputers. CONSTITUTION:This circuit is provided with a first bus switch 16 to control the opening/closing of a passage between a first node 13a for external data input fetch on an internal bus 13 of the one-chip microcomputer and a CPU core part 11, second bus switch 17 to control the opening/closing of a passage between a second node 13b for read data take-out on the internal bus and a ROM part 12, and control circuit 20 for test to selectively control the respective bus switches to the ON state at the time of a normal operation mode and to selectively control them to the OFF state at the time of a test mode, and the passage between the first node and the first bus switch and the passage between the second node and the second bus switch are respectively overlapped at one part 13c at least.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test facilitating circuit for a microcomputer, and more particularly to a test circuit mounted on, for example, a one-chip microcomputer (one-chip microcomputer).

[0002]

2. Description of the Related Art Generally, in order to reduce the cost of a semiconductor integrated circuit (IC), a test facilitation design method is often adopted and a test circuit is mounted on an IC chip. Figure 4 shows a conventional 1-chip with a test circuit.
1 schematically shows the block configuration of a microcomputer.

Reference numeral 41 denotes a CPU (central processing unit) core section, 4
2 is a ROM section, 43 is an internal bus, 44 is a data input terminal (external terminal), 45 is a data output terminal (external terminal), 4
6 is a test mode input terminal (external terminal), and 47 is a bus switch.

In the one-chip microcomputer, in the normal operation mode, the ROM section 42 is executed by executing a certain instruction.
Data is read, and this read data is output to the data output terminal 45 by executing another instruction. Execution of these instructions is controlled by the CPU core unit 41, and each instruction requires an execution cycle of several steps.
On the other hand, in the test mode, when the test mode setting signal input to the test mode input terminal 46 is activated, the internal bus 43 is divided into two parts (the part connected to the ROM part 42 and the CPU core by the bus switch 47). Electrically connected to the portion 41).

As described above, in the state where the internal bus 43 is divided into two parts in the test mode, the read data from the ROM section 42 is directly output to the data output terminal 45 in one instruction execution cycle to monitor. Alternatively, or by directly inputting data from the data input terminal 44, the test of the CPU core unit 41 can be facilitated, so that the test time can be shortened.

In mass production of the one-chip microcomputer, all tests are performed in the test mode in order to reduce the test cost. At this time, if there is some hidden defect in the portion 43a from the external data input fetch node to the bus switch 47 and the portion 43b from the read data fetch node to the bus switch 47 on the internal bus 43, If a defect cannot be detected, a defective product (or a product containing a defective product) may be shipped as a result.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and when there is some hidden defect on a part of the internal bus when performing a test in the test mode. However, it is an object of the present invention to provide a microcomputer test facilitation circuit capable of detecting this defect, reducing the test cost during mass production, and ensuring high quality.

[0008]

A test facilitation circuit for a microcomputer according to the present invention includes at least two circuit blocks, an internal bus connecting the two circuit blocks to each other, and an internal bus on the internal bus. It is connected to an external data input fetch node and is connected to a data input terminal for supplying externally input data to the internal bus and a read data fetch node on the internal bus to output the read data on the internal bus to the outside. And a first bus switch circuit for controlling opening / closing of a transmission path between the external data input capturing node on the internal bus and one of the two circuit blocks, Transmission path between the read data fetch node on the internal bus and the other circuit block of the two circuit blocks A second bus switch circuit for controlling opening / closing, a test mode input terminal to which a test mode setting signal is externally input in the test mode, and the first switch circuit and the second switch circuit are turned on in the normal operation mode. And a test control circuit for selectively controlling the first bus switch circuit and the second bus switch circuit to be in an off state based on the test mode setting signal in the test mode. At least a part of each of the transmission path between the upper external data input capturing node and the first bus switch circuit and the transmission path between the read data capturing node and the second bus switch circuit overlap. It is characterized by doing.

[0009]

At least a part of the transmission path between the external data input capturing node and the first switch circuit on the internal bus and the transmission path between the second switching circuit and the read data capturing node overlap each other. Since the first switch circuit and the second switch circuit are selectively controlled to be in the OFF state in the test mode, external data input or read data passes through the overlapping transmission path. Like

With this, in the test performed in the test mode, the untested portion on the internal bus can be eliminated, and some portion on the internal bus (the above-mentioned overlapping transmission path portion) can be removed. Even if there is a hidden defect, this defect can be detected. Therefore,
When all the mass production tests are performed in the test mode, it is possible to reduce the test cost and guarantee high quality.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 schematically shows a block configuration of a one-chip microcomputer according to one embodiment of the present invention.

This one-chip microcomputer has at least two circuit blocks (for example, C
The PU core unit 11 and the ROM unit 12), the internal bus 13 that connects the two circuit blocks to each other, and the external data input capture node 13a on the internal bus 13 are connected to each other to receive data input from the outside. A data input terminal 14 for supplying to the internal bus 13, and the internal bus 13
It is connected to the read data fetch node 13b above,
And a data output terminal 15 for outputting read data to the outside.

Further, the external data input fetch node 13a on the internal bus 13 and one of the two circuit blocks (in this example, the CPU core unit 1).
1) A first bus switch circuit 16 that controls the opening and closing of a transmission path between the first and second circuit blocks, the other circuit block (ROM section 12 in this example) of the two circuit blocks, and reading on the internal bus 13. A second bus switch circuit 17 for controlling opening / closing of a transmission path to / from the data fetch node 13b
And an input buffer circuit 18 inserted in the transmission path between the data input terminal 14 and the external data input fetch node 13a on the internal bus 13.

Further, in the test mode, a test mode input terminal 1 to which a test mode setting signal is externally input.
9. In the normal operation mode, the first bus switch circuit 16 and the second bus switch circuit 17 are each turned on and the input buffer circuit 18 is controlled in the non-operation state. The first bus switch circuit 16 based on the setting signal
And a test control circuit 2 for selectively controlling the second bus switch circuit 17 in an off state and controlling the input buffer circuit 18 in an operating state or a non-operating state.
0 is provided.

The test control circuit 20 is, in this example,
A ternary level detection circuit 21 for detecting a ternary level signal input to the test mode input terminal, and the first bus switch circuit 16 and the second bus based on the detection output of the ternary level detection circuit 21. The logic circuit 22 controls the switch circuit 17.

The transmission path between the external data input fetch node 13a on the internal bus 13 and the first bus switch circuit 16 and the read data fetch node 13b and the second bus switch circuit 17 are connected. At least a part of each of the transmission paths between them overlaps, and this overlapping part is indicated by 13c.

FIG. 2 shows an example of a concrete circuit of the one-chip microcomputer shown in FIG. 1. However, in order to simplify the display, one bit of bus data (parallel data of a plurality of bits) is used. The portion corresponding to is representatively shown.

The first bus switch circuit 16 is a PMOS
The transistor P1 and the NMOS transistor N1 are connected in parallel, and each is composed of a CMOS transfer gate in which a complementary control signal is applied to each gate. Similarly, the second bus switch circuit 17 also includes a CMOS transfer gate in which a PMOS transistor P2 and an NMOS transistor N2 are connected in parallel, and complementary control signals are applied to their respective gates.

When the three-level detection circuit 21 detects a normal level ("H" level or "L" level) input signal, it outputs a level corresponding to the input signal as the first detection signal LS. , And outputs the inactive level “L” as the second detection signal HS. On the other hand, when an input signal having a potential higher than the normal level (high potential input signal) is detected, the active level “H” is set as the second detection signal HS.
Is output. At this time, the level of the first detection signal LS has no effective meaning.

The logic circuit 22 is a ternary level detection circuit 21.
A first inverter circuit 23 that inverts a second detection signal HS output from the first inverter circuit 23, an output signal of the inverter circuit 23, and a first output from the ternary level detection circuit 21.
The detection signal LS is composed of a two-input first NAND gate 24 which is one input, and a second inverter circuit 25 which inverts the output signal of the NAND gate 24. Then, the input signal and output signal of the first inverter circuit 23 are correspondingly supplied to the gates of both transistors of the second bus switch circuit 17, and the input signal and output signal of the second inverter circuit 25 are supplied. Is supplied to the gates of both transistors of the first bus switch circuit 16 correspondingly.

The input buffer circuit 18 includes a PMOS transistor P3 and an NMOS transistor N3 which are connected in series between a two-input second NAND gate 26 and a NOR gate 27, and a power supply potential (VCC) node and a ground potential (VSS) node. And a third inverter circuit 29. The second NAND gate 26 receives the external data input and the second detection signal HS of the ternary level detection circuit 21. Third above
The inverter circuit 29 of the three-level level detection circuit 21
The second detection signal HS of is inverted, and the inverted signal and the external data input are input to the NOR gate 27.
The outputs of the second NAND gate 26 and NOR gate 27 are correspondingly input to the gates of both transistors of the switch circuit 19, and the drain interconnection nodes of these transistors are external data input capture nodes on the internal bus 13. It is connected to 13a. FIG. 3 is a circuit state explanatory view showing an operation example of the one-chip microcomputer of FIG. Next, an operation example of the one-chip microcomputer shown in FIGS. 1 and 2 will be described with reference to FIG.

When a high potential input signal is applied to the test mode input terminal 19, the second detection signal HS becomes active level "H", and the output of the first inverter circuit 23 becomes "L" level, first output. The output of the NAND gate 24 is “H”
Level, the output of the second inverter circuit 25 becomes "L" level. As a result, the first bus switch circuit 16 is turned on, the second bus switch circuit 17 is turned off, and the CPU core unit 11 is tested.

At this time, the third inverter circuit 29
Is at the "L" level, the external data input is transmitted to the external data input fetching node 13a on the internal bus 13 via the second NAND gate 26, the NOR gate 27 and the switch circuit 28, and is interfered with by the ROM section 12. Without inputting to the CPU core unit 11.

Contrary to the above, the test mode input terminal 19
When a normal level input signal is applied to the second detection signal HS, the second detection signal HS becomes inactive level "L", and the first detection signal L
S is determined according to the level of the input signal.

At this time, when the first detection signal LS is at "H" level, the output of the first NAND gate 24 is "L".
Level, the output of the second inverter circuit 25 becomes "H" level, and the first bus switch circuit 16 is turned off. Further, since the output of the first inverter circuit 23 is at "H" level, the second bus switch circuit 17 is turned on and the ROM section 12 is tested.

At this time, the output of the second NAND gate 26 is at "H" level and the third inverter circuit 29
Output is "H" level, and output of NOR gate 27 is "L"
This is the level, and the switch circuit 28 is turned off. As a result, the read data from the ROM section 12 becomes CP
The data is output to the data output terminal 15 via the internal bus 13 without being interfered with by the U core unit 11 and the input buffer circuit 18.

On the other hand, when the second detection signal HS is at the inactive level "L" and the first detection signal LS is at the "L" level, the first bus switch circuit 16
The second bus switch circuit 17 is turned on, the switch circuit 28 is turned off, and the CPU core unit 11 and the ROM unit 12 are normally connected by the internal bus 13. Therefore, the normal operation mode is set.

In this normal operation mode, the data in the ROM section 12 is read by the execution of a certain instruction, and the read data is output by the data output terminal 1 by the execution of another instruction.
5 is output. Execution of these instructions is controlled by the CPU core unit 11.

That is, according to the one-chip microcomputer of the above embodiment, in the test mode, when the input signal of the test mode input terminal 19 is set to the predetermined level, the first bus switch circuit 16 and the second bus switch circuit are set. Circuit 1
7 is selectively controlled to the off state. As a result, the internal bus 13 is electrically separated into two parts (a part connected to the CPU core part 11 and a part connected to the ROM part 12), and the CPU core part 11 or the ROM part 1
It becomes the mode which tests 2.

In the mode of testing the CPU core section 11, it becomes possible to facilitate the test of the CPU core section 11 by directly inputting the data from the data input terminal 14, and to test the ROM section 12. In the mode, it becomes possible to output the read data from the ROM section 12 directly to the data output terminal 15 and monitor it in one step instruction execution cycle.

In such two test modes, the transmission path between the external data input fetch node 13a on the internal bus 13 and the first bus switch circuit 16 and the second bus switch circuit 17 and the read data fetch node 13b. At least a part 13c of each of the transmission paths between and overlaps with each other, and external data input or read data passes through the overlapping transmission paths 13c.

Therefore, in the test performed in the test mode, the untested portion on the internal bus can be eliminated, and some portion on the internal bus 13 (the above-mentioned overlapping transmission path portion 13c) can be removed. It is possible to detect this defect even if there is a defect.

[0033]

As described above, according to the present invention, when a test is performed in the test mode, the portion from the external data input fetch node on the internal bus to the first bus switch and the read data fetch node from the second node to the second bus switch are read. Even if there is some hidden defect up to the bus switch, it is possible to detect this defect. Therefore, when all the tests during mass production are performed in the test mode, it is possible to realize a microcomputer that can reduce the test cost during mass production and guarantee high quality.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a one-chip microcomputer according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a portion corresponding to one bit of bus data in the one-chip microcomputer shown in FIG.

3 is a circuit state explanatory view showing an operation example of the one-chip microcomputer of FIG.

FIG. 4 is a block diagram schematically showing a conventional one-chip microcomputer.

[Explanation of symbols]

11 ... CPU core section, 12 ... ROM section, 13 ... Internal bus, 13a ... External data input fetch node on internal bus, 13b ... Read data fetch node on internal bus, 13c ... Part of internal bus, 14 ... Data Input terminal,
15 ... Data output terminal, 16 ... First bus switch circuit, 17 ... Second bus switch circuit, 18 ... Input buffer circuit, 19 ... Test mode input terminal, 20 ... Test control circuit, 21 ... Tri-level detection Circuit, 22 ... Logic circuit.

Claims (3)

[Claims] 1. At least two circuit blocks formed on an integrated circuit chip, an internal bus connecting the two circuit blocks to each other, and an external data input fetch node on the internal bus. A data input terminal for supplying externally input data to the internal bus, and a data output terminal connected to the read data extraction node on the internal bus for outputting the read data on the internal bus to the outside, A first bus switch circuit for controlling opening / closing of a transmission path between an external data input fetching node on the internal bus and one circuit block of the two circuit blocks; and reading data fetching on the internal bus. A second bus switch circuit for controlling opening / closing of a transmission path between the node and the other circuit block of the two circuit blocks. And a test mode input terminal to which a test mode setting signal is externally input in the test mode, and the first bus switch circuit and the second bus switch circuit are turned on in the normal operation mode, respectively. A test control circuit for selectively turning off the first bus switch circuit and the second bus switch circuit based on a test mode setting signal, the external data input capturing node on the internal bus And at least a part of a transmission path between the read data fetch node and the second bus switch circuit are overlapped with each other. Microcomputer testability circuit. 2. The microcomputer test facilitation circuit according to claim 1, further comprising a transmission path inserted between the data input terminal and an external data input fetch node on the internal bus, and operating in a normal operation mode. A test facilitation circuit for a microcomputer, comprising: an input buffer circuit controlled by the test control circuit so as to enter a state and enter an operating state or a non-operating state in a test mode. 3. The microcomputer test facilitation circuit according to claim 1, wherein the test control circuit includes a ternary level detection circuit that detects a ternary level signal input to the test mode input terminal. , Based on the detection output of the three-value level detection circuit,
And a logic circuit for controlling the second bus switch circuit, and a test facilitation circuit for a microcomputer.