JPH05323921A - Image processor, display device and electronic equipment - Google Patents

Abstract

PURPOSE:To excellently perform an error diffusing process by selecting image data after the error diffusing process based on the characteristic information of the image data. CONSTITUTION:When the display data are read out of a video memory 18 to a ferrodielectric liquid crystal device(FLCD) 35, the value of an image bit 19 indicating whether or not an image is an image in the same address with this video memory is ANDed with the value of an image processing enabling register. When the kind of the display data indicates an image and image processing is performed, display 8-bit data from the video memory 18 pass through a plalette A27 to become specified 16-bit data, which are processed into 4-bit data matching the FLCD35 by mean density processing 31. When the kind of the display data does not indicate the image or when the image processing is not performed, the display 8-bit data from the video memory 18 become the specific 16-bit data by passing through the palette A27 and are further processed by a palette B30 into the 4-bit data matched with the FLCD35.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device, a display device and an image processing device.

[0002]

2. Description of the Related Art Conventionally, when an area of image data such as an image and an area of character data such as a character are simultaneously displayed on the same screen, only this area for performing halftone processing of the image area is dithered. There is a method of image processing.

[0003]

However, the above example has the following problems.

When halftone processing by error diffusion processing is performed on the character area, for example, image processing such as average density storage processing is performed, these processing also affect the image data of pixels around the target pixel to be processed. This has the disadvantage that the outline of the character becomes unclear because of the influence. An example of this is shown in FIG. Here, since the image processing is performed on the entire screen, the image area 56 is appropriately processed, but the outline of the character area 55 becomes unclear. Therefore, the quality of the image is degraded.

In view of the above points, the present invention has an object to provide an image processing device, an electronic device and a display device capable of improving the quality of an image.

[0006]

In order to achieve the above-mentioned object, an image processing apparatus of the present invention comprises a storage means for storing display image data, a means for performing halftone processing on the display image data, and Processing means for performing diffusion processing, generating means for generating information indicating characteristics of the display image data,
Selection means for selecting the output of the processing means based on the characteristic information generated by the generation means.

Further, in order to achieve the above-mentioned object, the electronic apparatus of the present invention generates a display image data, a storage unit for storing the display image data, and a halftone process for the display image data. Means for performing error diffusion processing, generating means for generating information indicating characteristics of the display image data, and selecting output of the processing means based on characteristic information generated by the generating means And a selection unit for performing the selection.

In order to achieve the above-mentioned object, the display device of the present invention is a storage means for storing display image data and a means for performing halftone processing on the display image data, and performs error diffusion processing. Processing means, generating means for generating information indicating the characteristics of the display image data, selecting means for selecting the output of the processing means based on the characteristic information generated by the generating means, selected by the selecting means It has a display means for displaying according to the output.

[0009]

According to the above construction, for example, the error diffusion process can be applied only to a predetermined image area.

[0010]

1 is a block diagram of an information processing system using an FLC (ferroelectric liquid crystal) display device having a display control device according to an embodiment of the present invention as a display device for displaying various characters and image information. ..

Reference numeral 11 is a CPU that executes control of the entire information processing system, 12 is a main memory that stores a program executed by the CPU 11 and is used as a work area for this execution, and 13 is a memory when the information processing system is powered on. RO that stores initial processing programs and fonts
M and 14 are keyboard controllers for inputting various characters, 105 is a keyboard connected to the keyboard controller 14, 110 is a mouse as a pointing device, 15 is a mouse controller for controlling the mouse 110, and 16 is an address with the CPU 11.・ System bus consisting of data / control bus, 101 is C
An arithmetic processor that processes the arithmetic of the PU 11 at higher speed,
Reference numeral 102 denotes a DMA controller (hereinafter abbreviated as “DMAC”) that transfers data between the main memory 12 and various devices that make up the system without going through the CPU 11, and 103 denotes an interrupt signal from the various devices that make up the system. An interrupt controller for processing, 104 is a real-time clock for notifying the current time when the battery is backed up, 10
Reference numerals 7 and 109 denote a hard disk device and a floppy disk device as external storage devices, respectively, and 106, a hard disk drive (hereinafter abbreviated as HDD) controller for controlling the hard disk device 107.
A floppy disk drive 08 controls the floppy disk device 109 (hereinafter abbreviated as FDD)
Controller, 111 is RS which is a kind of serial communication
RS232C interface capable of communication according to the 232C standard, 113 is a printer interface for signal connection between the printer and this system, and 35 is a ferroelectric liquid crystal device (hereinafter abbreviated as FLCD) as a display device for displaying. Needs an address and display data. Reference numeral 112 is an F for controlling the FLCD 35 to display.
It is an LCD controller.

FIG. 2 is a block diagram showing details of the FLCD controller 112.

Reference numeral 18 denotes a bit map type video memory having one byte of display data for one pixel of the display device, and the data output to the display device has 8 bits of red, green and blue RGB components in total. , 19 designates 0 if the type of display data for one pixel of the display device is a character, and 1 if it is an image at the same address of the video memory 1
1 byte image bit per pixel, 20 CP
Image bit 1 from U11 via system bus 16
An instruction register for instructing a value of 9, that is, 0 or 1, 21 is an image bit for reflecting the value of the instruction register 20 in the image bit 19 at the same address as the video memory 18 when writing to the video memory 18. Additional part, 22
Is address control for decoding and generating necessary addresses from the address information from the system bus 16 to the video memory 18 and the FLCD-I / F 34 (described later). 23 is a system for displaying position information of the mouse controller 15 and shape information from the CPU 11. A cursor register for writing as cursor data via the bus 16 is an image processing enable register for writing 0 from the CPU 11 when halftone image processing is not forcibly performed and writing 1 when halftone image processing may be performed. This is to provide a mode in which the image processing is not forcibly performed because it is not necessary to further perform the halftone image processing when the image processed data is input to the video memory 18. 28 is the image bit 19 and the image processing enable register 2
An AND circuit that takes the logical product of 4 and 27 is a video memory 1
For example, 8-bit data output per pixel from 8 to the display device is converted from the CPU 11 to the display device software which does not depend on the display device to convert the RGB component into 16-bit data. If the output of the AND circuit 28 is 0, palette B30
To 1 (to be described later), if it is 1, a switch for switching to the average density storing process 31 (to be described later), and 30 is an instruction from the CPU 11 to convert the 16-bit display data from the pallet A27 into 4-bit data which is suitable for the FLCD which is the display device of this embodiment. It is a palette B set in step 1, and is converted into 4-bit data of 1 pixel called R, G, B, I, for example. Reference numeral 31 is a kind of image processing device, which performs an average density storage process on the 16-bit display data from the palette A27 and converts it to 4-bit data suitable for the FLCD which is the display device of this embodiment. An OR circuit for taking the logical sum of the result of the pallet B30 and the average density storage processing 31, 34 is the display data from the switch 32, the cursor data from the cursor register 23 is overlaid and output to the display device as the final data, and FL that adds the address from the address control 22 and creates data with address to the FLCD 35
It is a CD interface (hereinafter abbreviated as I / F).

When the FLC unit including the FLCD 35 is assembled in a housing different from the information system main body, there are two ways of dividing the FLCD-I / F 34 and the FLCD 35, that is, a boundary 36 in FIG.

That is, FLCD-I / F 34 and FLCD 3
5 may be a separate body, or the portion on the right side of FIG. 2 with respect to the boundary of 36 in the FLCD-I / F 34 may be included in the FLCD 35.

Next, the operation will be described with reference to the flow chart of FIG.

In S61, the color conversion data is written in the palette A by the display driver software which does not depend on the display device, and the color conversion data which is dependent on the FLC display device is written in the palette B.

In step S62, 1 is written in the image processing enable register 24 when there is a possibility that the average density storage processing, which is one method of halftone image processing, is performed, and 0 is forcibly not performed. ..

In S63, 1 is written in the instruction register 20 if the data group to be written in the video memory 18 is an image, and 0 if it is a character. Such writing is performed by a computer connected to the system bus 16.

In S64, the CPU 11 causes the video memory 1
At the same time as writing the data to 8, the image bit adding unit 21
Writes the 1-bit information written in the instruction register 20 into the image bit 19.

In step S65, when the display data for the FLCD 35 is called from the video memory 18, the value of the image bit 19 indicating whether the image is at the same address as the video memory and the value of the image processable register are ANDed. If the result is '1', that is, the type of display data is image and image processing is performed, the process proceeds to step S66. If the result is '0', that is, the type of display data is character or image processing is not performed, the process proceeds to step S67.

In S66, the display 8-bit data from the video memory 18 passes through the palette A27 to become the 16-bit data designated in the process S61, and the average density process 3 is performed.
At 1, it is processed into 4-bit data that matches the FLCD 35.

In S67, the display 8-bit data from the video memory 18 passes through the palette A27 to become the 16-bit data designated in the process S61, and further the palette B30.
Is processed into 4-bit data matched with the FLCD 35.

In S68, the OR circuit 32 takes the logical sum of the average density processing 31 and the 4-bit data of each of the palettes B30.

In S69, the FLCD-I / F34 performs OR.
The display data from the circuit 32 and the cursor data from the cursor register 23 are combined, a display address from the address control 22 is further added, and the data is converted into address-added data and sent to the FLCD 35.

In the above example, the display side data width of the video memory is 8 bits, the output data of the palette A is 16 bits, and the output data of the palette B30 / average density storage processing 31 is 4 bits, but the data width is arbitrary. A suitable value of

The type of display data can be easily determined by determining whether the display data is an image or a character by the display driver software and adding the data to the data to transfer the data.

The average density preservation method has an advantage that a clear image with high resolution can be obtained even in an image with little shading because the size of the threshold value that determines the threshold value of gradation can be arbitrarily selected.

(Other Embodiment 1) FIG. 4 shows F of another embodiment 1.
A block diagram of the LCD controller is shown and described below.

The description from the video memory 18 to the AND circuit 28 is omitted because it is the same as in FIG.

Reference numeral 30 is a palette B for setting 16-bit display data from the palette A27 to 4-bit data corresponding to the FLCD which is the display device of the present invention by an instruction from the CPU 11. Reference numeral 31 is a kind of image processing. 16-bit display data is subjected to an average density storage process and converted into 4-bit data suitable for the FLCD which is the display device of the present invention. 33 is an average density storage process. A switch for switching from 4-bit data to 4-bit data of the average density storage process 31 if it is 1, 34 is the final data to be output to the display device by superimposing the cursor data from the cursor register 23 on the display data from the switch 32. , FLCD3 by adding the address from the address control 22
FLCD that creates data with address to 5 (described later)
-I / F, 35 is a ferroelectric liquid crystal device.

The operation will be described with reference to the flowchart of FIG.

The processes S61 to S64 are the same as those in FIG.

In S71, the display 8-bit data from the video memory 18 passes through the palette A27 and becomes the 16-bit data designated in the process S61, and further the palette B30.
Then, the average density processing 31 is processed into 4-bit data matched with the FLCD 35.

In S65, when the display data for the FLCD 35 is called from the video memory 18, the value of the image bit 19 indicating whether the image is at the same address as the video memory and the value of the image processable register are ANDed. If the result is '1', that is, the type of display data is an image and image processing is performed, the process proceeds to step S72. If the result is '0', that is, the type of display data is character or image processing is not performed, the process proceeds to step S73.

In S72, the display data is subjected to the average density storage processing, and the selected data is selected.

In step S73, the display data selected is subjected to the color conversion designated by the palette B, and the selected data is selected.

In S74, the display data from the switch 33 and the cursor data from the cursor register 23 are combined by the FLCD-I / F 34, the display address from the address control 22 is further added, and the data is converted into address-added data. Send to FLCD35.

(Other Embodiment 2) FIG. 6 shows F of another embodiment 2.
A block diagram of the LCD controller is shown and described below.

This is a modification of the average density storage processing 31 of the image processing of the first embodiment to an error diffusion processing of 38. The 16-bit display data from the palette A27 is subjected to the error diffusion processing and the present invention is used. It is converted into 4-bit data suitable for the FLCD which is a display device.

The error diffusion method has better gradation than the dither method,
This is an effective method for image information with high resolution.

(Other Embodiment 3) FIG. 7 shows an F of another embodiment 3.
A block diagram of the LCD controller is shown and described below.

This is a modification of the average density storage process 31 of the image processing of the first embodiment to the dither process of 39. The 16-bit display data from the palette A27 is subjected to the dither process and the display device of the present invention is used. It is converted into 4-bit data suitable for the FLCD.

The dither method has a simple circuit and is effective in an output device having a relatively low resolution such as a display device. Only the target line needs to be binarized, and peripheral image data is required for binarization. Compared with other error diffusion methods / average density preservation methods, it has the advantage of being easier to control, but the quality of the displayed image is slightly inferior.

(Other Embodiment 4) FIG. 8 shows F of another embodiment 4.
A block diagram of the LCD controller is shown and described below.

This is obtained by omitting the image processing enable register 24 and the AND circuit 28 of the first embodiment, and the switch 29 directly uses the output of the image bit 19.

FIG. 9 shows a flowchart.

This is except for the processing S62 of the first embodiment, and there is no mode for forcibly stopping the image processing. When the display data for the FLCD 35 is called from the video memory 18 in the processing S95, if the result of the value of the image bit 19 indicating whether the image is at the same address as the video memory is '1', that is, the type of the display data is an image, the processing S66 If the result is "0", that is, if the type of display data is a character, the process proceeds to step S67.

With the above structure, the following effects can be obtained according to this embodiment. Since it is possible to instantly judge whether or not to perform image processing while displaying the display data, it is possible to easily and quickly process an area where images and characters are complicated. Figure 1
This result is shown in 0. Image area 52 as in this example
A complicated and complicated area in which the character area 51 (within the range of the dotted line) is overlaid on the area can be easily processed at high speed. Since no image processing is performed on the character area, the outline of the character is not blurred. This is shown in Figure 1, for example.
It is shown in the character area 51 of 0. Since the display data after the image processing is overlaid on the cursor, the cursor is not subjected to the image processing, so that the outline of the cursor does not become unclear.

According to the embodiment shown in FIG. 4, since the output according to the average density storage method is selected after the processing according to the average density storage method is performed, the error diffusion processing of the average density storage method can be favorably performed.

As described above, in the embodiment, the process called the average density preservation method is performed as an example of the error diffusion process. However, the present invention is not limited to this process, and a simple error diffusion process may be performed.

[0052]

According to the present invention, since the image data after the error diffusion processing is selected based on the characteristic information, the error diffusion processing can be favorably performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus according to a first embodiment of this invention.

FIG. 2 is a block diagram of an FLCD controller in which an average density storage process according to the first embodiment of the present invention is performed and a switch is provided before image processing.

FIG. 3 is a flowchart of the FLCD controller in which the average density storage processing according to the first embodiment of the present invention is performed and the switch is before image processing.

FIG. 4 is a block diagram of an FLCD controller in which an average density storage process according to another embodiment of the present invention is performed and a switch is behind image processing.

FIG. 5 is a flowchart of an FLCD controller in which an average density storage process according to another embodiment of the present invention is performed and a switch is behind image processing.

FIG. 6 is a block diagram of an FLCD controller that has been subjected to error diffusion processing according to another embodiment 2 of the present invention.

FIG. 7 is a diagram showing another example F of the present invention, which has been subjected to the dither processing.
The block diagram of LCD controller.

FIG. 8 is a block diagram of an FLCD controller excluding an image processing enable register according to another embodiment 4 of the present invention.

FIG. 9 is a flowchart of the FLCD controller excluding the image processing enable register according to another embodiment 4 of the present invention.

FIG. 10 is an example of an image processed by the apparatus according to the embodiment of the present invention.

FIG. 11 is an example of an image showing conventional processing.

[Explanation of symbols]

 11 CPU 101 Arithmetic Processor 12 Main Memory 13 ROM 102 DMAC 103 Interrupt Controller 104 Real Time Clock 14 Keyboard Controller 105 Keyboard 106 HDD Controller 107 Hard Disk Device 108 FDD Controller 109 Floppy Disk Device 15 Mouse Controller 110 Mouse 111 RS232C Interface 113 Printer Interface 112 FLCD Controller 16 System Bus 18 Video Memory 19 Image Bit 20 Instruction Register 21 Image Bit Addition Section 22 Address Control 23 Cursor Register 24 Image Processing Allowed Register 27 Palette A 28 AND Circuit 29, 33 Switch 30 Palette B 31 Average Density Saving Processing 32 OR Road 34 FLCD-I / F 35 FCLD 38 error diffusion process 39 dithering 51,55 character region 52, 56 the image area

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Tatsuya Sakashita 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Morimoto Hajime 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Co., Ltd. (72) Inventor Toshiyuki Shintani Canon 3-30-2 Shimomaruko, Ota-ku, Tokyo Within Canon Inc. (72) Inventor Junichi Tanahashi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Kenzo Ina 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (8)

[Claims] 1. Storage means for storing display image data, processing means for performing error diffusion processing to perform halftone processing on the display image data, and information for indicating characteristics of the display image data is generated. An image processing apparatus comprising: a generating unit; and a selecting unit that selects an output of the processing unit based on characteristic information generated by the generating unit. 2. The image processing apparatus according to claim 1, further comprising a synthesizing unit for synthesizing the partial image data with the output of the processing unit selected by the selecting unit. 3. Generation means for generating display image data, storage means for storing the display image data, processing means for performing error diffusion processing to perform halftone processing on the display image data, and the display. An electronic device comprising: a generation unit that generates information indicating the characteristic of the image data for use, and a selection unit that selects the output of the processing unit based on the characteristic information generated by the generation unit. 4. The electronic device according to claim 3, further comprising a synthesizing unit for synthesizing the partial image data with the output of the processing unit selected by the selecting unit. 5. Storage means for storing display image data, processing means for performing error diffusion processing to perform halftone processing on the display image data, and information indicating characteristics of the display image data is generated. Generating means, selecting means for selecting an output of the processing means based on the characteristic information generated by the generating means, and display means for displaying according to the output selected by the selecting means. Display device. 6. The display device according to claim 5, further comprising a synthesizing unit for synthesizing the partial image data with the output of the processing unit selected by the selecting unit. 7. The display device according to claim 5, wherein the display means is a ferroelectric liquid crystal. 8. Display data storage means for storing display data including color information, discrimination means for discriminating the type of display data, and data obtained by the discrimination means are stored at the same address as the display data. Discrimination data storage means, sorting means for sorting data from the display data storage means corresponding to data obtained from the discrimination data storage means, and different processing for the display data sorted by the sorting means. A display device comprising: an image processing means for performing; a combining means for combining predetermined partial data with the display data after the image processing means; and a display means for displaying an output of the combining means.