JPH053216A - Charge transfer device and solid-state image pick-up device - Google Patents

Abstract

PURPOSE:To provide a charge transfer device wherein device characteristics of a peripheral circuit are not deteriorated at interface levels and trap levels and a charge transfer part has predetermined dielectric voltage, and further saturation characteristics of a CCD channel with respect to signal charges are not deteriorated. CONSTITUTION:A title charge transfer device comprises a charge transfer part and a peripheral circuit part both formed on a silicon substrate 5. The charge transfer part includes transfer electrodes 58, 60 formed through a laminated insulating film composed of a silicon oxide film 56 and a silicon nitride film 57. The peripheral circuit part includes 2 gate electrode 69 formed through a single layer insulating film composed of a silicon oxide film 68. In the laminated insulating film, the lower layer silicon oxide film 56 has its thickness ranging from 10 to 200nm and the upper layer silicon nitride film 57 has its thickness ranging from 10nm to 100nm.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device used as a solid-state image pickup device, a memory device, and a delay device, and more particularly to a charge transfer device using an ONO gate insulating film, which uses a surface channel. The present invention relates to a charge transfer element that reduces the interface state of a transistor in a circuit, a method for manufacturing the same, and a solid-state imaging device.

[0002]

2. Description of the Related Art A charge transfer device is constructed by using a two-layer or three-layer polysilicon gate and an embedded n-type transfer channel. In order to efficiently transfer in a continuous channel, a three-layer structure (generally called an ONO film) of a silicon oxide film, a silicon nitride film, and a silicon oxide film is often used as a gate insulating film. This is because a gate insulating film having the same film thickness is used to suppress fluctuations in potential in the transfer path, and a thick silicon oxide film formed below the lower gate end when forming a second or higher layer gate. The occurrence of (so-called gate bird's beak) is suppressed. Also, the dielectric strength is improved as compared with a simple silicon oxide film.

An example of a charge transfer element using an ONO film is disclosed in Japanese Patent Laid-Open No. 220450/1990. Next, the charge transfer device and the manufacturing method thereof disclosed in the above publication will be described with reference to the drawings. Figure 1
FIG. 1 shows a sectional view of the charge transfer device. In FIG. 11, 1
Is a charge transfer part, 2 is a peripheral circuit part, 3 is a semiconductor substrate, 4 is an isolation region for electrically separating the charge transfer part 1 and the peripheral circuit part 2, and 5 is silicon which is a gate insulating film of the charge transfer part 1. An oxide film, 6 is a silicon nitride film, 7 is a silicon oxide film, and 8 is a laminated insulating film composed of a silicon oxide film 5, a silicon nitride film 6, and a silicon oxide film 7. 9
Is a first transfer electrode, 10 is a silicon oxide film, 11 is a second
Of the transfer electrode. Reference numeral 12 is a gate insulating film of the peripheral circuit section 2, 13 is a source / drain, and 14 is a gate electrode. 16 is a surface protective film.

As described above, in the conventional charge transfer device, the laminated insulating film 8 is formed as the gate insulating film under the transfer electrodes 9 and 11 of the charge transfer portion 1, whereas the peripheral circuit portion 2 is formed.
The gate insulating film 12 is composed of a single-layer insulating film.
In such a configuration, since the gate electrode of the peripheral circuit section 2 is formed of a single-layer insulating film, it is easy to obtain a desired threshold voltage, and each transfer of the charge transfer section 1 is facilitated. Since the electrodes 9 and 11 are formed on the laminated insulating film 8, the pinhole phenomenon does not occur.

FIG. 12 is a cross-sectional view in order of the steps, illustrating a method for manufacturing the charge transfer device shown in FIG. Here, in FIG.
The manufacturing method will be described in detail below using the same numbers as those used in. First, as shown in FIG.
The isolation insulating film 4 is formed on the semiconductor substrate 3. Next, FIG.
As shown in FIG. 2B, a silicon oxide film 5 is formed on the semiconductor substrate 3 by thermal oxidation. Subsequently, the silicon nitride film 6 is formed on the silicon oxide film 5 by the CVD method. Further, a silicon oxide film 7 is formed on the silicon nitride film 6. Thus, the laminated insulating film 8 is formed and obtained.

Next, as shown in FIG.
The transfer electrode 9 of the layer is formed by the CVD method and selective etching. Further, a silicon oxide film 10 which is an interlayer insulating film is formed. Next, as shown in FIG.
The charge transfer unit 1 is covered with a resist 15. Then, the laminated insulating film 8 formed on the peripheral circuit portion 2 is removed by etching using the resist 15 as a mask.

Next, as shown in FIG. 12E, the surface of the semiconductor substrate 3 is thermally oxidized to form the gate insulating film 12 in the peripheral circuit section 2. Next, the transfer electrode 11 and the gate electrode 14 are formed of the second-layer polycrystalline silicon. Finally,
The source / drain 13 is formed in the peripheral circuit section 2.

[0008]

SUMMARY OF THE INVENTION In the above conventional configuration,
There is no definite description about the film thickness of each layer of the laminated insulating film of the charge transfer section 1, and a diffusion layer having a predetermined impurity concentration is formed to have a predetermined withstand voltage, a transfer efficiency and a signal of a CCD channel. It is not possible to obtain a charge transfer element having a saturation characteristic against electric charges.

Further, there is no regulation of the film thickness of the insulating film used as the gate insulating film under the transfer electrodes 9 and 11, and depending on the setting of the film thickness, the value (φ _L ) of the driving voltage on the low voltage side is It may become too low and transfer efficiency may deteriorate, or the value (φ _H ) on the high voltage side of the drive voltage may become too high and the pulse generator for driving may need to have high withstand voltage. .

Further, there is no disclosure regarding the use of this charge transfer device as a solid-state image pickup device. Further, the MIS transistor of the charge transfer device has a low amplifier noise by controlling the film thickness of its gate insulating film, and thus the conventional M
Regarding the fact that it can be suppressed to about 2/5 times that of the IS transistor and the frequency characteristics,
There is no description about the conditions under which the IS transistor can be made about 1.4 times higher than the conventional MIS transistor.

Furthermore, since it is not possible to set a plurality of types of film thicknesses of the gate insulating film of the MIS transistor, a transistor that reduces ON resistance during switching to reduce noise and a transistor such as a load transistor which is used only as a resistor. And cannot coexist. Further, in the method of manufacturing the charge transfer element, the film thickness of the silicon oxide film in the peripheral circuit portion is composed of only one type,
It is impossible to make plural kinds of silicon oxide film thicknesses in accordance with the purpose of the peripheral circuit.

Further, in order to form the gate insulating film of the peripheral circuit portion, all the ONO film formed in the charge transfer portion is once removed. For this reason, the process becomes complicated, and when the gate insulating film of the peripheral circuit portion is formed, the first transfer electrode is formed in the upper layer of the charge transfer portion. If the gate insulating film is oxidized in this state, the exposed silicon oxide film grows in the upper layer of the ONO film and becomes a bird's beak of the first transfer electrode, which deteriorates the characteristics of the charge transfer element.

Further, since the exposed silicon oxide film of the ONO film grows due to the formation of the gate insulating film in the peripheral circuit portion, the film thickness of the insulating film immediately below the first transfer electrode and the insulating film immediately below the second transfer electrode. Difference occurs in the film thickness. For this reason, a uniform channel is not formed immediately below the transfer electrode, and the reliability of the characteristics of the charge transfer element deteriorates. Further, the region of the peripheral circuit portion from which the silicon nitride film is removed is affected by the stress when the isolation region is formed, and causes a fatal defect in the peripheral circuit characteristics.

Further, when transistors having different purposes are formed in the peripheral circuit section, only transistors having a single silicon oxide film thickness can be obtained. It is an object of the present invention that the peripheral circuit portion does not deteriorate in device characteristics due to interface states or trap levels, the charge transfer portion has a predetermined withstand voltage, and CC
It is an object of the present invention to provide a charge transfer device which is not deteriorated in the saturation characteristic with respect to the signal charge of the D channel.

Another object is that the transfer efficiency is not deteriorated,
An object of the present invention is to provide a charge transfer element that does not require a pulse generator to have a high breakdown voltage. Another object of the present invention is to provide a solid-state imaging device using a charge transfer element, which does not attenuate the light incident on the photodiode.

Another object is that the amplifier noise is low,
It is to provide a charge transfer device having high frequency characteristics.
An object of the present invention is to provide a method for manufacturing a charge transfer device that can coexist a transistor that reduces ON resistance during switching to reduce noise and a transistor such as a load transistor that is used only as a resistor. .

Another object of the present invention is to provide a method of manufacturing a charge transfer element which can change the film thickness of a silicon oxide film according to the purpose of a peripheral circuit section.
Another object of the present invention is to provide a method of manufacturing a charge transfer element that is not affected by stress when the isolation region is formed.

[0018]

In order to solve the above problems, a charge transfer element according to claim 1 is a charge transfer element in which a charge transfer portion and a peripheral circuit portion are formed on a semiconductor substrate. The charge transfer portion has a transfer electrode formed through a laminated insulating film, the peripheral circuit portion has a gate electrode formed through a single-layer insulating film, and the laminated insulating film has at least a lower layer as a film. It is composed of a silicon oxide film having a thickness of 10 nm to 200 nm, and the upper layer has a film thickness of 10 nm to 100 n.
m silicon nitride film.

The charge transfer device according to claim 2 is the same as that according to claim 1.
In the charge transfer device described above, a silicon oxide film having a film thickness of 5 nm is formed on the silicon nitride film forming the laminated insulating film. The charge transfer device according to claim 3 is the charge transfer device according to claim 1.
In the charge transfer device described above, the gate insulating films of the plurality of transistors formed in the peripheral circuit section have different thicknesses.

The charge transfer device according to claim 4 is the charge transfer device according to claim 1.
In the charge transfer device described above, at least a load transistor serving as a resistance exists in the plurality of transistors formed in the peripheral circuit portion. The solid-state image pickup device according to claim 5, wherein the charge transfer part and the photodiode part are formed on a semiconductor substrate, and the charge transfer part is a transfer electrode formed via a laminated insulating film. The photodiode section has a single-layer insulating film formed on the semiconductor substrate, and the laminated insulating film has at least a lower layer made of a silicon oxide film and an upper layer made of a silicon nitride film. The single-layer insulating film is composed of a silicon oxide film.

A charge transfer device according to a sixth aspect of the present invention is a charge transfer device in which a charge transfer portion and a peripheral circuit portion are formed on a semiconductor substrate, and the charge transfer portion and the peripheral circuit portion are separated in a rectangular shape. A region, a region of a single-layer insulating film formed in the peripheral circuit portion inside the isolation region and with a gap, a gate electrode formed substantially in the center of the region, and the gate electrode Source / drain contact holes provided on both sides of and in the region.

A charge transfer device according to a seventh aspect is the sixth aspect.
In the charge transfer device described in the above, the gap is separated from the end of the separation region by a distance equal to or greater than a film thickness of the separation region. 9. The method of manufacturing a charge transfer device according to claim 8, wherein a step of growing an isolation region in a predetermined region of the main surface of the semiconductor substrate, a step of forming a first silicon oxide film on the semiconductor substrate, and the first A step of forming a silicon nitride film on the silicon oxide film, a step of removing the silicon nitride film in the first region to be a peripheral circuit part, and then the first step.
Removing the first silicon oxide film in the region of
Forming a second silicon oxide film on the upper surface of the second region to be the charge transfer portion with the silicon nitride film exposed to the entire surface; and a first transfer electrode to the first region to be the charge transfer portion. And simultaneously forming a gate electrode of the peripheral circuit section through the second silicon oxide film,
A step of oxidizing the first transfer electrode to form a third silicon oxide film, and a step of forming a third silicon oxide film through the third silicon oxide film.
And forming a transfer electrode.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a charge transfer device, the step of growing an isolation region in a predetermined region of the main surface of a semiconductor substrate, and then the step of forming a first silicon oxide film on the semiconductor substrate. Then, a step of forming a silicon nitride film on the first silicon oxide film, a step of removing the silicon nitride film in a first region to be a peripheral circuit section, and a step of removing the first silicon film in the first region. Second step of removing the silicon oxide film, and then the second step in the state where the silicon nitride film is entirely exposed on the upper surface of the second region to be the charge transfer portion.
Forming a silicon oxide film, and then forming a first transfer electrode in the second region to be the charge transfer portion, and simultaneously forming the second silicon oxide film in a third region in the first region. Forming a first gate electrode via
Then, the first transfer electrode is oxidized and at the same time the first transfer electrode is oxidized.
Forming a third silicon oxide film in the fourth region in the region of 2), and then forming a second transfer electrode in the second region serving as the charge transfer unit via the third silicon oxide film. And simultaneously forming a second gate electrode in the fourth region through the third silicon oxide film.

[0024]

According to the present invention, the peripheral circuit portion has a gate electrode formed via a single-layer insulating film, and at least the lower layer of the laminated insulating film is formed of a silicon oxide film having a film thickness of 10 nm to 200 nm. And the upper layer has a film thickness of 10 n
Since it is composed of a silicon nitride film of m to 100 nm, it has a predetermined dielectric strength by forming a diffusion layer having a predetermined impurity concentration, and the transfer efficiency and the saturation characteristic against the signal charge of the CCD channel are inferior. No charge transfer device is obtained.

Further, since the insulating film having the above-mentioned thickness is used as the gate insulating film, the value (φ _L ) on the low voltage side of the driving voltage does not become too low, and the transfer efficiency is poor. There is nothing to give down. Further, the value (φ _H ) on the high voltage side of the driving voltage does not become too high, and it is not necessary to make the pulse generator for driving high withstand voltage.

Further, as a result of setting the film thickness as described above, the stability of film formation is good, the reliability of the charge transfer element can be improved, and even if the charge transfer element is used for a long time, C
The effective voltage applied to the CD channel does not change. Further, in the charge transfer device of the present invention, the stress applied to the entire charge transfer device can be reduced by eliminating the silicon nitride film other than under the silicon oxide film. Further, even when this charge transfer element is used as a solid-state image pickup device, since there is no silicon nitride film, light incident on the photodiode is not attenuated.

Since the gate insulating film of the MIS transistor is provided with the silicon oxide film as a single layer, the transistor characteristics are not deteriorated by the interface level and the trap level existing in the insulating film. Therefore, the noise characteristic and the frequency characteristic of the MIS transistor are not deteriorated due to the increase of the interface state density. Further, the threshold voltage V _th of the MIS transistor is not shifted and the mutual conductance g _m is not deteriorated due to the increase of the trap density in the film.

Further, the MIS of the charge transfer device of the present invention
The transistor has a low amplifier noise and can be suppressed to about 2/5 times that of a conventional MIS transistor having a gate insulating film having a laminated structure. Therefore, when the charge transfer element operates, a minute signal charge can be sufficiently amplified. Further, the frequency characteristics of the MIS transistor of this embodiment can be improved by about 1.4 times as compared with the conventional MIS transistor having a gate insulating film having a laminated structure.

Furthermore, the film thickness of the gate insulating film of the MIS transistor can be set to an optimum value in the peripheral circuit section depending on the application. Therefore, it is possible to easily reduce the size of the device and optimize the device characteristics. Furthermore, since the thickness of the gate insulating film of the MIS transistor can be arbitrarily selected, a transistor that reduces ON resistance at the time of switching to reduce noise and a transistor such as a load transistor that is used only as a resistor are present together. be able to. Therefore, it is not necessary to increase the transconductance g _m or increase the size of the transistor. In addition, it is possible to prevent the high frequency characteristic from being deteriorated due to the increase of the added capacitance.

Further, since the silicon nitride film in the peripheral circuit portion is removed, the MIS is formed in a portion where the influence of the interface state is small.
A transistor can be formed. Therefore, the threshold voltage V _th is not degraded by the stress. Further, in the method of manufacturing a charge transfer device according to the present invention, the gate insulating film of the peripheral circuit portion is simultaneously formed in the charge transfer portion having the silicon nitride film as an upper surface, so that the process is simple and the film thickness of the gate insulating film is Can be changed according to the purpose.

Furthermore, since the first transfer electrode of the charge transfer section and the gate electrode of the peripheral circuit section can be formed by self-alignment, the process is easy. When forming transistors having different purposes in the peripheral circuit section, the gate insulating film of the peripheral circuit, the first transfer electrode of the charge transfer section and the gate electrode of the peripheral circuit section are formed in the charge transfer section by self-alignment. ,
Further, the gate insulating film of the transistor having a different purpose can be formed at the same time as the insulating film for electrically isolating the first transfer electrode. At this time, the gate electrodes and the second transfer electrodes of the transistors having different purposes can be formed at the same time. Therefore, the process is easy.

Further, in the method of manufacturing the charge transfer device according to the present invention, the laminated film of the silicon oxide film and the silicon nitride film is removed to form the gate insulating film of the peripheral circuit portion. Therefore, the process is simpler than the conventional process. further,
When the gate insulating film of the peripheral circuit portion is formed, the silicon nitride film is formed on the upper layer of the charge transfer portion. If the gate insulating film is oxidized in this state, the silicon nitride film does not change, that is, only a silicon oxide film of about 5 nm is formed, and the gate insulating film of the peripheral circuit portion can be formed at the same time.

Therefore, the film thickness of the insulating film immediately below the first transfer electrode and the film thickness of the insulating film immediately below the second transfer electrode become substantially uniform.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a sectional view of a charge transfer device according to a first embodiment of the present invention. In the cross-sectional view shown here, the end portion of the buried channel type charge transfer portion and the surface channel MIS transistor serving as the peripheral circuit portion are arranged (corresponding to claim 1).

A p-type diffusion layer 52 is formed on the main surface of the n-type silicon substrate 51. The impurity concentration of the p-type diffusion layer 52 is 1 to 5 × 10 ¹⁶ / cm ³ . The impurity concentration affects the saturation capacity and transfer efficiency of the signal charge of the CCD channel described below. Therefore, it is necessary to keep a predetermined impurity concentration. In addition, the p-type diffusion layer 52
Is formed to have a depth of about 5 μm from the surface of the silicon substrate 51. The depth of the p-type diffusion layer 52 is related to the breakdown voltage with respect to the silicon substrate 51. For this reason, a predetermined depth is set together with the impurity concentration so that the dielectric strength voltage does not deteriorate.

An n-type diffusion layer 53, which serves as a CCD channel, is formed in the portion of the p-type diffusion layer 52 that forms the embedded charge transfer portion. The impurity concentration of the n-type diffusion layer 53 is 5 to 10 × 10 ¹⁶ / cm ³ . The impurity concentration is p
Like the type diffusion layer 52, it affects the saturation capacity and transfer efficiency of the signal charge of the CCD channel. Therefore, it is necessary to keep a predetermined impurity concentration.

As described above, the impurity concentration of the n-type diffusion layer 53 is related to the impurity concentration of the p-type diffusion layer 52. That is, the potential applied to the diffusion layers is optimized so that the CCD channels are depleted. The depth of the n-type diffusion layer 53 is about 0.5 μm from the surface of the silicon substrate 51.
It is formed to be m. The depth of the n-type diffusion layer 53 is set to an appropriate depth so that the transfer efficiency and the saturation capacity are not deteriorated.

MI is attached to the end of the substrate on the surface of the silicon substrate 51.
An S transistor is formed. The MIS transistor and the embedded charge transfer section are electrically insulated from each other by a thick oxide film isolation region 54 called LOCOS. In the MIS transistor region, an n-type diffusion layer 55 serving as a source / drain is formed.

Silicon substrate 51 of embedded charge transfer section
A silicon oxide film 56 is formed on the surface. Since this silicon oxide film 56 becomes a gate insulating film, it is formed to have a thickness of about 80 nm by thermally oxidizing the silicon substrate 51. The film thickness of the silicon oxide film 56 affects the transfer efficiency of the charge transfer device and the saturation characteristic of the CCD channel with respect to the signal charge. Therefore, 10 nm to 2
A film thickness of 00 nm is preferable.

When this film thickness is 10 nm or less, the value (φ _L ) of the driving voltage on the low voltage side becomes too low. That is, the pulse amplitude of the drive voltage becomes low. Therefore, the transfer efficiency is deteriorated. Further, if the film thickness is 200 nm or more, the value (φ _H ) of the driving voltage on the high voltage side becomes too high. Therefore, it is necessary to make the pulse generator for driving high withstand voltage. This is not very practical.

Further, if the driving voltage is to be lowered, the impurity concentration of the n-type diffusion layer 53 must be reduced, and the CC
There is an inconvenience that the saturation capacity of the signal charge of the D channel decreases. A depressurized CV is formed on the silicon oxide film 56.
A silicon nitride film 57 having a film thickness of 40 nm formed by the D method is formed. As described above, in the embedded charge transfer section, the laminated film of the silicon oxide film 56 and the silicon nitride film 57 is used as the gate insulating film.

The thickness of the silicon nitride film 57 affects the withstand voltage of the charge transfer element and the saturation characteristic of the signal charge of the CCD channel. Therefore, 10 nm to 100 n
A film thickness of m is preferable. When this film thickness is 10 nm or less, the dielectric strength is deteriorated and the film formation stability is deteriorated. For this reason, there arises a disadvantage that the reliability of the element deteriorates.

Further, if the film thickness is 100 nm or more, the total film thickness of the gate insulating film becomes large, and the silicon oxide film 56 is formed.
As in the case of a large thickness, the driving voltage rises or the saturation capacity of the signal charge of the CCD channel decreases. Also,
The silicon nitride film 57 has a large amount of charge trap levels in the film. As the film thickness increases, the amount of trap levels increases, and when the charge transfer device is used for a long time, the effective voltage applied to the channel of the CCD changes and the reliability of the device deteriorates.

A transfer electrode 58 is formed on the silicon nitride film 57.
Are formed. The transfer electrode 58 is formed of the silicon oxide film 5.
It is electrically separated from the adjacent transfer electrode 60 via 9. The transfer electrodes 58 and 60 are formed of a phosphorus-doped polycrystalline silicon film. The thickness of the polycrystalline silicon film is about 0.2 to 0.6 μm. Here, it is important that the end of the silicon nitride film 57 and the end of the polycrystalline silicon film of the transfer electrode 58 are aligned. Silicon nitride film 5
7 and the end of the polycrystalline silicon film of the transfer electrode 58 are made to coincide with each other, the surface layer of the silicon nitride film 57 on the embedded charge transfer portion is completely formed by the transfer electrodes 58 and 60 and the silicon oxide film 59. Will be covered by.
Thus, the gate electrodes 58 and 60 and the silicon oxide film 5 are
By eliminating the silicon nitride film 7 except for the lower part of 9, the stress applied to the entire charge transfer element can be reduced.

Further, even when this charge transfer element is used as a solid-state image pickup device, since the silicon nitride film is not provided, the light incident on the photodiode is not attenuated. In order to explain this in more detail, FIG.
The cross-sectional shape when the charge transfer device of this embodiment is used in a solid-state imaging device is shown in (corresponding to claim 5).

A p-type diffusion layer 61 is formed from the surface of the silicon substrate 51 in the depth direction of the substrate. p-type diffusion layer 61
A charge transfer portion A and a photodiode portion B are formed in the inside. In the charge transfer portion A, the p-type diffusion layer 52 is formed from the surface of the silicon substrate 51 in the depth direction of the substrate.
An n-type diffusion layer 53 is formed on it. A diffusion layer 62 is formed adjacent to the n-type diffusion layer 53.

Further, a photodiode portion B is formed adjacent to the diffusion layer 62. The photodiode part B is provided with an n-type diffusion layer 63 having a certain depth,
Further, a p-type diffusion layer 64 is provided on the surface of the silicon substrate 51 and above the n-type diffusion layer 63. Usually, the light incident on the photodiode section B forms an electron pair in these diffusion layers. In this way, light can be converted into electrical signals.

A silicon oxide film 56 is formed on the entire surface of the silicon substrate 51. Silicon oxide film 56
Above, a silicon nitride film 57 is formed in a region substantially corresponding to the charge transfer portion A. Furthermore, the silicon nitride film 5
Polycrystalline silicon to be the transfer electrode 58 is formed on the surface 7. Further, a silicon oxide film 65 for insulation is formed so as to surround the transfer electrode 58. The solid-state imaging device transfers the signal that is incident on the photodiode section B and is electrically extracted through the channel directly below the transfer electrode 58.

Therefore, the transfer electrode 58 and the photodiode portion B have a pair of structures. A solid-state imaging device is one in which a plurality of these are formed. The plurality of this pair of elements are electrically insulated from the adjacent pair of elements by the diffusion layer 66. Certain transfer electrode 58
And the silicon substrate 51 in the opening region 67 of the adjacent transfer electrode 58
The photodiode portion B is formed immediately below. Only the silicon oxide film 56 is formed on the silicon substrate 51 on which the photodiode portion B is formed. Normal,
When such a gate insulating film of a transfer electrode having a multilayer film is used, the multilayer film is left on the photodiode portion B, but the incident light has been attenuated and used. However, it is difficult to realize the demand for higher sensitivity of the solid-state imaging device by such a method.

On the other hand, in FIG. 1, a normal MIS transistor is formed in the MIS transistor region. That is, a silicon oxide film 68 to be a gate insulating film is formed with a film thickness of 50 nm on the surface of the silicon substrate 51 between the source and the drain. Further, a gate electrode 69 is formed on the silicon oxide film 68. The gate electrode 69 is formed of a phosphorus-doped polycrystalline silicon film. The film thickness of polycrystalline silicon is about 0.2-0.
It is 6 μm.

In the charge transfer device configured as described above, even if the laminated film of the silicon oxide film and the silicon nitride film is used as the gate insulating film in the embedded charge transfer portion, the transfer characteristics thereof may be adversely affected. Absent. On the other hand, when a laminated film composed of such a silicon oxide film and a silicon nitride film is used as the gate insulating film of the MIS transistor which constitutes the peripheral circuit portion like the conventional charge transfer element, a single-layer gate of the silicon oxide film is used. Compared to the case of this embodiment using the insulating film, the transistor characteristics are deteriorated due to the interface level generated in the laminated film and the trap level existing in the insulating film. The increase in the interface state density of the laminated film deteriorates the noise characteristics and frequency characteristics of the MIS transistor. Further, the increase of the trap density in the film shifts the threshold voltage V _th of the MIS transistor and deteriorates the mutual conductance g _m . Due to these factors, the reliability of the charge transfer device using the laminated film is deteriorated.

In the charge transfer device of this embodiment, the device characteristics do not deteriorate unlike the MIS transistor of the conventional charge transfer device. In order to explain the effects described above in more detail, FIG. 3 shows a charge transfer device of this embodiment and a MIS using a conventional laminated film as a gate insulating film.
The figure which compared the amplifier noise with respect to the charge transfer element which has a transistor, and the gate insulating film kind of amplifier part, and a frequency characteristic is shown.

Black circles in the figure show frequency characteristics, and white circles show amplifier noise. It is the MIS transistor of this embodiment that the gate insulating film type is written as SiO ₂ .
A conventional MIS transistor is written as ONO. From this, the MIS transistor of this embodiment is
The amplifier noise is low and can be suppressed to about 2/5 times that of the conventional MIS transistor. Therefore, when the charge transfer element operates, a minute signal charge can be sufficiently amplified.

Regarding the frequency characteristic, the MIS transistor of this embodiment can be made about 1.4 times higher than the conventional MIS transistor. FIG. 4 shows a sectional view of a charge transfer device according to a second embodiment of the present invention. The cross-sectional view shown here is the surface channel MIS that becomes the end portion of the buried channel type charge transfer portion and the peripheral circuit portion.
A transistor is arranged (corresponding to claim 2).

The difference from the charge transfer device of the first embodiment is that the laminated film provided on the channel portion of the CCD is a laminated film called an ONO film composed of a silicon oxide film, a silicon nitride film and a silicon oxide film on the upper layer. It is formed of a film. That is, the p-type diffusion layer 52 is formed on the main surface of the silicon substrate 51. An n-type diffusion layer 53 that serves as a CCD channel is formed in a portion of the p-type diffusion layer 52 that forms the embedded charge transfer portion.

On the surface of the silicon substrate 51, M is formed at the end of the substrate.
The IS transistor is formed. The MIS transistor and the embedded charge transfer section are electrically insulated from each other by a thick oxide film isolation region 54 called LOCOS. In the MIS transistor region, an n-type diffusion layer 55 serving as a source / drain is formed.

Silicon substrate 51 of embedded charge transfer section
A silicon oxide film 56 is formed on the surface. Since this silicon oxide film 56 becomes a gate insulating film, it is formed to have a thickness of about 80 nm by thermally oxidizing the silicon substrate 51. A depressurized CV is formed on the silicon oxide film 56.
A silicon nitride film 57 having a film thickness of 40 nm formed by the D method is formed.

Further, a silicon oxide film 70 is formed on the silicon nitride film 57. The film thickness of the silicon oxide film 70 is about 5 nm. The silicon oxide film 70 is formed at the same time when the silicon oxide film that is the gate insulating film of the MIS transistor is formed in the manufacturing process described later. When forming the gate insulating film of the MIS transistor, the silicon oxide film 56 is formed in the region of the charge transfer element.
And a silicon nitride film 57 are laminated. When the silicon oxide film 68 of the gate insulating film is formed, the surface of the silicon nitride film 57 is oxidized by 5 nm.

This film thickness changes as the film thickness of the gate insulating film of the MIS transistor is changed. However, the oxide film thickness does not exceed several tens of nm.
Furthermore, such an ON is applied to the gate insulating film of the charge transfer element.
By forming the O film, the reliability of withstand voltage is improved.
Furthermore, since the gate electrode is formed of a laminated film of two or more layers, the film thickness of the insulating film is constant under any electrode. Therefore, the potential under the electrode does not change. Normally, the gate insulating film under the gate electrode is abnormally oxidized at the electrode end called bird's beak due to the oxidation in the subsequent process. However, when the laminated film is used as the gate insulating film as in this embodiment, bird's beak does not occur due to subsequent oxidation, and a uniform channel can be formed.

The effects described in the first embodiment can also be sufficiently obtained. Further, on the silicon nitride film 57,
The transfer electrode 58 is formed. The transfer electrode 58 is electrically separated from the adjacent transfer electrode 60 via the silicon oxide film 59. The transfer electrodes 58 and 60 are formed of a phosphorus-doped polycrystalline silicon film. The thickness of the polycrystalline silicon film is about 0.2 to 0.6 μm.

Here, the end of the silicon nitride film 57 and the end of the polycrystalline silicon film of the transfer electrode 58 are aligned with each other.
A normal MIS transistor is formed in the MIS transistor region. That is, a silicon oxide film 68 to be a gate insulating film is formed with a film thickness of 50 nm on the surface of the silicon substrate 51 between the source and the drain. Further, a gate electrode 69 is formed on the silicon oxide film 68. The gate electrode 69 is formed of a phosphorus-doped polycrystalline silicon film. The film thickness of polycrystalline silicon is about 0.2 to 0.6 μm.

In the charge transfer device configured as described above, even if the laminated film of the silicon oxide film and the silicon nitride film is used as the gate insulating film in the embedded type charge transfer portion, the transfer characteristics thereof may be adversely affected. Absent. On the other hand, when a laminated film including such a silicon oxide film, a silicon nitride film, and a silicon oxide film is used for the gate insulating film of the MIS transistor that constitutes the peripheral circuit portion like the conventional charge transfer element,
Compared with the case of this embodiment using a single-layer gate insulating film of silicon oxide film, the transistor characteristics are deteriorated due to the interface level generated in the laminated film and the trap level existing in the insulating film. By increasing the interface state density of the laminated film, M
Noise characteristics and frequency characteristics of the IS transistor deteriorate. In addition, an increase in trap density in the film causes MI.
The threshold voltage V _th of the S transistor shifts and the mutual conductance g _m deteriorates. Due to these factors, the reliability of the charge transfer device using the laminated film is deteriorated.

In the charge transfer device of this embodiment, since the gate insulating film of the MIS transistor is composed of a single-layer silicon oxide film, its device characteristics are not deteriorated like the MIS transistor of the conventional charge transfer device. Absent. Figure 5
A sectional view of a charge transfer device according to a third embodiment of the present invention is shown in FIG. The cross-sectional view shown here is the surface channel M which becomes the end of the buried channel type charge transfer section and the peripheral circuit section.
An IS transistor is arranged (corresponding to claims 3 and 4).

A p-type diffusion layer 52 is formed on the main surface of the n-type silicon substrate 51. The impurity concentration of the p-type diffusion layer 52 is about 1 to 5 × 10 ¹⁶ / cm ³ . The impurity concentration is
It affects the saturation capacity and transfer efficiency of the signal charge of the CCD channel. Therefore, it is necessary to keep a predetermined impurity concentration. The p-type diffusion layer 52 is formed to have a depth of about 5 μm from the surface of the silicon substrate 51. The depth of the p-type diffusion layer 52 is equal to that of the silicon substrate 51.
It is set in accordance with the impurity concentration and the voltage to be applied so that the withstand voltage between and does not decrease.

An n-type diffusion layer 53, which serves as a CCD channel, is formed in the portion of the p-type diffusion layer 52 that forms the embedded charge transfer portion. The impurity concentration of the n-type diffusion layer 53 is 5 to 10 × 10 ¹⁶ / cm ³ . The impurity concentration affects the saturation capacity of the signal charge of the CCD channel described below. Therefore, it is necessary to keep a predetermined impurity concentration.

The impurity concentration of the n-type diffusion layer 53 is p
It is related to the impurity concentration of the mold diffusion layer 52, and the potential applied to these diffusion layers is optimized so that the channels of the CCD are depleted. The depth of the n-type diffusion layer 53 is formed to be about 0.5 μm from the surface of the silicon substrate 51. The depth of the n-type diffusion layer 53 is equal to that of the silicon substrate 5.
In order to prevent the insulation breakdown voltage between 1 and 1 from deteriorating, it is appropriately set together with the impurity concentration.

On the surface of the silicon substrate 51, M is formed at the end of the substrate.
The IS transistor is formed. The MIS transistor and the embedded charge transfer section are electrically insulated by an isolation region 54 called LOCOS. MIS
An n-type diffusion layer 55 serving as a source / drain is formed in the transistor region.

Silicon substrate 51 of embedded charge transfer section
A silicon oxide film 56 is formed on the surface. Since this silicon oxide film 56 becomes a gate insulating film, it is formed to have a thickness of about 80 nm by thermally oxidizing the silicon substrate 51. The film thickness of the silicon oxide film 56 affects the transfer efficiency of the charge transfer element and the saturation characteristic of the signal charge of the CCD channel. Therefore, 10 nm to 20
The film thickness should be 0 nm. For this film thickness, it is necessary to use the film thickness within the range specified here for the same reason as in the first embodiment.

On the silicon oxide film 56, a 40-nm-thick silicon nitride film 57 formed by the low pressure CVD method is formed. As described above, in the embedded charge transfer section, the laminated film of the silicon oxide film 56 and the silicon nitride film 57 is used as the gate insulating film. The film thickness of the silicon nitride film 57 affects the withstand voltage of the charge transfer element and the saturation characteristic of the signal charge of the CCD channel. Therefore, 10n
It is preferable to set the film thickness to m to 100 nm. This film thickness also needs to be formed in the film thickness range shown here for the same reason as in the first embodiment.

A transfer electrode 58 is formed on the silicon nitride film 57.
Are formed. The transfer electrode 58 is formed of the silicon oxide film 5.
It is electrically separated from the adjacent transfer electrode 60 via 9. The transfer electrodes 58 and 60 are formed of a phosphorus-doped polycrystalline silicon film. The film thickness of polycrystalline silicon is
It is about 0.5 μm. On the other hand, a normal MIS transistor is formed in the MIS transistor region. That is, the silicon oxide film 71 to be a gate insulating film is formed on the surface of the n-type diffusion layer 52 between the source and the drain to a film thickness of 50 n.
It is formed by m. Further, a gate electrode 72 is formed on the silicon oxide film 71. Gate electrode 72
Is formed of a polycrystalline silicon film doped with phosphorus. The film thickness of polycrystalline silicon is about 0.5 μm.

Further, another MIS transistor in which the source or the drain of the MIS transistor is common is also formed. This MIS transistor is p
A silicon oxide film 73 to be a gate insulating film is formed on the surface of the mold diffusion layer 52 to have a film thickness of 100 nm. Further, a gate electrode 74 is formed on the silicon oxide film 73. The gate electrode 74 is formed of a phosphorus-doped polycrystalline silicon film. The film thickness of polycrystalline silicon is about 0.4 μm.

The difference between the two MIS transistors described here is that the film thicknesses of the silicon oxide films 71 and 73 serving as the gate insulating films of the two are different. The gate insulating film of the embedded charge transfer portion is formed of a laminated film, and the charge transfer element is formed so that the gate insulating film of the MIS transistor of the peripheral circuit portion has at least two different film thicknesses. In point.

When a thin film having a constant film thickness is formed on the gate insulating film of the MIS transistor in the peripheral circuit portion (particularly, the amplifier portion) of the charge transfer element, the MIS transistor defined by the purpose of use of the peripheral circuit portion is formed. If one has to do so, the desired properties cannot be obtained. For example, an MIS transistor using a thin gate insulating film has a small on-resistance at the time of switching of the transistor, noise can be reduced, and device characteristics can be improved. However, if the MIS transistor is used only as a resistor like the load transistor, the mutual conductance g _m becomes large. Therefore, in order to have a predetermined resistance value, it is necessary to increase the size of the transistor that must be formed when the gate insulating film is thin. In order to form MIS transistors having different purposes in the peripheral circuit section in this manner, it is necessary to use a gate insulating film having a desired film thickness suitable for each MIS transistor.

Furthermore, in such a peripheral circuit section, the additional capacitance also increases. For this reason, the high frequency characteristics deteriorate. In this embodiment, a MIS transistor having an optimum gate insulating film thickness can be formed depending on the application. Therefore, it is possible to easily reduce the size of the device and optimize the device characteristics.

In the charge transfer device configured as described above, even if a laminated film of a silicon oxide film and a silicon nitride film is used as a gate insulating film in the embedded charge transfer portion, its transfer characteristic is hardly affected. On the other hand, M which constitutes the peripheral circuit section
When such a laminated film is used as the gate insulating film of the IS transistor, it is present in the interface state generated in the laminated film or in the insulating film as compared with the case where a single-layer gate insulating film of a silicon oxide film is used. The transistor characteristics deteriorate due to the trap level. In the charge transfer device of this embodiment, the characteristic deterioration of the MIS transistor of such a charge transfer device does not occur.

FIG. 6 shows a plan view of one transistor for explaining the region where the silicon nitride film of the MIS transistor in the peripheral circuit portion is removed (corresponding to claims 6 and 7).
The hatched area 75 is the area where the silicon nitride film is removed. The MIS transistor is formed on the surface of the n-type diffusion layer of the silicon substrate. The MIS transistor is provided with an isolation region 76 called LOCOS so as to be electrically isolated from peripheral elements. The isolation region 76 is provided around the rectangle. The shaded area 75 is the separation area 76.
Has a slightly smaller area. The shaded area 75 also has a rectangular shape like the separation area 76.

A gate electrode 77 is formed substantially in the center of the isolation region 76. Diffusion layers serving as the source / drain of the MIS transistor are formed in the n-type diffusion layers on the left and right of the long side of the gate electrode 77. The source / drain contact hole 78 is formed by etching a predetermined position of a protective film provided on the upper layer of the MIS transistor. A wiring 79 connected to the source / drain diffusion layers is formed through the contact hole 78.

As described above, the region of the peripheral circuit portion where the silicon nitride film is removed is formed at a predetermined position in order to reduce the influence of the interface state. The position is formed in a flat portion where the stress generated at the time of forming the LOCOS formed in the isolation region 76 does not adversely affect. Such a flat portion extends from the end of the isolation region 76 to the isolation region 7
The film thickness of 6 and the film thickness of the silicon oxide film that is partially removed by etching the silicon nitride film must be separated by a distance corresponding to a total thickness or more.

In the first embodiment, the isolation region 76 has a film thickness of 500 nm, and the silicon oxide film to be removed by etching has a film thickness of 80 nm. From this, the separation regions 76 to 0.
If it is separated from the end of the isolation region 76 by 58 μm or more, the influence of stress is small. If the peripheral circuit portion is formed in the region affected by the stress, the interface order increases and the threshold voltage V _th deteriorates, which causes a reliability problem.

FIG. 7 shows a sectional view of a charge transfer device according to a fourth embodiment of the present invention. In the sectional view shown here, the surface channel MIS transistor serving as the peripheral circuit portion and the end portion of the buried channel type charge transfer portion are arranged (corresponding to claims 2 to 4). 5 is different from the charge transfer device of the embodiment shown in FIG. 5 in that the laminated film provided on the channel portion of the CCD has a three-layer structure including a silicon oxide film, a silicon nitride film, and an upper silicon oxide film, that is, an ONO.
It is formed of a laminated film called a film.

That is, the p-type diffusion layer 52 is formed on the main surface of the silicon substrate 51. An n-type diffusion layer 53 that serves as a CCD channel is formed in a portion of the p-type diffusion layer 52 that forms the embedded charge transfer portion. A MIS transistor is formed at the end of the substrate on the surface of the silicon substrate 51. The MIS transistor and the embedded charge transfer section are electrically insulated from each other by a thick oxide film isolation region 54 called LOCOS.

In the MIS transistor region, an n-type diffusion layer 55 serving as a source / drain is formed. A silicon oxide film 56 is formed on the surface of the silicon substrate 51 of the embedded charge transfer section. This silicon oxide film 5
Since 6 serves as a gate insulating film, the silicon substrate 51 is thermally oxidized to a thickness of about 80 nm.

On the silicon oxide film 56, a 40 nm-thickness silicon nitride film 57 formed by the low pressure CVD method is formed. Further, a silicon oxide film 70 is formed on the silicon nitride film 57. The film thickness of the silicon oxide film 70 is about 5 nm. The silicon oxide film 70 is formed at the same time when the silicon oxide film that is the gate insulating film of the MIS transistor is formed in the manufacturing process described later.

When forming the gate insulating film of the MIS transistor, the region of the charge transfer element is formed by the silicon oxide film 5.
6 and the silicon nitride film 57 are laminated.
When the silicon oxide film 71 of the gate insulating film is formed, the surface of the silicon nitride film 57 is oxidized by 5 nm. This film thickness changes as the film thickness of the gate insulating film of the MIS transistor is changed. However, the oxide film thickness does not exceed several tens nm.

Further, by forming such an ONO film on the gate insulating film of the charge transfer element, the reliability of the dielectric strength voltage is improved. Furthermore, since the gate electrode is formed of a laminated film of two or more layers, the film thickness of the insulating film is constant under any electrode. Therefore, the potential under the electrode does not change. Normally, the gate insulating film under the gate electrode is abnormally oxidized at the electrode end called bird's beak due to the oxidation in the subsequent process. However, when the laminated film is used as the gate insulating film as in this embodiment, bird's beak does not occur due to subsequent oxidation, and a uniform channel can be formed.

Transfer electrodes 58 are formed on the silicon oxide film 70.
Are formed. The transfer electrode 58 is electrically separated from the adjacent transfer electrode 60 via the silicon oxide film 59. The transfer electrodes 58 and 60 are formed of a phosphorus-doped polycrystalline silicon film. The film thickness of polycrystalline silicon is about 0.5 μm. On the other hand, a normal MIS transistor is formed in the MIS transistor region.
That is, the silicon oxide film 71 serving as a gate insulating film is formed on the surface of the n-type diffusion layer 52 between the source and the drain to have a film thickness of 5
It is formed with 0 nm. Further, the silicon oxide film 71
A gate electrode 72 is formed on the top. Gate electrode 7
2 is formed of a phosphorus-doped polycrystalline silicon film. The film thickness of polycrystalline silicon is about 0.5 μm.

Further, another MIS transistor in which the source or the drain of the MIS transistor is common is also formed. This MIS transistor is p
A silicon oxide film 73 to be a gate insulating film is formed on the surface of the mold diffusion layer 52 to have a film thickness of 100 nm. Further, a gate electrode 74 is formed on the silicon oxide film 73. The gate electrode 74 is formed of a phosphorus-doped polycrystalline silicon film. The film thickness of polycrystalline silicon is about 0.4 μm.

The difference between the two MIS transistors described here is that the film thicknesses of the silicon oxide films 71 and 73 serving as the gate insulating films of the two are different. The gate insulating film of the embedded charge transfer portion is formed of a laminated film, and the charge transfer element is formed so that the gate insulating film of the MIS transistor of the peripheral circuit portion has at least two different film thicknesses. In point.

When a thin film having a constant thickness is formed on the gate insulating film of the MIS transistor in the peripheral circuit portion (particularly, the amplifier portion) of the charge transfer element, the MIS transistor defined by the purpose of use of the peripheral circuit portion is formed. If one has to do so, the desired properties cannot be obtained. For example, an MIS transistor using a thin gate insulating film has a small on-resistance at the time of switching of the transistor, noise can be reduced, and device characteristics can be improved. However, if the MIS transistor is used only as a resistor like the load transistor, the mutual conductance g _m becomes large. Therefore, in order to have a predetermined resistance value, it is necessary to increase the size of the transistor that must be formed when the gate insulating film is thin. In order to form MIS transistors having different purposes in the peripheral circuit section in this manner, it is necessary to use a gate insulating film having a desired film thickness suitable for each MIS transistor.

Furthermore, in such a peripheral circuit section, the additional capacitance also increases. For this reason, the high frequency characteristics deteriorate. In this embodiment, a MIS transistor having an optimum gate insulating film thickness can be formed depending on the application. Therefore, it is possible to easily reduce the size of the device and optimize the device characteristics.

In the charge transfer device configured as described above, even if a laminated film of a silicon oxide film and a silicon nitride film is used as a gate insulating film in the embedded charge transfer portion, its transfer characteristics are hardly affected. On the other hand, when such a laminated film is used for the gate insulating film of the MIS transistor that constitutes the peripheral circuit portion, the interface state generated in the laminated film and The transistor characteristics deteriorate due to the trap level existing in the insulating film. In the charge transfer device of this embodiment, the characteristic deterioration of the MIS transistor of such a charge transfer device does not occur.

Next, FIG. 8 shows a plan view of a FIT (frame transfer) type solid-state image pickup device. The FIT type charge transfer element enables high-speed transfer as compared with the charge transfer element described above. For this purpose, a storage unit for holding signal charges is provided. The signal charge from the photoelectric conversion unit is
Usually, it is taken out by using a sense amplifier. In this case, it can be said that the transfer time required for the signal charges to be sent to the sense amplifier is the transfer speed capability of the charge transfer element. On the other hand, since the FIT type charge transfer device has the storage portion, the signal can be taken out directly from the storage portion. Therefore, higher speed operation is possible as compared with the conventional charge transfer element.

Reference numeral 80 is a pixel portion for photoelectric conversion, 81 is a storage portion for temporarily holding the photoelectrically converted charges, and 82 is a horizontal charge transfer portion for sequentially outputting the stored charges. Accumulator 8
In No. 1, the silicon nitride film is not removed by self-alignment like the transistor in the peripheral circuit section. Therefore, the entire surface is covered with the silicon nitride film. In this case, the interface order increases due to the stress of the silicon nitride film. Further, since the silicon nitride film has a low hydrogen permeability, the effect of improving the interface by the hydrogen treatment used in the manufacturing process of the charge transfer device becomes low.

FIG. 9 shows a method of manufacturing the charge transfer device of the present invention.
Process sectional views for explaining the first embodiment of
Corresponding to requirements 8 and 9). First, as shown in FIG.
Then, boron is ion-implanted on the entire surface of the n-type silicon substrate 51.
To do. Then, heat treatment is performed to form the p-type diffusion layer 52.
It At this time, the ion implantation conditions are an acceleration voltage of 100 ke.
V, injection amount 5 × 10¹¹/cm ² Is going on. Also, heat treatment
The treatment was performed at a treatment temperature of 1200 ° C. for 10 hours. See you
At that time, the diffusion depth of the p-type diffusion layer 52 was about 5 μm.

Next, the surface of the silicon substrate 51 is thermally oxidized to form a silicon oxide film 83 with a film thickness of 50 nm.
Then, a silicon nitride film 84 is formed on the silicon oxide film 83 by the low pressure CVD method. The film thickness of the silicon nitride film 84 is 120 nm. After that, a resist pattern covering a region other than the portion to be the isolation region 54 is formed by using normal photolithography. Using this resist pattern as a mask, the silicon nitride film 54 is removed by etching.

Further, the silicon oxide film 83 is removed,
The surface of the silicon substrate 51 is exposed. After this,
The resist pattern is removed. Thus, the silicon substrate 51 from which the silicon nitride film 84 and the silicon oxide film 83 have been removed is thermally oxidized to grow the isolation region 54. The isolation region 54 is called LOCOS, and an oxide film with a film thickness of about 500 nm is formed.

Next, as shown in FIG. 9B, the silicon nitride film 84 formed on the entire surface of the semiconductor substrate 51 is removed by etching. After that, a resist pattern is formed in a region where the MIS transistor is to be formed (not shown) by using ordinary photolithography. After this, the semiconductor substrate 5
1 Phosphorus ion implantation is performed on the entire surface. Ion implantation conditions are
The acceleration voltage is 100 keV and the injection amount is 3 × 10 ¹² / cm ² . After that, the resist pattern is removed.

Further, heat treatment is performed to form an n-type diffusion layer 53 which will be a transfer channel. At this time, the n-type diffusion layer 5
The diffusion depth of 3 is 0.5 μm. Further, the silicon oxide film 83 used as the surface protection film is removed by etching. By this etching, the oxide film in the isolation region 54 is also etched by a thickness corresponding to the film thickness of the silicon oxide film 83.

Next, as shown in FIG. 9C, the semiconductor substrate 51 is thermally oxidized to form a silicon oxide film 56 with a thickness of 80 nm. Furthermore, the thickness is 40 nm by the low pressure CVD method.
Of silicon nitride film 57 is grown on the silicon oxide film 56. At this time, the film thickness of the silicon oxide film 56 is 10 nm to
Within the range of 200 nm, the film thickness of the silicon nitride film 57 is
Within the range of 10 nm to 100 nm, it is possible to find the optimum film thickness for the characteristics of the charge transfer device and the circuit driving conditions.

After that, a resist pattern having an opening in the peripheral circuit region for forming the MIS transistor is formed by using ordinary photolithography. The silicon nitride film 57 is removed by plasma etching using this resist pattern as a mask. Thus, the silicon nitride film in the region for forming the MIS transistor is removed.

Further, the silicon oxide film 56 exposed in this region is removed by wet etching with a mixed solution of hydrofluoric acid and ammonium fluoride. It goes without saying that a plasma etching method may be used for etching the silicon oxide film 56. Here, the silicon substrate 51 is exposed in the region where the MIS transistor is formed. However, the etching amount of the silicon oxide film 56 does not have any adverse effect in the subsequent steps even if the etching is performed until the semiconductor substrate 51 is exposed on the surface and the silicon oxide film 56 is slightly left.

Before wet etching the silicon oxide film 56, a step of facilitating the wet etching may be performed by exposing it to oxygen plasma for the purpose of removing dirt on the surface of the silicon oxide film 56. Next,
The resist pattern is removed. Then, thermal oxidation is performed to form a silicon oxide film 68 on the exposed peripheral circuit portion on the semiconductor substrate 51.

At this time, the embedded charge transfer device section is
A two-layer film including a silicon oxide film 56 and a silicon nitride film 57 is formed. Since the upper silicon nitride film 57 has a low oxidation rate, it is not affected by the increase in film thickness. Therefore, the film thickness of the silicon oxide film 68 which becomes the gate insulating film of the MIS transistor can be freely set.

At this time, at the same time, a silicon oxide film 70 having a film thickness of about 5 nm is grown on the silicon nitride film 57 of the charge transfer portion. In this embodiment, a silicon oxide film 68 having a film thickness of about 50 nm is formed by optimizing the withstand voltage characteristics, frequency characteristics and noise characteristics.

After that, as shown in FIG. 9D, a first polycrystalline silicon film is vapor-deposited and doped with phosphorus to have a low resistance, and the first transfer electrode 58 of the charge transfer element and its periphery are photoetched. The gate electrode 69 of the circuit portion is formed at the same time. At this time, the etching conditions for the polycrystalline silicon film are set so that the etching rate ratio to the underlying silicon nitride film 57 is large, so that the silicon nitride film 57 is hardly etched.

Next, as shown in FIG. 9E, the polycrystalline silicon film is oxidized to form a silicon oxide film 59.
As a result, the first transfer electrode 58 becomes the second transfer electrode 60.
Electrically isolated from. After that, a second polycrystalline silicon film is vapor-deposited and doped with phosphorus to have a low resistance, and the second transfer electrode 60 of the charge transfer element is formed by photoetching.

After that, the gate insulating film below the second transfer electrode 60 of the second polycrystalline silicon film is changed to the first transfer electrode 58.
It has the same thickness as the lower gate insulating film. That is, the gate insulating film under both electrodes has the sum of the film thicknesses of the silicon oxide film 56 and the silicon nitride film 57. Therefore, when the charge transfer element is operated, a uniform CCD channel can be obtained.

As described above, according to the method of manufacturing the charge transfer device of this embodiment, the laminated film of the silicon oxide film 56 and the silicon nitride film 57 is removed to form the silicon oxide film 68 of the gate insulating film in the peripheral circuit portion. To do. Therefore, the process is simpler than the conventional process. Further, when the gate insulating film 68 of the peripheral circuit portion is formed, the silicon nitride film 57 is in the upper layer of the charge transfer portion. When the silicon oxide film 68 of the gate insulating film is oxidized in this state, the silicon nitride film 57 does not change, that is, only the silicon oxide film 70 of about 5 nm is formed, and at the same time the gate insulating film of the peripheral circuit portion is formed. You can

Therefore, the film thickness of the insulating film immediately below the first transfer electrode 58 and the film thickness of the insulating film immediately below the second transfer electrode 60 become uniform. The second transfer electrode 60 is also formed by similar photoetching, but the first transfer electrode 58 and the second transfer electrode 6 are formed.
The silicon nitride film 57 in the region other than the lower portion of 0 is simultaneously removed by etching when the second transfer electrode 60 is self-aligned.

At this time, the polycrystalline silicon film is etched under the condition that the etching rate ratio between the polycrystalline silicon film and the underlying silicon nitride film 57 is small. Transfer electrode 58,
By removing the silicon nitride film 57 other than the lower part of 60, the stress applied to the entire device is reduced. Further, when the charge transfer device is used for a solid-state image pickup device or the like, it is possible to prevent attenuation of light incident on the photodiode by removing the silicon nitride film.

After that, an insulating film is formed and aluminum wiring is performed to form a charge transfer element. Through the above steps, the gate insulating film can be formed of the laminated film having excellent stability in the CCD channel portion, and the transistor can be formed of the gate insulating film of the silicon oxide film 68 having a small interface state in the peripheral circuit portion.

Surface channel MOS transistor of peripheral circuit section
Silicon with few interface states and trap states in the film
Since an oxide film is used, noise characteristics due to interface state density
And the threshold voltage V due to the trap density in the film_thShi
And transconductance g _mO due to reliability such as deterioration of
Excellent compared to a charge transfer device formed only with an NO film
The device is obtained.

FIG. 10 is a process sectional view for explaining the second embodiment of the method of manufacturing a charge transfer device according to the present invention (corresponding to claim 10). The second embodiment is based on the first
In the manufacturing method shown in the above embodiment, a manufacturing method when two or more MIS transistors are formed will be described. First, as shown in FIG. 10A, boron is ion-implanted into the entire surface of the n-type silicon substrate 51. Then, heat treatment is performed to form the p-type diffusion layer 52. At this time, the diffusion depth of the p-type diffusion layer 52 is about 5 μm.

Next, the surface of the silicon substrate 51 is thermally oxidized to form a silicon oxide film 83 with a film thickness of 50 nm.
Then, a silicon nitride film 84 is formed on the silicon oxide film 83 by the low pressure CVD method. The film thickness of the silicon nitride film 84 is 120 nm. After that, a resist pattern covering a region other than the portion to be the isolation region 54 is formed by using normal photolithography. Using this resist pattern as a mask, the silicon nitride film 84 is removed by etching.

Further, the silicon oxide film 83 is removed,
The surface of the silicon substrate 51 is exposed. After this,
The resist pattern is removed. Thus, the silicon substrate 51 from which the silicon nitride film 84 and the silicon oxide film 83 have been removed is thermally oxidized to grow the isolation region 54. The isolation region 54 is called LOCOS, and an oxide film with a film thickness of about 500 nm is formed.

Next, as shown in FIG. 10B, the silicon nitride film 84 formed on the entire surface of the semiconductor substrate 51 is removed by etching. After that, a resist pattern is formed in a region where the MIS transistor is to be formed (not shown) by using ordinary photolithography. After that, ion implantation is performed on the entire surface of the semiconductor substrate 51. After that, the resist pattern is removed.

Further, heat treatment is performed to form an n-type diffusion layer 53 which will be a transfer channel. At this time, the n-type diffusion layer 5
The diffusion depth of 3 is 0.5 μm. Further, the silicon oxide film 83 used as the surface protection film is removed by etching. Next, as shown in FIG. 10C, the semiconductor substrate 5
1 is thermally oxidized to form a silicon oxide film 56 with a thickness of 80 nm.

Further, a silicon nitride film 57 having a thickness of 40 nm is grown on the silicon oxide film 56 by the low pressure CVD method.
Then, using a normal photolithography, a resist pattern having an opening in the region where the first MIS transistor is formed in the peripheral circuit portion is formed (not shown). The silicon nitride film 57 is removed by plasma etching using this resist pattern as a mask. Thus, the silicon nitride film 57 in the region for forming the first MIS transistor is removed.

Further, the silicon oxide film 56 exposed in this region is removed by wet etching with a mixed solution of hydrofluoric acid and ammonium fluoride. It goes without saying that a plasma etching method may be used for etching the silicon oxide film 56. Here, the silicon substrate 51 is exposed in the region where the MIS transistor is formed. Next, the resist pattern is removed.

Thereafter, as shown in FIG. 10D, thermal oxidation is performed to form a silicon oxide film 71 on the exposed semiconductor substrate 51. At this time, the embedded charge transfer unit is
A two-layer film including a silicon oxide film 56 and a silicon nitride film 57 is formed. Since the upper silicon nitride film 57 has a low oxidation rate, it is not affected by the increase in film thickness. Therefore, the film thickness of the silicon oxide film 71 which becomes the gate insulating film of the MIS transistor can be freely set. Here, the film thickness was set to 50 nm.

At this time, at the same time, a silicon oxide film 70 having a film thickness of about 5 nm is grown on the silicon nitride film 57 of the charge transfer portion. After that, a first polycrystalline silicon film is vapor-deposited and doped with phosphorus to have a low resistance, and the first transfer electrode 58 of the charge transfer element and the gate electrode 72 of the peripheral circuit portion are simultaneously formed by photoetching. At this time, the silicon oxide film 71 to be the gate oxide film of the first MIS transistor is formed simultaneously with the etching of the gate electrode 72.

After that, a resist pattern having an opening in the region for forming the second MIS transistor in the peripheral circuit portion is formed by using ordinary photolithography (not shown). Then, as shown in FIG. 10E, the silicon nitride film 57 in the peripheral circuit portion is removed by plasma etching using this resist pattern as a mask. Thus the second
The silicon nitride film 57 in the region for forming the MIS transistor is removed.

Further, the silicon oxide film 56 exposed in this region is removed by wet etching with a mixed solution of hydrofluoric acid and ammonium fluoride. Here, the silicon substrate 51 is exposed in the region where the MIS transistor is formed. Next, the resist pattern is removed. Then, thermal oxidation is performed to form a silicon oxide film 73 on the exposed semiconductor substrate 51. By this oxidation step, the polycrystalline silicon film of the transfer electrode 58 is also oxidized and a silicon oxide film 59 is formed. This electrically insulates the first transfer electrode from the second transfer electrode.

At this time, the silicon oxide film 7 is formed in the region of the buried charge transfer portion where the first transfer electrode 58 is not formed.
0 is formed. By forming the silicon oxide film 73 which is the gate insulating film of the second MIS transistor, the silicon oxide film 70 is further grown. However, again, since the lower silicon nitride film 57 has a low oxidation rate,
There is no effect due to increased film thickness. Therefore, MI
Silicon oxide film 7 to be the gate insulating film of S transistor
The film thickness of 3 can be set freely. Here, the film thickness is 80 nm
Set to.

After that, a second polycrystalline silicon film is vapor-deposited and doped with phosphorus to have a low resistance, and the second transfer electrode 60 of the charge transfer element and the gate electrode 74 of the peripheral circuit portion are simultaneously formed by photoetching. To do. At this time, the silicon oxide film 73 to be the gate oxide film of the second MIS transistor is formed at the same time as the etching of the gate electrode 74. Next, FIG.
As shown in 0 (f), the second gate electrode 74 is formed by photoetching. At this time, at the same time, the first transfer electrode 5
8 and the silicon nitride film in regions other than the lower portion of the second transfer electrode 60 are removed by self-alignment using these as a mask.

As described above, the film has two kinds of film thickness, that is, the first peripheral circuit portion of 50 nm and the second peripheral circuit portion of 80 nm, the interface state is small, and the trap level in the film is small. A peripheral circuit portion having an optimum gate insulating film is formed for forming the surface channel transistor. Although the silicon oxide films of 50 nm and 80 nm are formed in this embodiment, the oxide film thickness can be arbitrarily changed within the limit of withstand voltage.

Then, after forming an insulating film, aluminum wiring is performed to complete the charge transfer element. Even in the case of an element having three or more layers of gates, the silicon nitride film in the peripheral circuit portion can be similarly removed to form a silicon oxide film. Since the silicon nitride film in the peripheral circuit portion is removed as described above, it is possible to form the MIS transistor in the portion where the influence of the interface state is small. Therefore, the threshold voltage V _th is not degraded by the stress.

Further, since the gate insulating film of the peripheral circuit portion is simultaneously formed in the charge transfer portion whose upper surface is the silicon nitride film, the process is simple and the film thickness of the gate insulating film can be changed according to the purpose. Furthermore, the first transfer electrode of the charge transfer section and the gate electrode of the peripheral circuit section can be formed by self-alignment, which facilitates the process.

Furthermore, when the gate insulating film of the peripheral circuit portion is formed, the silicon nitride film is formed in the upper layer of the charge transfer portion. If the gate insulating film is oxidized in this state, the silicon nitride film does not change, that is, only a silicon oxide film of about 5 nm is formed, and the gate insulating film of the peripheral circuit portion can be formed at the same time.

[0130]

According to the present invention, the peripheral circuit portion has a gate electrode formed through a single-layer insulating film, and at least the lower layer of the laminated insulating film has a thickness of 10 nm to 200 n.
m silicon oxide film and the upper layer is a silicon nitride film having a film thickness of 10 nm to 100 nm, a diffusion layer having a predetermined impurity concentration is formed to have a predetermined withstand voltage and transfer. Efficiency and CCD
It is possible to obtain a charge transfer device which is not deteriorated in the saturation characteristic with respect to the signal charge of the channel.

Further, since the insulating film having the above-mentioned film thickness is used as the gate insulating film, the value (φ _L ) on the low voltage side of the driving voltage does not become too low and the transfer efficiency is poor. There is nothing to give down. Further, the value (φ _H ) on the high voltage side of the driving voltage does not become too high, and it is not necessary to make the pulse generator for driving high withstand voltage.

Further, as a result of setting the film thickness as described above, the stability of film formation is good, the reliability of the charge transfer element can be improved, and even if the charge transfer element is used for a long time, C
The effective voltage applied to the CD channel does not change. Further, in the charge transfer device of the present invention, the stress applied to the entire charge transfer device can be reduced by eliminating the silicon nitride film other than under the silicon oxide film. Further, even when this charge transfer element is used as a solid-state image pickup device, since there is no silicon nitride film, light incident on the photodiode is not attenuated.

Since the gate insulating film of the MIS transistor is provided with the silicon oxide film as a single layer, the transistor characteristics are not deteriorated by the interface level and the trap level existing in the insulating film. Therefore, the noise characteristic and the frequency characteristic of the MIS transistor are not deteriorated due to the increase of the interface state density. Further, the threshold voltage V _th of the MIS transistor is not shifted and the mutual conductance g _m is not deteriorated due to the increase of the trap density in the film.

Furthermore, the MIS of the charge transfer device of the present invention.
The transistor has a low amplifier noise and can be suppressed to about 2/5 times that of a conventional MIS transistor having a gate insulating film having a laminated structure. Therefore, when the charge transfer element operates, a minute signal charge can be sufficiently amplified. Further, the frequency characteristics of the MIS transistor of this embodiment can be improved by about 1.4 times as compared with the conventional MIS transistor having a gate insulating film having a laminated structure.

Furthermore, the film thickness of the gate insulating film of the MIS transistor can be set to an optimum value in the peripheral circuit section depending on the application. Therefore, it is possible to easily reduce the size of the device and optimize the device characteristics. Furthermore, since the thickness of the gate insulating film of the MIS transistor can be arbitrarily selected, a transistor that reduces ON resistance at the time of switching to reduce noise and a transistor such as a load transistor that is used only as a resistor are present together. be able to. Therefore, it is not necessary to increase the transconductance g _m or increase the size of the transistor. In addition, it is possible to prevent the high frequency characteristic from being deteriorated due to the increase of the added capacitance.

Further, since the silicon nitride film in the peripheral circuit portion is removed, the MIS is formed in a portion where the influence of the interface state is small.
A transistor can be formed. Therefore, the threshold voltage V _th is not degraded by the stress. Further, in the method of manufacturing a charge transfer device according to the present invention, the gate insulating film of the peripheral circuit portion is simultaneously formed in the charge transfer portion having the silicon nitride film as an upper surface, so that the process is simple and the film thickness of the gate insulating film is Can be changed according to the purpose.

Further, since the first transfer electrode of the charge transfer section and the gate electrode of the peripheral circuit section can be formed by self-alignment, the process is easy. When forming transistors having different purposes in the peripheral circuit section, the gate insulating film of the peripheral circuit, the first transfer electrode of the charge transfer section and the gate electrode of the peripheral circuit section are formed in the charge transfer section by self-alignment. ,
Further, the gate insulating film of the transistor having a different purpose can be formed at the same time as the insulating film for electrically isolating the first transfer electrode. At this time, the gate electrodes and the second transfer electrodes of the transistors having different purposes can be formed at the same time. Therefore, the process is easy.

Further, in the method of manufacturing the charge transfer device according to the present invention, the laminated film of the silicon oxide film and the silicon nitride film is removed to form the gate insulating film of the peripheral circuit portion. Therefore, the process is simpler than the conventional process. further,
When the gate insulating film of the peripheral circuit portion is formed, the silicon nitride film is formed on the upper layer of the charge transfer portion. If the gate insulating film is oxidized in this state, the silicon nitride film does not change, that is, only a silicon oxide film of about 5 nm is formed, and the gate insulating film of the peripheral circuit portion can be formed at the same time.

Therefore, the film thickness of the insulating film immediately below the first transfer electrode and the film thickness of the insulating film immediately below the second transfer electrode become substantially uniform.

[Brief description of drawings]

FIG. 1 is a sectional view of a charge transfer device according to a first embodiment of the present invention.

FIG. 2 is an element cross-sectional view when the charge transfer element according to the first embodiment of the present invention is applied to a solid-state imaging device.

FIG. 3 is a characteristic diagram illustrating an amplifier noise characteristic and a frequency characteristic of the charge transfer device according to the present invention.

FIG. 4 is a sectional view of a charge transfer device according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a charge transfer device according to a third embodiment of the present invention.

FIG. 6 is a plan view of a peripheral portion of a peripheral circuit portion of the charge transfer device according to the present invention.

FIG. 7 is a sectional view of a charge transfer device according to a fourth embodiment of the present invention.

FIG. 8 is a plan view in which the charge transfer device of the present invention is applied to a FIT type CCD solid-state imaging device.

FIG. 9 is a step-by-step cross-sectional view showing the method of manufacturing the charge transfer element according to the first embodiment of the present invention.

FIG. 10 is a step-by-step cross-sectional view showing the method of manufacturing the charge transfer element according to the second embodiment of the present invention.

FIG. 11 is a cross-sectional view of a conventional charge transfer element.

FIG. 12 is a step-by-step cross-sectional view showing the method of manufacturing the conventional charge transfer device.

[Explanation of symbols]

51 Silicon substrate 52 p-type diffusion layer 53 n-type diffusion layer 54 Separation area 55 n-type diffusion layer 56 Silicon oxide film 57 Silicon nitride film 58 transfer electrode 59 Silicon oxide film 60 transfer electrodes 68 Silicon oxide film 69 Gate electrode

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuji Matsuda             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electronics             Industry Co., Ltd.

Claims (10)

[Claims] 1. A charge transfer device comprising a semiconductor substrate on which a charge transfer section and a peripheral circuit section are formed, the charge transfer section having a transfer electrode formed through a laminated insulating film, and the peripheral circuit. Has a gate electrode formed via a single-layer insulating film, and the laminated insulating film has a film thickness of at least 10 n at the lower layer.
A charge transfer device comprising a silicon oxide film of m to 200 nm and an upper layer of a silicon nitride film having a film thickness of 10 to 100 nm. 2. The charge transfer device according to claim 1, wherein a silicon oxide film having a film thickness of 5 nm is formed on the silicon nitride film forming the laminated insulating film. 3. The charge transfer device according to claim 1, wherein the gate insulating films of the plurality of transistors formed in the peripheral circuit portion have different film thicknesses. 4. The charge transfer device according to claim 1, wherein at least a load transistor serving as a resistance is present in the plurality of transistors formed in the peripheral circuit section. 5. A solid-state imaging device having a charge transfer section and a photodiode section formed on a semiconductor substrate, comprising:
The charge transfer section has a transfer electrode formed via a laminated insulating film, the photodiode section has a single-layer insulating film formed on the semiconductor substrate, and the laminated insulating film has at least a lower layer. Composed of silicon oxide film,
A solid-state imaging device, wherein an upper layer is composed of a silicon nitride film, and the single-layer insulating film is composed of a silicon oxide film. 6. A charge transfer device having a charge transfer section and a peripheral circuit section formed on a semiconductor substrate, wherein a rectangular separation region separating the charge transfer section and the peripheral circuit section, and the peripheral circuit section are provided. A region of a single-layer insulating film formed inside the isolation region and with a gap, a gate electrode formed substantially in the center of the region, and on both sides of the gate electrode and in the region. A charge transfer device having a source / drain contact hole provided. 7. The gap is formed from an end of the separation area.
7. The charge transfer device according to claim 6, wherein the charge transfer devices are separated from each other by a distance corresponding to a film thickness of the separation region or more. 8. A step of growing an isolation region in a predetermined region of a main surface of a semiconductor substrate, a step of forming a first silicon oxide film on the semiconductor substrate, and a silicon nitride film on the first silicon oxide film. And a step of removing the silicon nitride film in the first region to be a peripheral circuit section, a step of removing the first silicon oxide film in the first area, and a charge transfer section. Forming a second silicon oxide film on the upper surface of the second region with the entire surface of the silicon nitride film exposed, and forming a first transfer electrode in the first region serving as the charge transfer portion at the same time. Forming a gate electrode of the peripheral circuit portion via the second silicon oxide film, forming a third silicon oxide film by oxidizing the first transfer electrode, and forming a third silicon oxide film. A second transfer charge through the membrane A method of manufacturing a charge transfer device, comprising the step of forming a pole. 9. A method of manufacturing a charge transfer device, wherein the film thickness of a silicon nitride film formed directly below a first transfer electrode and a second transfer electrode is substantially equal. 10. A step of growing an isolation region in a predetermined region of a main surface of a semiconductor substrate, a step of forming a first silicon oxide film on the semiconductor substrate, and a step of forming silicon on the first silicon oxide film. A step of forming a nitride film, a step of removing the silicon nitride film in the first region to be a peripheral circuit portion, a step of removing the first silicon oxide film in the first region, Forming a second silicon oxide film on the upper surface of the second region to be the charge transfer portion with the silicon nitride film exposed to the entire surface; and then performing a first transfer to the second region to be the charge transfer portion. Forming an electrode and forming a first gate electrode in a third region in the first region through the second silicon oxide film at the same time, and then oxidizing the first transfer electrode and at the same time First area A step of forming a third silicon oxide film in a fourth region therein, and then forming a second transfer electrode in the second region which will be the charge transfer portion through the third silicon oxide film. Forming a second gate electrode in the fourth region via the third silicon oxide film.