JPH05315570A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To easily form a fine pattern by a method wherein a photoresist film on a second region is exposed to light and then a photoresist film on a first region is exposed to light when the same wiring is formed on a first and a second region which are different from each other in average surface height. CONSTITUTION:The main parts of a DRAM cell array and a peripheral circuit are formed, then a aluminum film 13 is deposited on an interlayer insulating film 12, a photoresist film 14 is applied thereon, and a photoresist film 14 on a first region 15 where a decoder and the like other than memory cells are formed is selectively exposed to light, and then a photoresist film 14 is exposed to light through a second photomask where only a pattern of a memory cell array region is formed. At this point, the table of a light exposure device where a wafer is held is adjusted in height to enable a second light exposure region 16 to be exposed to light under optimal focal conditions. Thereafter, the photoresist film 14 is developed to remove an exposed part, and a lower aluminum film 13 is etched into an aluminum wiring of required pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for exposing a photoresist film.

[0002]

2. Description of the Related Art FIG. 2 shows a one-transistor / one-capacitor dynamic memory (hereinafter referred to as DRAM
Is a circuit diagram showing a memory cell portion of FIG. The word line W is selected to make the switching transistor Q ₁ conductive, and the data line D is connected to one electrode of the capacitor C _1.
To write data in the form of electric charge, or to read data from the capacitor C ₁ to the data line D.

FIG. 3 is a cross-sectional view showing the actual structure of the memory cell shown in FIG. 2, showing a state of being formed on the P-type silicon substrate 1. The word line is formed by the polycrystalline silicon film 4a extending in one direction and constitutes the gate electrode of the switching transistor. The N-type disordered regions 3a and 3b form the source and drain of the switching transistor, and one N-type impurity region 3b is connected to the data line formed by the silicide film 11. The other N-type irregular region 3a is connected to the polycrystalline silicon film 7 forming one electrode of the capacitor. The polycrystalline silicon film 9 is the other electrode of the capacitor, and the portion where the two polycrystalline silicon films 7 and 9 face each other via the thin insulating film 8 is the actual capacitor. The polycrystalline silicon film 4b constitutes a word line of an adjacent memory cell. Also, aluminum wiring 1
3a and 13b are polycrystalline silicon films 4a and 4b, respectively.
In order to reduce the resistance of the word line constituted by the above, it is provided to connect with the polycrystalline silicon films 4a and 4b below at a predetermined interval. Furthermore, the aluminum wiring 13c is
It is a signal wiring of circuits such as a decoder and a sense amplifier provided outside the memory cell.

In the memory cell of the DRAM shown in FIG. 3, in order to operate the circuit stably, it is necessary to increase the capacitance value of the capacitor of the memory cell and increase the amount of accumulated charges. Examples of the method include a method of thinning the insulating film of the capacitor, a method of using a substance having a large dielectric constant for the insulating film, and a method of increasing the area where the electrodes face each other. Of these, the most commonly used method is the last-mentioned method of increasing the facing area of the electrodes.

FIG. 4 shows a DRA having such a device.
3 is different from that shown in FIG. 3 in the cross-sectional view showing the memory cell of M, the polycrystalline silicon film 7A forming one electrode of the capacitor is formed thick, so that the facing area in the side surface portion can be increased. This is the point that it is made larger. This method is based on the idea that the area occupied by the memory cell is not changed, and the area facing the electrode of the capacitor can be increased in the vertical direction. As a result, the capacitance value of the capacitor can be increased, and the circuit can be operated stably.

[0006]

However, in the conventional memory cell shown in FIG. 4, since the polycrystalline silicon film 7A is formed thick in order to increase the capacitance value of the capacitor, a region where the memory cell is formed is formed. However, the height is higher than the area where peripheral circuits such as the decoder and the sense amplifier are formed, and a large step is generated at the boundary between the two areas. This step difference is 0.5 to 1.5 μm although it varies depending on the thickness of the polycrystalline silicon film 7A.

When it is attempted to form the patterns of the aluminum wirings 13a to 13c, an aluminum film (13 in FIG. 7) is formed on the entire surface, a photoresist is applied, and a photomask is used to select a desired pattern. Exposure. FIG. 5 is a cross-sectional view showing the state after the photoresist film 14 is exposed, and the shaded portion of the photoresist film 14 is the exposed portion 14A.

At this time, since there is a large step between the memory cell area and the surrounding area, it becomes difficult to expose the photoresist under the optimum focus condition in both of the two areas. As a result, there arises a problem that in one region, adjacent patterns are connected at a portion having a small pattern interval, or patterns are cut at a portion having a small width.

[0009]

According to a method of manufacturing a semiconductor memory device of the present invention, a predetermined insulating film on a semiconductor substrate having a first region and a second region having a difference in average surface height is provided. A step of depositing a conductive film for wiring thereon and covering the conductive film for wiring with a photoresist film; and the first (or second)
And the step of selectively exposing the photoresist film on the second (or first) area after the photoresist film on the area is exposed at the time of selection.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

1 (a) and 1 (b) are cross-sectional views showing one embodiment of the present invention in the order of manufacturing steps.

As shown in FIG. 1A, after the main part of the DRAM cell array and the main part of the peripheral circuit are formed as in the conventional example, the aluminum film 13 is formed on the interlayer insulating film 12.
Then, a photoresist film 14 is applied. Then, the photoresist film 14 in the first region 15 (peripheral circuit region) in which the decoder and the sense amplifier other than the memory cells are formed is selectively exposed according to the aluminum pattern. In FIG. 1A, the shaded portion is the exposed portion 14B of the photoresist film 14. At this time, the photomask used for the exposure of the photoresist film 14 is such that the pattern of the first region 15 is formed and the memory cell array region is entirely dark. Then, only the pattern of the memory cell array region is formed, and the first region 15 is entirely a dark part. The photoresist film 14 in the memory cell array region is formed by the second photomask different from the above-described photomask.
To expose. This state is shown in FIG.
At this time, the second exposure region 16 can be exposed under the optimum focus condition by adjusting the height of the table for holding the wafer of the exposure apparatus by the amount that the average height is higher than the surrounding region. To do so. Further, it is preferable that the boundary portion between the first exposure area and the second exposure area be slightly overlapped. Next, the exposed photoresist film is developed to remove the exposed portion, and then the lower aluminum film 13 is etched to form an aluminum wiring having a desired pattern (13a in FIG. 4).
~ 13c) can be formed.

In the above description, the dynamic memory is described, but it is obvious that the present invention can be applied to a static memory or a read-only memory. Also, the order of exposure is not necessarily limited to the order described above.

[0014]

As described above, according to the present invention, the photoresist film applied to the conductive film for wiring deposited on the predetermined interlayer insulating film on the semiconductor substrate is exposed to expose the surface of the semiconductor substrate to an average height. In order to form the wirings of the same layer in the first and second regions having different depths, after exposing the photoresist film in the first (or second) region to the second (or first) region, By exposing the photoresist film in the region, the two regions having different heights can be exposed under the optimum exposure condition, so that the fine pattern can be easily formed.

[Brief description of drawings]

1A to 1C are cross-sectional views in order of the processes, which are illustrated in FIGS.

FIG. 2 is a circuit diagram of a dynamic memory.

FIG. 3 is a cross-sectional view of a conventional dynamic memory.

4 is a cross-sectional view of a dynamic memory obtained by improving the dynamic memory shown in FIG.

FIG. 5 is a cross-sectional view corresponding to one manufacturing process of the conventional dynamic memory shown in FIG.

[Explanation of symbols]

1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4a, 4b Polycrystalline silicon film 5a, 5b N-type impurity region 6 Interlayer insulating film 7, 7A Polycrystalline silicon film (capacitor lower electrode) 8, 8A Insulating film 9, 9A Polycrystalline silicon film (capacitor upper electrode) 10 Interlayer insulating film 11 Silicide film 12 Interlayer insulating film 13 Aluminum film 13a, 13b, 13c Aluminum wiring 14 Photoresist film 14A, 14B, 14C Exposed portion of photoresist film 15 First Area 16 Second area

Claims (2)

[Claims] 1. A conductive film for wiring is deposited on a predetermined insulating film on a semiconductor substrate having a first region and a second region having a difference in average surface height, and the conductive film for wiring is provided. Coating the film with a photoresist film, and the first (or second)
A step of selectively exposing the photoresist film on the second (or first) area after exposing the photoresist film on the area (4) at the time of selection. Method. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the second region is a memory cell array region in which memory cells are arranged in a matrix, and the first region is a peripheral circuit region.