JPH05315499A - Lead frame for semiconductor use - Google Patents
Lead frame for semiconductor useInfo
- Publication number
- JPH05315499A JPH05315499A JP4121909A JP12190992A JPH05315499A JP H05315499 A JPH05315499 A JP H05315499A JP 4121909 A JP4121909 A JP 4121909A JP 12190992 A JP12190992 A JP 12190992A JP H05315499 A JPH05315499 A JP H05315499A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- die pad
- lead frame
- pin portion
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title description 35
- 239000000725 suspension Substances 0.000 description 12
- 239000000463 material Substances 0.000 description 4
- 230000008602 contraction Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Landscapes
- Punching Or Piercing (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体用リードフレー
ムに関し、更に詳しくは、ダイパッド沈め後に発生する
フレーム枠の湾曲変形を防止した半導体用リードフレー
ムに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor lead frame, and more particularly to a semiconductor lead frame that prevents the frame frame from being bent and deformed after the die pad is sunk.
【０００２】[0002]
【従来の技術】従来の半導体用リードフレームを図４〜
図８を参照しながら説明する。従来の半導体用リードフ
レーム１０は、図４に示すように、フレーム枠１１と、
このフレーム枠１１の内部に形成されたダイパッド部１
２と、このダイパッド部１２と上記フレーム枠１１とを
連結する吊りピン部１３とを有している。2. Description of the Related Art A conventional semiconductor lead frame is shown in FIG.
This will be described with reference to FIG. As shown in FIG. 4, the conventional semiconductor lead frame 10 includes a frame 11 and
Die pad portion 1 formed inside the frame 11
2 and a suspension pin portion 13 that connects the die pad portion 12 and the frame frame 11 to each other.
【０００３】而して、上記半導体用リードフレーム１０
にＩＣチップ等を取り付ける際には、図５に示すように
ダイパッド部１２を金型を用いてダイパッド部１２をフ
レーム枠１１よりも沈めてワイヤボンディングをしやす
いようにする。このダイパッド沈めには、同図に示すよ
うに、フレーム枠１１をストリッパー２１で押え、この
状態でパンチ２２とダイ２３でダイパッド部１２を挟ん
でダイパッド部１２を沈めると共に吊りピン部１３を塑
性変形させて、ダイパッド部１２をフレーム枠１１から
所定深さ迄沈めるようにしている。Thus, the semiconductor lead frame 10 is used.
When an IC chip or the like is attached to the die, the die pad portion 12 is sunk into the die pad portion 12 below the frame 11 to facilitate wire bonding as shown in FIG. In this die pad sinking, as shown in the figure, the frame frame 11 is pressed by the stripper 21, and in this state, the die pad portion 12 is sandwiched between the punch 22 and the die 23 to sink the die pad portion 12 and the hanging pin portion 13 is plastically deformed. Thus, the die pad portion 12 is sunk from the frame frame 11 to a predetermined depth.
【０００４】このダイパッド沈め、ＩＣチップの装着及
びＩＣチップのワイヤボンディングの過程を示したもの
が図６で、同図（ａ）に示す平坦な半導体用リードフレ
ーム１０のダイパッド部１２を金型で沈めた後（同図
（ｂ）参照）、このダイパッド部１２にＩＣチップ３０
を接着し（同図（ｃ）参照）、然る後、金線３１によっ
てＩＣチップ３０を金線３１によってワイヤボンディン
グする（同図（ｄ）参照）。FIG. 6 shows the steps of sinking the die pad, mounting the IC chip, and wire bonding the IC chip. The die pad portion 12 of the flat semiconductor lead frame 10 shown in FIG. After being submerged (see FIG. 2B), the IC chip 30 is placed on the die pad portion 12.
Are bonded (see (c) in the figure), and thereafter, the IC chip 30 is wire-bonded with the gold wire 31 (see (d) in the figure).
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、従来の
半導体用リードフレーム１０は、吊りピン部１３が他の
フレーム枠１１及びダイパッド部１２と一体的に形成さ
れ、しかも直線状に形成されているため、ダイパッド沈
め時に吊りピン部１３が伸張して塑性変形させてダイパ
ッド部１２を沈め位置で固定するようにしているが、通
常、この吊りピン部１３はダイパッド沈め後、多少の弾
性回復して収縮し、延いてはフレーム枠１１を引っ張っ
て図７に示すように幅方向の断面形状を弓状に反らせて
しまうという課題があった。尚、図８は図７に示す半導
体用リードフレームの平面図である。However, in the conventional semiconductor lead frame 10, the hanging pin portion 13 is formed integrally with the other frame frame 11 and the die pad portion 12, and is formed linearly. When the die pad is submerged, the suspension pin portion 13 is stretched and plastically deformed to fix the die pad portion 12 at the submerged position. Normally, the suspension pin portion 13 is elastically recovered and contracted after the submersion of the die pad. However, there is a problem that the frame frame 11 is pulled and the cross-sectional shape in the width direction is warped in an arc shape as shown in FIG. 7. 8 is a plan view of the semiconductor lead frame shown in FIG.
【０００６】本発明は、上記課題を解決するためになさ
れたもので、ダイパッド沈めを行なっても反りを生じさ
せることのない半導体用リードフレームを提供すること
を目的としている。The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor lead frame that does not warp even when the die pad is submerged.
【０００７】[0007]
【課題を解決するための手段】本発明の請求項１に記載
の半導体用リードフレームは、ダイパッド沈め時に発生
する吊りピン部の伸張部の収縮力を吸収するクッション
部を上記吊りピン部に設けたものである。The semiconductor lead frame according to claim 1 of the present invention is provided with a cushion portion for absorbing the contracting force of the extension portion of the suspension pin portion generated when the die pad is sunk in the suspension pin portion. It is a thing.
【０００８】また、本発明の請求項２に記載の半導体用
リードフレームは、ダイパッド沈め時に発生する吊りピ
ン部の伸張部の収縮力を吸収するクッション材によって
上記吊りピン部を形成したものである。According to a second aspect of the present invention, the above-mentioned suspension pin portion is formed by a cushion material that absorbs the contracting force of the extension portion of the suspension pin portion that occurs when the die pad is sunk. .
【０００９】[0009]
【作用】請求項１に記載の本発明によれば、金型を用い
てダイパッド沈めを行なって吊りピン部が弾性回復する
ことがあっても、そのクッション部で伸張部の収縮力を
吸収して半導体用フレームを反らせることがない。According to the present invention as set forth in claim 1, even when the die pad is sunk by using a mold to elastically recover the hanging pin portion, the cushion portion absorbs the contracting force of the extension portion. It does not warp the semiconductor frame.
【００１０】また、請求項２に記載の本発明によれば、
金型を用いてダイパッド沈めを行なって吊りピン部が弾
性回復することがあっても、クッション材によって形成
された吊りピン部全体で収縮力を吸収して半導体用フレ
ームを反らせることがない。According to the present invention as set forth in claim 2,
Even if the die pad is submerged by using a mold to elastically recover the suspension pin portion, the entire suspension pin portion formed by the cushion material does not absorb the contraction force and warp the semiconductor frame.
【００１１】[0011]
【実施例】以下、図１〜図３に示す実施例に基づいて本
発明を説明する。尚、図１は本発明の半導体用リードフ
レームの一実施例の要部を拡大してを示す平面図、図２
は本発明の半導体用リードフレームの他の実施例の要部
を拡大してを示す平面図、図３は本発明の更に他の実施
例の要部を拡大してを示す断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the embodiments shown in FIGS. 2 is a plan view showing an enlarged main part of one embodiment of the semiconductor lead frame of the present invention, and FIG.
FIG. 3 is a plan view showing an enlarged essential part of another embodiment of the semiconductor lead frame of the present invention, and FIG. 3 is an enlarged sectional view showing an essential part of still another embodiment of the present invention.
【００１２】本実施例の半導体用リードフレーム５０
は、図１に示すように、フレーム枠５１と、このフレー
ム枠５１の内部に形成されたダイパッド部５２と、この
ダイパッド部５２と上記フレーム枠５１を連結する吊り
ピン部５３とを有して構成されている。A semiconductor lead frame 50 of this embodiment.
As shown in FIG. 1, has a frame frame 51, a die pad part 52 formed inside the frame frame 51, and a hanging pin part 53 connecting the die pad part 52 and the frame frame 51. It is configured.
【００１３】而して、上記吊りピン部５３には、図１に
示すように、ジグザグ状を呈するクッション部５３Ａが
設けられている。そして、上記ダイパッド部５２を金型
によって所定の深さ迄沈める際に、上記吊りピン部５３
が塑性変形しながら伸張し、ダイパッド沈め時の伸張し
た吊りピン部５３が金型を除去した後、この吊りピン部
５３が多少弾性回復しても、この弾性力に起因する収縮
力をジグザグ状のクッション部５３Ａの伸びによって吸
収するように構成されている。As shown in FIG. 1, the hanging pin portion 53 is provided with a zigzag cushion portion 53A. Then, when the die pad portion 52 is sunk to a predetermined depth by a mold, the hanging pin portion 53
Expands while being plastically deformed, and even after the hanging pin portion 53 that has stretched when the die pad is submerged removes the mold, even if the hanging pin portion 53 elastically recovers to some extent, the contracting force due to this elastic force zigzag The cushion portion 53A is configured to absorb the expansion.
【００１４】従って、本実施例によれば、ダイパッド沈
め後に、吊りピン部５３が弾性回復力を保持していて
も、この弾性力による吊りピン部５３の収縮力を当該部
に形成されたクッション部５３Ａで吸収してフレーム枠
５１に発生する張力を消失させてフレーム枠５１を反ら
せることがなく、半導体素子を高精度に製造することが
できる。Therefore, according to this embodiment, even if the hanging pin portion 53 holds the elastic recovery force after the die pad is sunk, the contraction force of the hanging pin portion 53 due to this elastic force is formed in the cushion. The semiconductor element can be manufactured with high accuracy without causing the tension generated in the frame frame 51 absorbed by the portion 53A to disappear and warping the frame frame 51.
【００１５】また、図２は本発明の更に他の実施例の半
導体用リードフレームを示す図で、本実施例の半導体用
リードフレーム６０は、同図に示すように、フレーム枠
６１と、このフレーム枠６１の内部に形成されたダイパ
ッド部６２と、このダイパッド部６２と上記フレーム枠
６１を連結する吊りピン部６３とを有して構成されてい
る。そして、上記吊りピン部６３がダイパッド沈め時に
発生する塑性変形した伸張部に残留する弾性回復力を収
縮力を吸収して伸びる合成樹脂等のクッション材によっ
て形成されている。FIG. 2 is a view showing a semiconductor lead frame of still another embodiment of the present invention. A semiconductor lead frame 60 of the present embodiment, as shown in FIG. It is configured to have a die pad portion 62 formed inside the frame frame 61, and a hanging pin portion 63 connecting the die pad portion 62 and the frame frame 61. The suspension pin portion 63 is formed of a cushion material such as a synthetic resin that absorbs the contraction force and expands the elastic recovery force remaining in the plastically deformed extension portion generated when the die pad is submerged.
【００１６】従って、本実施例によれば、ダイパッド沈
め後に、吊りピン部６３が弾性回復力を保持していて
も、この弾性力による吊りピン部６３の収縮力を吊りピ
ン部５３自体で吸収してフレーム枠６１間に発生する張
力を消失させてフレーム枠６１を反らせることがなく、
半導体素子を高精度に製造することができる。Therefore, according to the present embodiment, even if the hanging pin portion 63 retains the elastic recovery force after the die pad is submerged, the hanging pin portion 53 itself absorbs the contracting force of the hanging pin portion 63 due to this elastic force. Then, the tension generated between the frame frames 61 is eliminated and the frame frames 61 are not warped,
The semiconductor element can be manufactured with high precision.
【００１７】また、図３は本発明の他の実施例における
半導体用フレームのダイパッド沈め後の断面を示してい
る。本実施例の半導体用フレーム７０は、同図に示すよ
うに、ダイパッド沈め時に、吊りピン部７３に階段状を
呈するクッション部７３Ａが形成されている以外は、上
記実施例と同様に構成されている。即ち、本実施例で
は、吊りピン部７３自体は従来と同様に形成されたもの
であっても、ダイパッド沈め時に金型によって階段状を
呈するように吊りピン部７３を成形するようにしたもの
である。FIG. 3 shows a cross section of the semiconductor frame according to another embodiment of the present invention after the die pad is submerged. As shown in the figure, the semiconductor frame 70 of the present embodiment is configured in the same manner as the above-mentioned embodiment, except that the hanging pin portion 73 has a stepped cushion portion 73A when the die pad is sunk. There is. That is, in this embodiment, even if the hanging pin portion 73 itself is formed in the same manner as the conventional one, the hanging pin portion 73 is formed so as to have a stepwise shape by the mold when the die pad is submerged. is there.
【００１８】従って、本実施例によれば、階段状のクッ
ション部７３Ａでダイパッド沈め時に発生した弾性力を
吸収して上記各実施例と同様の作用効果を期することが
できる。Therefore, according to this embodiment, the elastic force generated when the die pad is sunk is absorbed by the stepped cushion portion 73A, and the same effects as those of the above embodiments can be expected.
【００１９】尚、本発明は、上記実施例に何等制限され
るものでなく、吊りピン部が弾性力を吸収するように構
成されたものであれば、本発明に包含される。The present invention is not limited to the above-mentioned embodiments, but any other structure in which the hanging pin portion absorbs the elastic force is included in the present invention.
【００２０】[0020]
【発明の効果】以上説明したように本発明の請求項１に
記載の発明によれば、吊りピン部にクッション部を設け
てダイパッド沈めで吊りピン部に残留する弾性力を吸収
するようにしたので、ダイパッド沈めを行なっても反り
を生じさせることのない半導体用リードフレーを提供す
ることができる。As described above, according to the first aspect of the present invention, the suspension pin portion is provided with the cushion portion so that the elastic force remaining in the suspension pin portion is absorbed when the die pad is submerged. Therefore, it is possible to provide a semiconductor lead frame that does not warp even when the die pad is submerged.
【００２１】また、本発明の請求項２に記載の発明によ
れば、吊りピン部自体をクッション材で形成してダイパ
ッド沈めで吊りピン部に残留する弾性力を吸収するよう
にしたので、ダイパッド沈めを行なっても反りを生じさ
せることのない半導体用リードフレーを提供することが
できる。According to the second aspect of the present invention, since the hanging pin portion itself is formed of a cushioning material to absorb the elastic force remaining in the hanging pin portion when the die pad is submerged, the die pad is used. It is possible to provide a semiconductor lead frame that does not warp even when it is submerged.
【図１】本発明の半導体用リードフレームの一実施例の
要部を拡大してを示す平面図である。FIG. 1 is a plan view showing an enlarged main part of an embodiment of a semiconductor lead frame of the present invention.
【図２】本発明の半導体用リードフレームの他の実施例
の要部を拡大してを示す平面図である。FIG. 2 is a plan view showing an enlarged main part of another embodiment of the semiconductor lead frame of the present invention.
【図３】本発明の半導体用リードフレームの更に他の実
施例の要部を拡大してを示す断面図である。FIG. 3 is a sectional view showing an enlarged main part of still another embodiment of the semiconductor lead frame of the present invention.
【図４】従来の半導体用リードフレームの一例を示す平
面図である。FIG. 4 is a plan view showing an example of a conventional semiconductor lead frame.
【図５】図４に示す半導体用リードフレームのダイパッ
ド沈め動作を示す部分拡大図である。5 is a partial enlarged view showing a die pad submerging operation of the semiconductor lead frame shown in FIG.
【図６】図４に示す半導体用リードフレームにＩＣチッ
プを装着する過程を示す横方向の断面図であり、（ａ）
はダイパッド沈め前の半導体用リードフレームを示す
図、（ｂ）はダイパッド沈め後の半導体用リードフレー
ムを示す図、（ｃ）はダイパッド部にＩＣチップを接着
した状態を示す図、（ｄ）はＩＣチップをワイヤボンデ
ィングした状態を示す図である。6 is a lateral cross-sectional view showing a process of mounting an IC chip on the semiconductor lead frame shown in FIG.
Is a diagram showing the semiconductor lead frame before the die pad is submerged, (b) is a diagram showing the semiconductor lead frame after the die pad is submerged, (c) is a diagram showing a state in which an IC chip is bonded to the die pad portion, and (d) is It is a figure which shows the state which carried out the wire bonding of the IC chip.
【図７】ダイパッド沈めによって従来の半導体用リード
フレームに反りが生じた状態を示す横方向の断面図であ
る。FIG. 7 is a lateral cross-sectional view showing a state in which a conventional semiconductor lead frame is warped due to the die pad sinking.
【図８】図７に示す半導体用リードフレームの正面図で
ある。8 is a front view of the semiconductor lead frame shown in FIG. 7. FIG.
５０、６０、７０ 半導体用リードフレーム ５１、６１、７１ フレーム枠 ５２、６２、７２ ダイパッド部 ５３、６３、７３ 吊りピン部 ５３Ａ、７３Ａ クッション部 50, 60, 70 Lead frame for semiconductor 51, 61, 71 Frame frame 52, 62, 72 Die pad portion 53, 63, 73 Hanging pin portion 53A, 73A Cushion portion
Claims (2)
形成されたダイパッド部と、このダイパッド部と上記フ
レーム枠を連結する吊りピン部とを有する半導体用リー
ドフレームにおいて、ダイパッド部の沈め時に発生する
吊りピン部の伸張部の収縮力を吸収するクッション部を
上記吊りピン部に設けたことを特徴とする半導体用リー
ドフレーム。1. In a semiconductor lead frame having a frame frame, a die pad portion formed inside the frame frame, and a hanging pin portion connecting the die pad portion and the frame frame, it occurs when the die pad portion is submerged. A lead frame for a semiconductor, wherein a cushion portion for absorbing a contracting force of an extension portion of the hanging pin portion is provided on the hanging pin portion.
形成されたダイパッド部と、このダイパッド部と上記フ
レーム枠を連結する吊りピン部とを有する半導体用リー
ドフレームにおいて、ダイパッド部の沈め時に発生する
吊りピン部の伸張部の収縮力を吸収するクッション材に
よって上記吊りピン部を形成したことを特徴とする半導
体用リードフレーム。2. In a semiconductor lead frame having a frame frame, a die pad portion formed inside the frame frame, and a hanging pin portion connecting the die pad portion and the frame frame, it occurs when the die pad portion is submerged. A lead frame for a semiconductor, wherein the hanging pin portion is formed of a cushion material that absorbs the contracting force of the extension portion of the hanging pin portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4121909A JPH05315499A (en) | 1992-05-14 | 1992-05-14 | Lead frame for semiconductor use |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4121909A JPH05315499A (en) | 1992-05-14 | 1992-05-14 | Lead frame for semiconductor use |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05315499A true JPH05315499A (en) | 1993-11-26 |
Family
ID=14822914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4121909A Pending JPH05315499A (en) | 1992-05-14 | 1992-05-14 | Lead frame for semiconductor use |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05315499A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0902473A3 (en) * | 1997-09-09 | 2001-11-21 | Texas Instruments Incorporated | Improvements in or relating to leadframes |
| US6894370B2 (en) | 2001-07-30 | 2005-05-17 | Nec Electronics Corporation | Lead frame and semiconductor device having the same as well as method of resin-molding the same |
| US7187063B2 (en) | 2002-07-29 | 2007-03-06 | Yamaha Corporation | Manufacturing method for magnetic sensor and lead frame therefor |
| JP2013048150A (en) * | 2011-08-29 | 2013-03-07 | Sanken Electric Co Ltd | Semiconductor module and manufacturing method of the same |
| CN114864530A (en) * | 2021-01-20 | 2022-08-05 | 无锡华润安盛科技有限公司 | A lead frame structure and semiconductor device |
-
1992
- 1992-05-14 JP JP4121909A patent/JPH05315499A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0902473A3 (en) * | 1997-09-09 | 2001-11-21 | Texas Instruments Incorporated | Improvements in or relating to leadframes |
| US6894370B2 (en) | 2001-07-30 | 2005-05-17 | Nec Electronics Corporation | Lead frame and semiconductor device having the same as well as method of resin-molding the same |
| US7239009B2 (en) | 2001-07-30 | 2007-07-03 | Nec Corporation | Lead frame and semiconductor device having the same as well as method of resin-molding the same |
| US7187063B2 (en) | 2002-07-29 | 2007-03-06 | Yamaha Corporation | Manufacturing method for magnetic sensor and lead frame therefor |
| US7494838B2 (en) | 2002-07-29 | 2009-02-24 | Yamaha Corporation | Manufacturing method for magnetic sensor and lead frame therefor |
| US7541665B2 (en) | 2002-07-29 | 2009-06-02 | Yamaha Corporation | Lead frame for a magnetic sensor |
| US8138757B2 (en) | 2002-07-29 | 2012-03-20 | Yamaha Corporation | Manufacturing method for magnetic sensor and lead frame therefor |
| JP2013048150A (en) * | 2011-08-29 | 2013-03-07 | Sanken Electric Co Ltd | Semiconductor module and manufacturing method of the same |
| CN114864530A (en) * | 2021-01-20 | 2022-08-05 | 无锡华润安盛科技有限公司 | A lead frame structure and semiconductor device |
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