JPH05315468A - Structure of leadless chip carrier - Google Patents
Structure of leadless chip carrierInfo
- Publication number
- JPH05315468A JPH05315468A JP11555992A JP11555992A JPH05315468A JP H05315468 A JPH05315468 A JP H05315468A JP 11555992 A JP11555992 A JP 11555992A JP 11555992 A JP11555992 A JP 11555992A JP H05315468 A JPH05315468 A JP H05315468A
- Authority
- JP
- Japan
- Prior art keywords
- chip carrier
- organic substrate
- active
- leadless chip
- passive elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000004020 conductor Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 abstract description 9
- 238000000576 coating method Methods 0.000 abstract description 9
- 239000000463 material Substances 0.000 abstract description 8
- 229920003002 synthetic resin Polymers 0.000 abstract description 6
- 239000000057 synthetic resin Substances 0.000 abstract description 6
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract 2
- 239000002184 metal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はリードレスチップキャリ
アの構造に関し、特に高周波対応用としてシールド効果
を高めるリードレスチップキャリアの構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a leadless chip carrier, and more particularly to a structure of a leadless chip carrier for improving a shield effect for high frequency.
【０００２】[0002]
【従来の技術】従来のリードレスチップキャリアは、あ
らかじめ配線パターンが形成された有機基板にざぐり加
工をした配線基板（以下、有機基板と記す）に能動素子
及び受動素子（以下、能動及び受動素子と記す）を搭載
した構造となっている。2. Description of the Related Art A conventional leadless chip carrier is an active element and a passive element (hereinafter, active and passive element) formed on a wiring board (hereinafter, referred to as an organic board) which is formed by counterboring an organic board on which a wiring pattern is formed in advance. It is a structure equipped with.
【０００３】図３は従来のリードレスチップキャリアの
一例の断面図である。FIG. 3 is a sectional view of an example of a conventional leadless chip carrier.
【０００４】図３に示すように有機基板１の中央ざぐり
部分に接着剤２を介して能動及び受動素子３を搭載し、
能動及び受動素子３と有機基板１の配線パターン８との
間を金属細線４で接続し、合成樹脂などのコーティング
材５にて外装の一部を形成している。As shown in FIG. 3, the active and passive elements 3 are mounted on the central counterbore of the organic substrate 1 via the adhesive 2.
The active and passive elements 3 and the wiring pattern 8 of the organic substrate 1 are connected by metal thin wires 4, and a part of the exterior is formed by a coating material 5 such as synthetic resin.
【０００５】[0005]
【発明が解決しようとする課題】上述した従来の技術に
よるリードレスチップキャリアの構造は、図３に示す通
り、能動及び受動素子３の上下の面が合成樹脂等のコー
ティング材５及び有機基板１で封止されているので、外
部からの電磁気の影響を受けやすい構造であるという問
題点があった。In the structure of the leadless chip carrier according to the above-mentioned conventional technique, as shown in FIG. 3, the upper and lower surfaces of the active and passive elements 3 are the coating material 5 such as synthetic resin and the organic substrate 1. Since it is sealed with, there is a problem that the structure is easily affected by electromagnetic waves from the outside.
【０００６】本発明の目的は、外部からの電磁気の影響
を受けにくいリードレスチップキャリアの構造を提供す
ることにある。An object of the present invention is to provide a structure of a leadless chip carrier which is less likely to be affected by electromagnetic waves from the outside.
【０００７】[0007]
【課題を解決するための手段】本発明のリードレスチッ
プキャリアの構造は、あらかじめ配線パターンが形成さ
れた有機基板に少くとも１個の回路素子を搭載し該回路
素子を二重の異なる樹脂で封止し、前記回路素子に直接
接触しない方の外側の前記樹脂を導電性物質にて形成す
る。The structure of the leadless chip carrier of the present invention is such that at least one circuit element is mounted on an organic substrate on which a wiring pattern is formed in advance, and the circuit element is made of a double different resin. The resin is formed of a conductive material on the outer side that is sealed and does not come into direct contact with the circuit element.
【０００８】さらに、前記有機基板の回路素子搭載面と
反対側の裏面に導電性物質を形成している。Further, a conductive material is formed on the back surface of the organic substrate opposite to the circuit element mounting surface.
【０００９】[0009]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１０】図１（ａ），（ｂ）は本発明の第１の実施
例の平面図およびそのＡ−Ａ′線断面図である。1A and 1B are a plan view and a sectional view taken along the line AA 'of the first embodiment of the present invention.
【００１１】第１の実施例は、図１（ａ），（ｂ）に示
すように、能動及び受動素子３を搭載し、金属細線４で
接続した有機基板１に、合成樹脂などのコーティング材
５にて、能動及び受動素子３をコーティングしその上面
に導電性物質６を印刷する。又、有機基板１の能動及び
受動素子搭載面と反対側の裏面にも導電性物質６を印刷
して構成する。In the first embodiment, as shown in FIGS. 1 (a) and 1 (b), a coating material such as synthetic resin is applied to an organic substrate 1 on which active and passive elements 3 are mounted and which are connected by metal wires 4. At 5, the active and passive elements 3 are coated and a conductive material 6 is printed on top of it. Further, the conductive material 6 is also printed on the back surface of the organic substrate 1 opposite to the active and passive element mounting surface.
【００１２】図２は本発明の第２の実施例の断面図であ
る。FIG. 2 is a sectional view of the second embodiment of the present invention.
【００１３】第２の実施例は、図２に示すように、図１
の第１の実施例と同じ構造を用いる。第２実施例の特徴
は、導電性のシール７を合成樹脂などのコーティング材
５の上面に貼ると同時に、有機基板１の裏面にも導電性
シール７を貼ることにより構成する。In the second embodiment, as shown in FIG.
The same structure as in the first embodiment is used. The feature of the second embodiment is that the conductive seal 7 is attached to the upper surface of the coating material 5 such as a synthetic resin, and at the same time, the conductive seal 7 is attached to the back surface of the organic substrate 1.
【００１４】[0014]
【発明の効果】以上説明したように本発明は、リードレ
スチップキャリア内部に搭載された能動及び受動素子に
対して、合成樹脂コーティング材の表面及び有機基板の
裏面に導電性物質を塗布する構造にしたので、従来の構
造に対し、外部からの電磁気の影響を受けにくくし、信
頼性を向上させる効果がある。As described above, according to the present invention, the active and passive elements mounted inside the leadless chip carrier are coated with the conductive material on the surface of the synthetic resin coating material and the back surface of the organic substrate. Therefore, it has an effect of improving the reliability by making the structure less susceptible to the influence of electromagnetic waves from the outside as compared with the conventional structure.
【図１】本発明の第１の実施例の平面図及びそのＡ−
Ａ′線断面図である。FIG. 1 is a plan view of the first embodiment of the present invention and its A-
It is an A'line sectional view.
【図２】本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.
【図３】従来のリードレスチップキャリアの一例の断面
図である。FIG. 3 is a sectional view of an example of a conventional leadless chip carrier.
１ 有機基板 ２ 接着剤 ３ 能動及び受動素子 ４ 金属細線 ５ コーティング材 ６ 導電性物質 ７ 導電性シール ８ 配線パターン 1 Organic Substrate 2 Adhesive 3 Active and Passive Elements 4 Thin Metal Wire 5 Coating Material 6 Conductive Material 7 Conductive Seal 8 Wiring Pattern
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/31 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/31
Claims (2)
機基板に少くとも１個の回路素子を搭載し該回路素子を
二重の異なる樹脂で封止し、前記回路素子に直接接触し
ない方の外側の前記樹脂を導電性物質にて形成した事を
特徴とするリードレスチップキャリアの構造。1. At least one circuit element is mounted on an organic substrate on which a wiring pattern is preliminarily formed, and the circuit element is sealed with a double different resin. A structure of a leadless chip carrier, characterized in that the resin is formed of a conductive material.
の裏面に導電性物質を形成した事を特徴とする請求項１
記載のリードレスチップキャリアの構造。2. A conductive material is formed on the back surface of the organic substrate opposite to the circuit element mounting surface.
The structure of the leadless chip carrier described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11555992A JPH05315468A (en) | 1992-05-08 | 1992-05-08 | Structure of leadless chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11555992A JPH05315468A (en) | 1992-05-08 | 1992-05-08 | Structure of leadless chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05315468A true JPH05315468A (en) | 1993-11-26 |
Family
ID=14665541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11555992A Withdrawn JPH05315468A (en) | 1992-05-08 | 1992-05-08 | Structure of leadless chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05315468A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08186189A (en) * | 1994-12-29 | 1996-07-16 | Toray Dow Corning Silicone Co Ltd | Semiconductor device and its manufacture |
| JPH0997854A (en) * | 1995-09-29 | 1997-04-08 | Nec Corp | Semiconductor device |
| JP2001083174A (en) * | 1999-09-14 | 2001-03-30 | Matsushita Electric Ind Co Ltd | Acceleration sensor |
| JP2006310433A (en) * | 2005-04-27 | 2006-11-09 | Kyocera Corp | Electronic component storage container |
-
1992
- 1992-05-08 JP JP11555992A patent/JPH05315468A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08186189A (en) * | 1994-12-29 | 1996-07-16 | Toray Dow Corning Silicone Co Ltd | Semiconductor device and its manufacture |
| JPH0997854A (en) * | 1995-09-29 | 1997-04-08 | Nec Corp | Semiconductor device |
| JP2001083174A (en) * | 1999-09-14 | 2001-03-30 | Matsushita Electric Ind Co Ltd | Acceleration sensor |
| JP2006310433A (en) * | 2005-04-27 | 2006-11-09 | Kyocera Corp | Electronic component storage container |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990803 |