JPH05314766A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce current consumption by holding a BLI signal to a fixed level while refreshing continuously the memory cell of a cross point between one side of two sets of bit line pairs connected to a sense amplifier and plural word lines at every word line. CONSTITUTION:By a row address judging circuit 5, /CAS before /RAS is entered to a self refresh mode by the signal from an inside row address generation circuit 2. At this time, by the circuit 5, a matter that the memory cell of the cross point between one side of two sets of bit line pairs connected to the sense amplifier and plural intersecting word lines is refreshed continuously at every word line is judged. In such a case, by the circuit 5, the signal holding the BLI signal supplied to the nch transistor of the bit line pair to a Vcc+alpha or GND level constantly to a BLI signal generation circuit 6. Thus, current consumption while refreshing is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which consumes less power during refreshing.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a structure of a conventional semiconductor memory device. In the figure, 1 is a / CAS before / RAS refresh determination circuit, 2 is an internal row address generation circuit, 3 is a timer, and 4 is a timer. Is an internal / RAS generation circuit, 6 is a bit line selection signal generation circuit (hereinafter referred to as BLI signal generation circuit), 7a to 7f are sense amplifiers, 8 is a row decoder, and 9a to 9d are bit line selection signals (hereinafter, A signal line for transmitting a BLI signal), 10a to 10d are word lines, 11a to 11p are bit lines, 12a to 12p are memory cells, and 13a to 13p are nch transistors functioning as switching transistors. Here, two predetermined pairs of bit line pairs are connected to the sense amplifiers 7a to 7f through switching transistors 13a to 13p, and the bit lines 11a to 11p and the word lines 10a to 10d are connected to each other. Memory cells 12a to 12p connected to these are formed at the intersecting positions.

FIG. 5 is a circuit diagram of the semiconductor memory device of FIG.
7 is a timing chart showing an operation in a CAS before / RAS refresh mode, and FIG. 6 is a timing chart showing an operation in a self refresh mode.

Next, the operation will be described. First, / C
The operation in the AS before / RAS refresh mode will be described.

After the standby state in which both / RAS and / CAS are High and before / RAS becomes Low level when / CAS becomes Low level, they are received / C
AS before / RAS refresh determination circuit 1 is / CA
Detects that S-before / RAS refresh mode has been entered. Next, the internal row address generation circuit 2 outputs
An internal address is generated in response to a signal from CAS before / RAS refresh determination circuit 1, and this internal row address is input to row decoder 8 and BLI generation circuit 6. Then, the row decoder 8 receiving the internal row address selects a predetermined word line, for example, the word line (W0) 10a, changes the selected word line (W0) 10a from the GND level to the High level, and The unselected word lines (W1) 10b, (W2) 10c, (W3) 10e are held at the GND level. On the other hand, the BLI generating circuit 6 which has received the internal row address causes the memory cells 12a to 12a connected to the selected word line (W0) 10a.
2d is connected to the sense amplifiers 7a to 7d.
The LI signals BLI0 and BLI1 are changed from the precharge level to the (Vcc + α) level, and the memory cells 12e to p connected to the unselected word lines (W1) 10b, (W2) 10c and (W3) 10d are connected to the sense amplifier 7c.
BLI signals BLI2, B so that they are not connected to ~ 7f
LI3 is changed from the precharge level to the GND level, and as a result, only the memory cells 12a to 12d connected to the word line (W0) 10a are refreshed. And
After that, when / RAS changes from the Low level to the High level, the selected word line (W0) 10a returns to the GND level, and the BLI signals BLI0, BLI01 and BL are generated.
The I signals BLI2 and BLI3 are returned to the precharge level.

Next, when / RAS is again set to low level while holding / CAS at low level, internal row address generation circuit 2 generates the next internal row address, and row decoder 8 causes word line (W1). 10b is selected, and from the BLI generation circuit 6, the nch transistors 13a to 13a ...
The BLI signals BLI0 and BLI1 given to h are changed from the precharge level to (Vcc + α) level, the BLI signals BLI2 and BLI3 given to the nch transistors 13i to 13p from the BLI generation circuit 6 are changed from the precharge level to the GND level, and the word line ( The memory cells 12e to 12h connected to W1) 10b are refreshed as described above.

Next, / RAS is changed from Low level to High level.
When the / RAS is further set to the low level after the signal is set to the h level, the internal row address generation circuit 2 further generates the next internal row address, and the row decoder 8 which receives this generates the word line (W2) in the same manner as described above. ) 10c, the BLI generation circuit 6 changes the BLI signals BLI0 and BLI1 from the precharge level to the GND level, and the BLI signals BLI2 and BLI2.
By setting LI3 from the precharge level to the (Vcc + α) level, the memory cells 12i to 12l connected to the word line (W2) 10c are refreshed.

As described above, in the / CAS before / RAS refresh mode, / RAS is set to the low level while / CAS is kept at the low level.
The memory cells 12a to 12p connected to the word lines W0 to W3 can be sequentially refreshed for each word line until S is set to the high level.

Next, the operation of the self refresh mode will be described. After / RAS and / CAS are in the high-level standby state, / CAS becomes the low level before / RAS becomes the low level, and then / RAS,
When / CAS is at the Low level for the time set by the timer 3, the self-refresh mode is entered, the internal / RAS generation circuit 4 generates the internal / RAS signal, and the internal row address generation circuit 2 outputs the internal address. Then, the same operation as the above-mentioned / CAS before / RAS refresh mode is performed.

[0010]

The conventional semiconductor memory device is configured as described above, and is / CAS before / R.
By the AS refresh mode (or self refresh mode), / CAS is kept at the Low level,
By setting RAS to Low level, / CAS becomes H
Word line (W0 to W3) 10 until high level
The memory cells 12a to 12p connected to a to 10d are refreshed one after another for each word line.

However, as described above, while refreshing the memory cells connected to the word line one after another for each word line, / RAS (or internal / RAS) becomes High.
When the h level changes to the low level, the BLI signal generated from the BLI generation circuit 6 changes from the precharge level to the (Vcc + α) level or the GND level, and / RA
S (or internal / RAS) goes from Low level to High
When the level is reached, BL generated from the BLI generation circuit 6
Since the I signal changes from the (Vcc + α) level or the GND level to the precharge level, there is a problem that the charging / discharging current due to the BLI signal at this time is large and the current consumption naturally increases.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor memory device in which current consumption is reduced in the / CAS before / RAS refresh mode and the self refresh mode. And

[0013]

A semiconductor memory device according to the present invention is arranged at an intersection of one bit line pair of two bit line pairs connected to a sense amplifier and a plurality of word lines. The BL provided to the switching transistor of the bit line pair while the refreshed memory cell is continuously refreshed for each word line among the plurality of word lines.
The I signal is kept constant at (Vcc + α) level or GND level.

[0014]

In the present invention, / CAS before / RA
In the S refresh mode and the self-refresh mode, while the memory cells arranged at the intersections of the pair of bit lines and the plurality of word lines are continuously refreshed for each word line between the plurality of word lines, the pair of Since the level of the BLI signal applied to the switching transistor of the bit line is kept constant, the charge / discharge current due to the BLI signal can be reduced, and the current consumption in the / CAS before / RAS refresh mode and the self refresh mode can be reduced. Can be reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 4 denote the same or corresponding parts. In this semiconductor memory device, internal row address generation is performed. When the internal row address signal generated from the internal row address generation circuit 2 is determined between the circuit 2 and the BLI generation circuit 6 and it is determined that two word lines intersecting the bit line pair are continuously addressed. To
The BLI signal generated from the BLI generation circuit 6 is not returned to the precharge level, that is, (V
BL to hold at cc + α) level or GND level
A row address determination circuit for giving a signal to the I generation circuit 6 is provided.

FIG. 2 is a timing chart showing the operation timing in the / CAS before / RAS refresh mode in the semiconductor memory device shown in FIG.
FIG. 3 is a timing chart showing the operation timing in the self refresh mode.

Next, the operation will be described. First, / CA
The operation in the S-before / RAS refresh mode will be described. After / RAS and / CAS are both in the high level standby state and before / RAS is in the low level and / CAS is in the low level, / CAS is before /
RAS refresh determination circuit 1 is / CAS before / R
It detects that the AS refresh mode has been entered. Next, internal row address generation circuit 2 generates an internal row address, and this internal row address is input to row decoder 8 and row address determination circuit 5. Then, the row decoder 8 selects a predetermined word line, for example, the word line (W0) 10a, changes the selected word line (W0) 10a from the GND level to the High level, and the other word line (W1) 1
0b, (W2) 10c, and (W3) 10d are kept at the GND level. On the other hand, the row address judging circuit 5 which has received the internal row address, after judging the address state of this internal row address, supplies an address signal to the BLI generating circuit 6 and connects it to the selected word line (W0) 10a. The memory cells 12a to 12d are connected to the sense amplifier 7a to
unselected word line (W1) 10 connected to d
b, (W2) 10c and (W3) 10d so that the memory cells 12e to p connected to the sense amplifiers 7c to 7f are not connected to the bit lines 11a connecting the memory cells 12a to 12da and the sense amplifiers 7a to 7f. ~ 11
Each nch transistor 13 provided for p
A BLI signal having a predetermined signal level is generated in a to p. At this time, B given to the nch transistors 13a to 13h
The LI signals BLI0 and BLI1 change from the precharge level to the (Vcc + α) level, and the nch transistor 13i
BLI signals BLI2 and BLI3 given to ~ 13p
Changes from the precharge level to the GND level.

Next, / CAS remains at the low level,
When RAS changes from low level to high level, the memory cell connected to the next word line is refreshed, and the row address determination circuit 5 receiving the internal row address signal from the internal row address generation circuit 2 refreshes the next refresh. The corresponding word line of the memory cell to be executed is the word line (W
1) When 10b detects that the memory cell is in the same block as the refreshed word line (W0) 10a (that is, the memory cell is connected to the sense amplifier by the same bit line pair), the row is detected. The address determination circuit 5 sends a signal for holding the signal level of the BLI signal as it is to the BLI signal generation circuit 6, and as a result,
The selected word line (W0) 10a is returned to the GND level, but the BLI signal is kept at the same signal level, that is, the BLI signals BLI0 and BLI1 are (Vcc +
α) level, and the BLI signals BLI2 and BLI3
Remains at the GND level. Then, in this state, the word line (W0) 10a becomes H level by the internal row address.
From high level to GND level, word line (W1) 1
0b is changed from GND level to High level, and (W
2) 10c and (W3) 10d are kept at the GND level, and the memory cells 12e to 12h connected to the word line (W1) 10b are refreshed.

Next, / RAS is changed from Low level to High level.
When set to the h level, the word line (W1) 10b becomes the GND level, the address determination circuit 5 determines the internal row address generated from the internal row address generation circuit 2, and the word line to which the memory cell to be refreshed next is connected. When it is detected that the word line (W2) 10c is a different block from the word line (W1) 10a, the address determination circuit 5
Sends a signal for returning the BLI signal to the precharge level to the BLI generation circuit 6 so that the BLI signals BLI0 and BLI1 change from the (Vcc + α) level to the precharge, and the BLI signal B.
LI2 and BLI3 are returned from the GND level to the precharge level. Then, when / RAS is changed from the high level to the low level, the internal row address generation circuit 2
The next row address is generated, and the row decoder 8 receiving this selects the word line (W2) 10c, the BLI generation circuit 6 changes the BLI signals BLI0 and BLI1 from the precharge level to the GND level, and the BLI signals BLI2 and BLI3. From the precharge level to the (Vcc + α) level. As a result, the memory cells 12i to 12l connected to the word line (W2) 10c are refreshed.

Next, / RAS changes from Low level to High level.
At the h level, the word line (W2) 10c becomes High.
From the level to the GND level, and the row address detection circuit 5
Detects that the corresponding word line of the memory cells 12n to 12p to be refreshed next is the word line (W3) 10d and is in the same block as the word line (W2) 10c, the row address detection circuit 5 outputs the BLI. Generation circuit 6
Since a signal for holding the signal level of the BLI signal as it is is sent to BLI signals BLI0 and BLI1, the BLI signals BLI0 and BLI2 are held at the (Vcc + α) level and selected by the row decoder 8. Word line (W3) that has become a high level
The memory cells 12n to 12p connected to 10d are refreshed.

Next, the operation of the self refresh mode will be described. After / RAS and / CAS are at the high level in the standby state, / CAS becomes the low level before / RAS becomes the low level, and then / RAS,
When / CAS is at the Low level for the time set by the timer 3, the self-refresh mode is entered, the internal / RAS generation circuit 4 generates the internal / RAS signal, and the internal row address generation circuit 2 outputs the internal row address. Then, the operation similar to that in the / CAS before / RAS refresh mode is performed.

In such a semiconductor memory device of this embodiment, the row address determination circuit 5 is provided between the internal row address generation circuit 2 and the BLI generation circuit 6, and / CAS is used.
In the before / RAS refresh mode and the self-refresh mode, the row address determination circuit 5 is provided at an intersection with a plurality of word lines intersecting one bit line pair of the two pairs of bit lines connected to the sense amplifier. When it is determined that the arranged memory cells are continuously refreshed for each word line among a plurality of word lines, the row address determination circuit 5 informs the BLI generation circuit 6 of the bit line pair. Since a signal for keeping the BLI signal given to the nch transistor at a constant level (Vcc + α) or GND is sent, during this refresh
The charge / discharge current due to the BLI signal can be reduced,
As a result, it is possible to reduce current consumption in the / CAS before / RAS refresh mode and the self refresh mode.

[0023]

As described above, according to the present invention, one of the two bit line pairs connected to the sense amplifier is arranged at the intersection of a plurality of word lines. While the memory cell is continuously refreshed for each word line among the plurality of word lines, the BLI signal applied to the switching transistor of the bit line pair is (Vcc +
Since it is kept constant at the α) level or the GND level, the charging / discharging current due to the BLI signal is reduced in the / CAS before / RAS refresh mode and the self refresh mode, and the current consumption of the device can be reduced. There is.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is an operation timing chart in the / CAS before / RAS refresh mode in the semiconductor memory device of FIG.

FIG. 3 is an operation timing chart in the self-refresh mode in the semiconductor memory device of FIG.

FIG. 4 is a circuit diagram showing a circuit configuration of a conventional semiconductor memory device.

5 is an operation timing chart in the / CAS before / RAS refresh mode in the semiconductor memory device of FIG.

6 is an operation timing chart in the self-refresh mode in the semiconductor memory device of FIG.

[Explanation of symbols]

 1 / CAS before / RAS refresh determination circuit 2 internal row address generation circuit 3 timer 4 internal / RAS generation circuit 5 row address determination circuit 6 BLI generation circuit 7a to 7f sense amplifier 8 row decoder 9a to 9d signal line for transmitting BLI signal 10a -10d Word line 11a-11p Bit line 12a-12p Memory cell 13a-13p nch transistor BIL0-BIL4 BIL signal

Claims (3)

[Claims] 1. A pair of bit line pairs are shared by one sense amplifier, and switching of a switching transistor interposed between each bit line and the sense amplifier causes the above-mentioned 2 to occur.
In a semiconductor memory device having a pair of bit line pairs, a pair of bit line pairs are connected to the sense amplifier, the semiconductor memory device comprising: / CAS before / RAS refresh mode and self refresh mode. While the memory cells on the two word lines intersecting the pair are continuously refreshed for each word line, the signal level of the bit line selection signal input to the gate of the switching transistor corresponding to the one bit line pair is A semiconductor memory device characterized by being maintained constant. 2. A pair of bit line pairs are shared by one sense amplifier, and a sensed sense amplifier having a switching transistor interposed between each bit line and the sense amplifier, and a / CSA before / RAS refresh determination circuit. An internal row address generation circuit that receives an output and generates an internal row address, and a row decoder that selectively sets a predetermined word line to a high level from a plurality of word lines at the GND level based on the internal row address. Of the two bit line pairs connected to the memory cell so that the memory cell connected to the high-level word line is connected to the sense amplifier based on the internal row address. The switching transistor of one bit line pair is
In a semiconductor memory device including a bit line selection signal generation circuit for giving a signal for setting to an N state, an address state of the internal row address is determined between the internal row address generation circuit and the bit line selection signal generation circuit. In the / CAS before / RAS refresh mode, the row address determination circuit continuously connects two word lines intersecting one bit line pair of the two bit line pairs. When it is determined to address, a signal for holding the signal level of the bit line selection signal generated from the bit line selection signal generation circuit constant is given from the row address determination circuit to the bit line selection signal generation circuit. A semiconductor memory device characterized by the above. 3. The semiconductor memory device according to claim 2, wherein the timer circuit sets a self refresh mode based on the output of the / CSA before / RAS refresh determination circuit, and the output of the timer circuit. And a internal / RAS signal generation circuit for supplying an internal / RAS signal to the internal row address generation circuit.