JPH05313861A - Kaihei arithmetic unit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a square root arithmetic unit that does not reduce performance while reducing the hardware scale of the multiplier. [Structure] The approximate reciprocal of the square root is indexed from the table information storage means 8 by using the higher order of the 2-bit-normalized operand output from the normalization means 7 as an address, and the 0th remainder is used as the normalization operand. The output of the means 10 is multiplied by the approximate reciprocal of the square root by the multiplication means 11 to obtain a partial square root, and the partial square roots in each iteration are merged by the digit aligning means 20 and the adding means 21, and the inverting means 15, the multiplicand generating means 16, The (R + S × T) computing means 17 obtains the remainder in the next step of the iterative calculation by subtracting the product of the merged square root and the partial square root from the remainder. Moreover,
The output of the multiplying means 11 is rounded by one bit less than the least significant bit of the partial square root.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a square root calculating device in a data processing device.

[0002]

2. Description of the Related Art Conventionally, in the square root arithmetic unit, Newton
In many cases, square root calculation is executed using the Rapson method.
To obtain the square root of the numerical value A, first find 1 / √A,
Multiply it by A to obtain √A. In the Newton-Raphson method, 1 / √A is calculated by the convergence calculation.
The number of iterations required for convergence is smaller as the initial value of the reciprocal is closer to the true value, and in a high-speed square root calculation device, it can be obtained by convergence calculation of about 3 to 4 times.
No. 24, or U.S. Pat. No. 4,998,801 related to the above publication.

Also, unlike the Newton-Raphson method, there is a square root calculation device that employs a method similar to square root calculation by handwriting. The method is to iteratively calculate the square root in order from the top every time by the same number of digits, and the open number is the initial (0th) partial remainder, and the i-th partial remainder and the first From the i-th partial square root to the i + 1-th partial square root
The product is calculated by adding the i + 1th partial square root to twice the partial square root up to the i th, and taking the i + 1 th partial square root as a multiplier to obtain the product, and subtracting the product from the i th partial remainder And An example of a square root computing device using this method is described in P. Montuschi and L.A.
"On the Effic" by Ciminiera
ient Implementation of Hi
gher Radix SquareRoot Alg
orithms, "Proc. 9th IEEE Sy
mposium on Computer Arith
metic, pp. 154-161, Septembe
r 1989.

[0004]

However, in the above Kaihei arithmetic unit based on the Newton-Raphson method, the mantissa part of the floating-point number input operand is input to the multiplier as the multiplicand and the multiplier, and the double precision floating of the IEEE standard is used. When obtaining the square root of the decimal point number, 53 bits corresponding to the bit length of the mantissa part with leading bits added
Requires a 53-bit multiplier. There is no problem if the multiplier for executing the multiplication instruction is not used at the same time for executing the multiplication instruction and the square root operation instruction, and is also used for executing the square root operation instruction. However, when there is no dependency on the data used between the multiplication instruction and the square root operation instruction, it is hardware to provide a 53-bit × 53-bit multiplier for the square root operation in order to execute two instructions at the same time. However, this is a problem because the quantity of the product increases significantly.

In addition, P. Montuschi and L.A. Ci
In the example of miniera, the number of digits that can be obtained in one iterative calculation is 2 bits. To obtain the square root of a double-precision floating point number of the IEEE standard, guard bits and round bits are added to 53 bits of the mantissa part. It requires 28 times of iterative calculation to obtain the square root of a bit, which is not suitable for high-speed square root calculation.

In view of the above problems, the present invention uses a multiplier having a bit length of a multiplier smaller than the operand length in the case of a fixed point number and the mantissa part in the case of a floating point number, but at a high speed. The present invention provides a square root calculation device for obtaining a square root.

[0007]

In order to solve the above problems, a square root arithmetic unit according to the present invention has a table information storing means for indexing an approximate reciprocal of a square root with respect to an input operand, and a square root having a constant value in order from a higher order. A remainder holding means for holding a remainder when iteratively obtaining the number of bits and a remainder output from the remainder holding means and an approximate reciprocal of a square root output from the table information storage means are multiplied as a multiplicand and a multiplier, respectively. And a merged square root holding means for holding a merged square root obtained by merging the square roots in each iteration with the upper part of the product output by the multiplying means as a partial square root, and output from the merged square root holding means. In addition to the multiplicand generating means for generating as a multiplicand the data obtained by collecting the merged square root and the square root output from the multiplying means, It is obtained by a further comprising a computing means having ability. That is, the computing means outputs the remainder (R) output by the remainder holding means, the multiplicand (S) output by the multiplicand generating means, and the partial square root (T) output by the multiplying means.
And (R−S × T) are calculated by inputting each and.

In addition, in the present invention, in order to improve the operation speed, the upper part of the product output from the multiplication means or the (RS-T) operation means is input and the bit is smaller than the least significant bit of the partial square root by one bit. An adding means for calculating a partial square root is provided for rounding.

[0009]

Before explaining that the square root calculation can be executed by the above-mentioned structure, the square root calculation method used in the present invention will be described. The square root processing of the exponent part of the floating point number is easy, and will be described in the embodiment of the present invention described later.
Here, the mantissa part of a floating-point number or square root of a positive fixed-point number will be described. The numerical value A is subjected to normalization in units of 2 bits and satisfies (Equation 1). (Equation 1) 2 ^-2 ≤ A <1

The square root of A is divided into groups by a certain number n of bits from the higher order and expressed as (Equation 2). At this time, a _ij is 0 or 1, and especially a ₁₁ is 1 from (Equation 1). (Equation 2) √A = a ₁ + a ₂ + a ₃ + a ₄ + a ₅ + ... (a _i = 2 ^-in (a _i1.2n ^-1 + a _i2 / ^2n-2 + ... ^{_{· + a in · 2 0)}} )

On the contrary, by squaring the sides of (Equation 2) (Equation 3)
To get (Equation 3) A = (a ₁ + a ₂ + a ₃ + a ₄ + a ₅ + ...) ²

It is assumed that the approximate reciprocal of the square root of A is M, and the precision of M satisfies the condition of (Equation 4). (Equation 4) | √AM-1 | ≤ 2- ^{(n + 1)}

At this time, the square root can be obtained by the following procedure, and (Equation 4) is a sufficient condition for obtaining the partial square root by n bits. (1) A ( _denoted as R ₀ ) is multiplied by M, and the constant number n of high-order bits of the result is taken as b ₁ . (2) After calculating R ₁ = R ₀ −b ₁ × b ₁ , shift R ₁ to the left by the constant number of bits n in (1). Hereinafter, (3) and (4) are repeated as many times as necessary. (3) R _i is multiplied by M, and a fixed number of high-order bits of the result n
Let +1 be b _{i + 1} . However, as compared with b ₁ in (1), b _{i + 1} is taken from the upper one bit, and as a correction to b _i , an extra one bit is taken to the upper bit. (4) R _{i + 1} = R _i − {(b ₁ + ... + b _i ) × 2 +
After calculating b _{i + 1} } × b _{i + 1} , shift R _{i + 1} to the left by a fixed number of bits n in (1).

The fact that the square root of A can be obtained by the above procedure will be shown by proving that the following matter A holds. (Matter A) Sum from the 1st to the i-th b ₁ + b ₂ + ...
· + A b _i when compared to _{a 1 + a 2 + ··· +} a i, equal, or only 2 ^-in large, only 2 ^-in small.

(Proof) When i = 1, the following (Equation 5) is established from (Equation 3). (Equation 5) a ₁ × √A ≦ A <(a ₁ +2 ⁻ⁿ ) × √A

## EQU1 ## M is multiplied to each side of (Equation 5) to obtain (Equation 6). (Equation 6) a ₁ × (1-2 ^{− (n + 1)} ) ≦ A × M <(a ₁ +2 ⁻ⁿ ) × (1 + 2 ^{− (n + 1)} )

Since the n bits at the positions of 2 ^-1 to 2 ^{-n on} the left side and the right side of (Equation 6) are a ₁ -2 ^-n and a ₁ +2 ^{-n respectively} , the corresponding bits of A × M are calculated. If n bits are taken as b ₁ , (Matter A) holds when i = 1.

Next, it is assumed that (Matter A) is satisfied until i ≦ k. The kth partial remainder Rk can be expressed as in (Equation 7). (Equation 7) R _k = R _k-1 − {(b ₁ + b ₂ + ... + b _k-1 ) × 2 + b _k } × b _k = R _k-2 − {(b ₁ + b ₂ + ... + B _k-2 ) × 2 + b _k-1 } × b _k-1 − {(b ₁ + b ₂ + ... + b _k-1 ) × 2 + b _k } × b _k ··· == R ₀ −b ₁ × b _{1 - {b 1 × 2 +} b 2} × b 2 · · · - {(b 1 + b 2 + ··· + b k-2) × 2 + b k-1} × b k-1 - {(b 1 + b 2 +・ ・ ・ + B _k-1 ) × 2 + b _k } × b _k = R ₀ − (b ₁ + b ₂ + ... + b _k ) ² = (a ₁ + a ₂ + a ₃ + ...) ² − _{(b 1 + b 2 + ···} + b k) 2 = {(a 1 + a 2 + ··· + a k) + (b 1 + b 2 + ··· + b k) + a k + 1 + ···} × _{{(a 1 + a 2 +} ··· + a k) - (b 1 + b 2 + ··· + b k) + a k + 1 + ···}

(I) b ₁ + b ₂ + ... + b _k = a ₁ + a ₂ + ... + a _k (Equation 8) (2√A−a _{k + 1} ) × a _{k + 1} ≦ R _k <2√A × (a _{k + 1} +2- ^{(k + 1) n} )

For the left side of (Equation 8), (2√A-a
_{When k + 1-} X) * (a _{k + 1} + X) is considered as a quadratic function of X, it is a monotonically increasing function in the domain [0, 2- ^{(k + 1) n} ), and X =
By taking the minimum value at 0. Multiply each side of (Equation 8) by M to obtain (Equation 9). (Equation 9) 2 (1-2 ^{− (n + 1)} −a _{k + 1} ) × a _{k + 1} ≦ R _k × M <2 (1 + 2 ^{− (n + 1)} ) × (a _{k + 1} +2 ^{− (k + 1) n} )

2- ^{kn on} each of the left and right sides of ( ^Equation 9)
To 2 ^{− (k + 1) n + 1} n bits are a _{k + 1} −
Since 2 ^{− (k + 1) n} and a _{k + 1} +2 ^{− (k + 1) n} , when the corresponding n bits of R _k × M are taken as b _{k + 1} (Matter A)
Also holds when i = k + 1.

(Ii) b ₁ + b ₂ + ... + b _k = a ₁
+ A ₂ + ... + _ak +2 ^-kn (Equation 10) (2√A + 2 ^-kn ) × (−2 ^−kn + a _{k + 1} ) <R _k <2√A × (−2 ^−kn + a _{k +1 +} 2- ^{(k + 1) n} )

Regarding the left side of (Equation 10), in the final expression of (Equation 7), since the multiplier is negative in this case, 2 ^-kn
> A _{k + 1} + a _{k + 2} + ... 2− ^kn − (a _{k + 1} + a
The absolute value of the product was evaluated to be large with _{k + 2} + ...) = 0. Multiply each side of (Equation 10) by M to obtain (Equation 11). ( ^Equation 11) 2 (1-2 ^{− (n + 1)} +2 ^−kn ) × (−2 ^−kn + a _{k + 1} ) <R _k × M <2 (1-2 ^{− (n + 1)} ) × ( -2 ^-kn + a _{k + 1} + ^{2- (k + 1) n} )

2 on each of the left and right sides of (Equation 11)
^Considering that n bits at the 2- ^{(k + 1) n + 1} position from ^-kn are added with sign bits higher than 2- ^kn , -2 ^-kn + a _{k + 1} ^{-2- (k + 1) n} , -2 ^-kn + a _{k + 1} + ^{2- (k + 1) n} , and b ₁ + b ₂ + ... + b _{k + 1} is a ₁ + a ₂ +
... is equal to + a _{k + 1,} is larger by 2- ^{(k + 1) n,} or is smaller by 2- ^{(k + 1) n,} so when (Matter A) is i = k + 1 Also holds.

(Iii) b ₁ + b ₂ + ... + b _k = a
_{In the case of 1} + a ₂ + ... + _ak -2 ^-kn (Equation 12) (2√A-2 · 2 ^-kn ) × (2 ^-kn + a _{k + 1} ) <R _k <(2√A-2 ^-kn ) x (2 ^-kn + a _{k + 1} + ^{2- (k + 1) n} ) ( ^Equation 13) 2 ( ^{1-2- (n + 1)} -2 ^{-kn + 1} ) x (2 ^-kn + a _{k +1} ) <R _k × M <2 (1 + 2 ^{− (n + 1)} −2 ^−kn ) × (2 ^−kn + a _{k + 1} +2 ^{− (k + 1) n} )

2 on each of the left and right sides of (Equation 13)
^Considering n bits from ^-kn to 2- ^{(k + 1) n + 1} and 1 bit added to the higher order as 2 ^{-kn + 1} , 2 ^-kn + a _{k + 1} ^{-2- (k + 1 ) n} , 2 ^-kn + a _{k + 1} + ^{2- (k + 1) n} , and b ₁ + b ₂ + ... + b _{k + 1} is a ₁ + a ₂ +
... is equal to + a _{k + 1,} is larger by 2- ^{(k + 1) n,} or is smaller by 2- ^{(k + 1) n,} so when (Matter A) is i = k + 1 Also holds.

Assuming that (Matter A) is satisfied from (i), (ii), and (iii) up to i ≦ k,
When i = k + 1, it is derived that (Matter A) holds, and when i = 1, it has been proved that (Matter A) holds. Therefore, by mathematical induction, (Matter A) is arbitrary. Applies to natural number i.

The table information storage means stores the approximate reciprocal of the square root of A, is indexed by using the upper bits of A as an address, and is stored as 0th remainder in the remainder holding means R ₀ (= A). And the approximate reciprocal of the square root of A are calculated by the multiplication means, and b is set as the high-order bit of the product.
You get ₁ . Next, the multiplicand generating means outputs b _{1 in the first} iterative calculation, and R ₀ , b ₁ and b ₁ are (R−S ×
T) Inputting to the calculating means, R ₁ is obtained. Then b ₁
Is stored in the merged square root holding means, R ₁ is left-shifted by a certain number of bits, and then stored in the remainder holding means.
After that, the following process is repeated with i ≧ 1 until the bit length of the merged square root becomes equal to or larger than the bit length of the square root to be obtained.

The product of R _i stored as the i-th residue in the residue holding means and the approximate reciprocal of the square root of A is calculated by the multiplying means, and b _{i + 1} is obtained as the upper bit of the product. Next, in the multiplicand generating means (b ₁ + ... + b _i ).
Is shifted to the left by 1 bit and merged with b _{i + 1} and output as a multiplicand, and R _i , {(b ₁ + ... + b _i ) × 2
+ B _{i + 1} } and b _{i + 1} are input to the (R−S × T) computing means to obtain R _{i + 1} . Next, (b ₁ + ... + b
_{i + 1} ) is stored in the merged square root holding means, R _{i + 1} is left-shifted by a fixed number of bits, and then stored in the remainder holding means.

It should be noted that R _{i + 1} is stored in the remainder holding means without being left-shifted by a fixed number of bits, and in the next iterative calculation, R _i − {(b ₁ + ... + b _i ) × 2 + b _The result is the same even if R _i is left-shifted by a certain number of bits immediately before the calculation of _{i + 1} } × b _{i + 1} .

[0031]

[Embodiments] First, items common to the embodiments will be described.

In each of the embodiments, the aperture number A is moved from (Equation 1) to the right by 2 bits (Equation 14) so that the obtained square root becomes the same as the position of the decimal point of the mantissa part of the IEEE standard floating point. ) Range. (Number 14) 1 ≦ A ^<2 2

The approximate reciprocal of the square root is 1 shown in (Equation 15).
Two bits (x represents 0 or 1) are indexed as an address. (Equation 15) 01. xxxxxxxxxxxx 1x. xxxxxxxxxxxx

The numerical values stored in the table information storage means are
As the reciprocal of the square root, it was selected in the range satisfying n = 11 in (Equation 4). The accuracy of the approximate reciprocal of the square root was confirmed using a computer, but the outline of the confirmation method is shown below. M is [1 + k] obtained by dividing the interval [1,4) into 3072 equal parts.
× 2 ^-10 , 1 + (k + 1) × 2 ^-10 ) (k = 0,1, ...
.., 3071) is a constant. In order to further improve the precision of the approximate reciprocal of the square root, if the 2 ^{-11 digit} , which is one bit smaller than the least significant bit used as the address of the table information storage means of the ^augend , is 0, the table is obtained by the method described later. Add 2 ^-16 to the value output by the information storage means. Considering this graphically, y = 1 / √x is a downward-sloping curve as shown in FIG. 15, so [1 + k
In the left half of × 2 ^-10 , 1 + (k + 1) × 2 ^-10 ), this means raising the value of the approximate reciprocal of the square root by 2 ^-16 . Therefore, the interval [1,4) is 6144.
The graph of the approximate reciprocal of the square root with respect to the evenly divided A is the step function shown in FIG. On the other hand, in the graph of A × M × M, as shown in FIG. 14, 6144 line segments are in the shape of saw teeth. The accuracy obtained is as follows (1
Hexadecimal display). When the maximum value is 1.004, 1.001FD9048 When the minimum value is 1.000, 0. FFE001

The above values satisfy (Equation 16), which is obtained by performing equation transformation with n = 11 in (Equation 4) and squaring each side. (Equation 16) (1-0.001) ² = 0. FFE001 ≦ A × M × M ≦ (1 + 0.001) ² = 1.200001

The table information storage means stores values of 2 ⁻² to 2 ⁻¹⁶ , which are the reciprocal of the square root, and the sign bit which is always 0 and the 2 ⁻¹ bit which is always 1 are not directly stored in the table. Since it is troublesome to add the description one by one in the embodiment, the description will be made so that 01 is included in the table as the first 2 bits. When performing multiplication, set the multiplier to 1
Divide into groups of 3-bit units with bits overlapped to generate a multiple of the multiplicand according to the Booth algorithm shown in Table 1, and to generate two partial carry and partial sum by a carry hold adder group configured like a tree. Then, the two are added by the carry propagation adder to obtain the final product. When multiplying the remainder by the approximate reciprocal of the square root, 1 is added to the beginning of the value read from the table, and
At the end, the inversion of the adjacent 1 bit to the right of the bit used as the address is added. In multiplication, the bit added to the right is used as the least significant bit of the multiplier, so that the effect is not 2 ^-17 times but 2 ^-16 times.

[0037]

[Table 1]

In the calculation of (R−S × T), R is input to the tree-like carry-reserving adder group as a kind of multiple with respect to the configuration of the multiplier described above, and {R + S × (-T )} Is obtained by taking the 1's complement of the input of the multiplier and adding 1 as the least significant bit to the above ^2-17
With the same effect that it has a ^2-16x effect instead of a double,
The multiplier is made to be a two's complement substantially by an arithmetic means of (RS). It is well known to those skilled in the art that multiplication of the sign bit can be executed in the 2's complement notation by appropriately expanding the sign bit to the higher order.

Further, in each claim, in the square root arithmetic unit having the adding means for calculating the partial square root, the multiplying means or (R
The output of the + S × T) calculating means is used as the input of the adding means for calculating the partial square root, but in each embodiment, the adding means for calculating the partial square root is included inside the multiplying means or the (R + S × T) calculating means. . This is to carry out carry propagation addition to find the product at the stage where the partial carry and partial sum are found in the multiplication, and at the same time to perform the addition to find the partial square root with rounding to improve the operation speed. by. Multiplying means or (R + S in such an embodiment
× T) The case where the adding means for calculating the partial square root is included inside the calculating means is also an object of the present invention. In each of the embodiments, the explanation of the addition means for calculating the partial square root is performed by mischievous space, so that only the case corresponding to the first embodiment will be described here, and the multiplication means or ( R + S
× T) The description of the internal operation of the calculation means for calculating the partial square root will be omitted. The purpose of rounding the partial square root may be smaller by 1 when comparing the true square root with the least significant bit (LSB) when the square root is obtained by the required number of digits. For example, the square root of 1 is 0.111.・ ・
This is for avoiding (binary number display), and conversely, when b _i is larger by 2 ⁻ⁱⁿ than the accurate partial square root a _i , the lower one bit is 0, and by rounding it further +2 ^-Because it is not in, the partial square root b _i is 1
There is no adverse effect from rounding at the lower bits.

FIG. 12 is an internal block diagram of multiplication means (first embodiment of the present invention). In FIG. 12, 401 to 409 are multiple generation means (ML), 410 to 416 are carry hold addition means (CSA), 417 is carry propagation addition means (CPA), 418 and 419 are addition means for partial square root calculation (CPA1). , CPA2), 420 are look-ahead carry means (LAC). Multiple generation means 401 to 409
Input a multiplicand, and input a multiplicand of 3 bits by overlapping the adjacent multiplier generating means by 1 bit, and generate a multiple of the multiplicand shown in Table 1. The outputs of the multiple generation means 401 to 409 are input to the carry hold addition means 410 to 412 as shown in FIG. 12, respectively, and after the carry hold addition is executed, the carry hold addition means 413.
From 416 to 416, they are finally grouped into two: partial carry and partial sum. And bits from 2 ⁷² to 2 ⁰ parts carry a partial sum output from the carry save adder means 416, 2
And bits from ⁷¹ to 2 ^58, respectively bits from 2 ⁷² to 2 ^59, carry propagate adder means 417 and the look ahead carry means 420, the first partial square root calculation adding unit 418, calculating a second partial square It is input to the adding means 419 for use. The foreseeing carry means 420 predicts and outputs a carry to 2 ⁵⁸ to the first adding means 418 for calculating a partial square root, while it outputs 2 ⁵⁹ to the adding means 419 for calculating a second partial square root. Predict and output carry to. The addition means 418 and 419 for calculating both partial square roots perform rounding addition at the positions of 2 ⁵⁸ and 2 ⁵⁹ , respectively, and 13 bits of 2 ⁷¹ to 2 ⁵⁹ and 2 ⁷² to 2 ⁶⁰ are 1-bit sign and 12-bit partial square root of data. Output as.

Seven examples will be described below. In the embodiments, specific numerical examples are cited, but the numerical values are displayed in hexadecimal unless otherwise specified in order to save space. In addition, since reference is made in a plurality of embodiments in the figures showing numerical examples, it seems that the code bits are excessively extended for some embodiments. In the vector square root computing devices of the third embodiment (FIGS. 5 and 6) and the sixth embodiment (FIGS. 10 and 11), when the corresponding claims 3 and 8 are compared, the data holding means is more than the claims. Although the present invention is provided, the present invention is not limited to the number of data holding means in the claims, and the operation of the data holding means is performed so that the pipeline pitch is optimum according to the hardware circuit used. The arrangement in the device may be determined. Further, in the vector square root computing device of the third embodiment, when compared to the corresponding claim 3, the arrangements of the exponent constant adding means and the exponent holding means do not match, but the exponent part can be easily obtained compared to the mantissa part. The arithmetic means for the exponent may be inserted between arbitrary exponent holding means until the arithmetic result of the mantissa part is obtained.

(Embodiment 1) FIG. 1 is a block diagram of a floating point square root arithmetic unit according to a first embodiment of the present invention. The floating point square root arithmetic unit of this embodiment is IEEE
A standard double-precision floating-point number is input, the square root of the same double-precision floating-point number is output, the bit length as the data of the partial square root is 12, and there is an overlap of 1 bit between the partial square roots. In FIG. 1, 1 is an input register, 2 is exception detecting means, 3 is exponential constant subtracting means, 4 is shifter, 5 is exponential constant adding means, 6 is a leading bit adding circuit, 7 is normalizing means, and 8 is table information. Storing means, 9 is a multiplexer, 10 is a remainder holding means, 11 is a multiplying means, 12 is a shifter, 13 is a multiplexer, 14 is a merged square root holding means, 15 is an inverting means, 16 is a multiplicand generating means, and 17 is (R + S × T). ) Computation means, 18 is constant subtraction means, 19 is a multiplexer, 20 is digit alignment means, and 21 is addition means.

The operation of the floating point square root arithmetic unit shown in FIG. 1 will be described below by using specific numerical examples. 2 and 3
Shows the process of processing by each means after the operand is input. First as an operand 7
C88B89EAF092E9F is input and set in the input register 1. When the input operand is negative, the exception detection unit 2 detects it as a data exception and notifies the instruction execution control unit outside the floating point square root arithmetic unit that an exception has occurred. In this numerical example (in the following,
(This assumption is omitted.) The operand is positive, so no exception is detected. The exponents from 2 ⁶² to 2 ⁵² of the output of the input register 1 are subtracted by 3FF by the exponent constant subtracting means 3, then shifted right by 1 bit by the shifter 4, and added by 3FF again by the exponential constant adding means 5. And the resulting index is determined. The leading bit adding circuit 6 adds a leading bit 1 to the head of the mantissa part of 2 ⁵¹ to 2 ⁰ of the output of the input register 1. In the normalizing means 7, when the 2 ⁵² bits of the output of the input register 1 is 1, the input is shifted left by 1 bit, and when the 2 ⁵² bits of the output of the input register 1 is 0, the input is moved to the left. 2 bits are shifted and output. 12 bits from 2 ⁵⁴ to 2 ⁴³ of the normalization means 7 are input to the table information storage means 8, and 09
1A0 is output. Further, as the least significant bit of this output, a bit obtained by inverting the 2 ⁴² bit of the normalizing means 7 is added, but in this example, 1 is added and the multiplying means 1 is added.
The actual multiplier at 1 is 091A1. The multiplexer 9 selects the output of the normalizing means 7, and this output is set in the surplus holding means 10. At this time, the merged square root holding means 14 is reset to zero. 6 by multiplication means 11
The product of 2E27ABC24BA7C and 091A1 is multiplied, and the product of 0384077F3C120B983FC is obtained, and at the same time, the result of rounding the product at 2 ^{58 in} the first iteration and at 2 ^{59 in} the second and subsequent iterations is the result for multiplexer 13. Is output. Code 1 bit 13 bits 2 ⁷¹ 2 ⁵⁹ multiplexers 13, multiplying unit 11, selects as the first partial square root of the data 12 bits. The inverting means 15 inputs the partial square root, inverts the bits, adds 1 to the least significant bit, and outputs it. Also, in the multiplicand generating means 16, in the first iteration, the output of the multiplexer 13 is embedded from 2 ⁵⁶ to 2 ⁴⁴ and the other bits are output as zero. (R + S × T)
In the calculation means 17, the surplus holding means 1 output from the shifter 12
The value obtained by shifting the output of 0 to the left by 11 bits is input as R, the output of the multiplicand generating means 16 is input as S, and the output of the inverting means 15 is input as T, and the operation of (R + S × T) is executed. (R + S
XT) Output 0FD5E125D3E00 of the calculation means 17
0 is selected by the multiplexer 9, and the surplus holding means 1
It is set to 0. On the other hand, the constant subtracting means 18 subtracts 1 from the LSB of the output of the multiplexer 13. The multiplexer 19 selects the output of the constant subtracting means 18 when the output of the (R + S × T) computing means 17 is negative, and selects the output of the multiplexer 13 otherwise. In the first iteration, the above condition is judged and the output of the multiplexer 13 is selected. The digit alignment means 20 performs digit alignment for merging the partial square roots in each iteration. In particular,
When the partial square root is negative, the first 2 bits of the 13 bits of the output of the multiplexer 19 are suppressed to zero, and when the partial square root is positive, the 13 bits of the output of the multiplexer 19 are set to the upper merged square root. Shift and output so that the bit weights of and are balanced. For the first partial square root, align the input data from 2 ⁵⁶ to 2 ⁴⁴ and output. In the adding means 21, the merged square root holding means 1
The output of 4 and the output of the digit aligning means 20 are input to perform addition, and the result is set in the merged square root holding means 14.

Next, the second iterative calculation is started. The output of the table information storage means 8 is the same as that of the first time after the second time. The first surplus R ₁ set in the surplus holding means 10.
0FD5E125D3E000 is multiplied by 091A1 by the multiplication means 11 to obtain the product 009021A0905CC.
1FE000 is output. Numerals 2 ⁷² to 2 ⁶⁰ 0090 are selected by the multiplexer 13 as the second partial square root of the code 1 bit and the data 12 bits. The inverting means 15 inverts 0090 into 1F6F, adds 1 as the least significant bit, and outputs (R + S × T).
In the calculation means 17, the calculation is performed at 1F70 as a multiplier. On the other hand, in the multiplicand generating means 16, the output of the merged square root holding means 14 is shifted to the left by 1 bit, and the 12 bits excluding the head bit of the 13 bits output from the multiplexer 13 are embedded from 2 ⁴⁴ to 2 ³³ to 0E.
Outputs 1012000000. (R + S ×
T) In the computing means 17, the output of the remainder holding means 10 output from the shifter 12 is shifted to the left by 11 bits to R, the output of the multiplicand generating means 16 is S, and the output of the inverting means 15 is T.
Is input and the calculation of (R + S × T) is executed. (R
+ S × T) Output of computing means 17 1E672E9F000
000 is selected by the multiplexer 9 and set in the surplus holding means 10. The multiplexer 19 selects and outputs the output of the multiplexer 13, and the digit alignment means 2
At 0, the 13-bit input is aligned from 2 ⁴⁵ to 2 ³³ .
The addition means 21 inputs the output of the merged square root holding means 14 and the output of the digit alignment means 20 to perform addition, and 070
Outputs 812,000000000. The merged square root holding means 14 sets the output of the adding means 21.

Next, the third iterative calculation is started. The output of the table information storage means 8 is the same as that of the first time. 1E672E of the _second surplus R ₂ set in the surplus holding means 10.
9F000000 is multiplied by 091A1 by the multiplication means 11, and the product 0114B904C60FF000000 is output. 2 ⁷² to 2 ⁶⁰ after rounding at 2 ⁵⁹ place 011
5 is selected by the multiplexer 13 as the third partial square root of the code 1 bit and the data 12 bits. In the inverting means 15, 0115 is inverted to become 1EEA, 1 is added as the least significant bit, and output (R + S ×
T) In the calculation means 17, the calculation is substantially performed with 1EEB as a multiplier. On the other hand, in the multiplicand generating means 16, the output of the merged square root holding means 14 is shifted to the left by 1 bit, and 12 bits excluding the head bit of the 13 bits output from the multiplexer 13 are embedded from 2 ³³ to 2 ²² .
0E1024045400000 is output. (R + S
XT) In the calculating means 17, the output of the remainder holding means 10 output from the shifter 12 is shifted to the left by 11 bits, and the result is R,
The output of the multiplicand generating means 16 is input as S and the output of the inverting means 15 is input as T, and the operation of (R + S × T) is executed.
(R + S × T) Output of computing means 17 C2056D11C
00000 is selected by the multiplexer 9 and set in the surplus holding means 10. The multiplexer 19 selects and outputs the output of the constant subtracting means 18, and the digit aligning means 20 aligns the 13-bit input from 2 ³⁴ to 2 ²² . The addition means 21 inputs the output of the merged square root holding means 14 and the output of the digit alignment means 20 to perform addition,
The output is 070812045000000. The merged square root holding means 14 sets the output of the adding means 21.

Next, the fourth iterative calculation is started. The output of the table information storage means 8 is the same as that of the first time. C2056D of the _third residue R ₃ set in the residue holding means 10.
11C00000 is multiplied by 091A1 by the multiplication means 11, and the product 1DCBE1830A5E9C00000 is output. 1 DC from 2 ⁷² to 2 ⁶⁰ after rounding at 2 ⁵⁹
The multiplexer 13 selects C as the fourth partial square root of the code 1 bit and the data 12 bits. In the inverting means 15, 1DCC is inverted to become 0233, 1 is added as the least significant bit and the result is output (R + S ×
T) In the calculating means 17, the calculation is practically performed at 0234 as a multiplier. On the other hand, the multiplicand generating means 16 shifts the output of the merged square root holding means 14 to the left by 1 bit, and embeds 12 bits excluding the head bit of 13 bits output from the multiplexer 13 from 2 ²² to 2 ¹¹ ,
0E102408A6E6000 is output. (R + S
XT) In the calculating means 17, the output of the remainder holding means 10 output from the shifter 12 is shifted to the left by 11 bits, and the result is R,
The output of the multiplicand generating means 16 is input as S and the output of the inverting means 15 is input as T, and the operation of (R + S × T) is executed.
(R + S × T) Output of computing means 17 E45EBEFB2
B8000 is selected by the multiplexer 9 and set in the surplus holding means 10. The multiplexer 19 selects and outputs the output of the constant subtraction means 18, and the digit alignment means 20 suppresses the leading 2 bits of the 13-bit input to zero and aligns 11 bits from 2 ²¹ to 2 ¹¹ . The addition means 21 inputs the output of the merged square root holding means 14 and the output of the digit alignment means 20 to perform addition, and 0708
120452E5000 is output. The merged square root holding means 14 sets the output of the adding means 21.

Next, the fifth iterative calculation is started. The output of the table information storage means 8 is the same as that of the first time. E45EBE of the _fourth residue R ₄ set in the residue holding means 10.
The FB2B8000 is multiplied by 091A1 by the multiplication means 11, and the product 1F04849C25F99DB8000 is output. After rounding at 2 ⁵⁹ , 2 ⁷² to 2 ⁶⁰ 1F0
5 is selected by the multiplexer 13 as the fifth partial square root of the code 1 bit and the data 12 bits. The inverting means 15 inverts 1F05 to become 00FA, adds 1 as the least significant bit, and outputs (R + S ×
T) The calculation means 17 performs calculation with 00FB as a multiplier. On the other hand, the multiplicand generating means 16 shifts the output of the merged square root holding means 14 to the left by 1 bit, and embeds 12 bits excluding the head bit of 13 bits output from the multiplexer 13 from 2 ¹¹ to 2 ⁰ ,
Outputs 0E102408A5CBF05. (R + S
XT) In the calculating means 17, the output of the remainder holding means 10 output from the shifter 12 is shifted to the left by 11 bits, and the result is R,
The output of the multiplicand generating means 16 is input as S and the output of the inverting means 15 is input as T, and the operation of (R + S × T) is executed.
The (R + S × T) calculating means 17 is 932D2104EF4.
9E7 is output. The multiplexer 19 selects and outputs the output of the constant subtracting means 18, and the digit aligning means 20 suppresses the leading 2 bits of the 13-bit input to zero and aligns 11 bits from 2 ¹⁰ to 2 ⁰ . Adder 2
In the case of 1, the output of the merged square root holding means 14 and the output of the digit alignment means 20 are input and addition is performed.
52E5F04 is output.

As a final result, the sign bit of 2 ⁶³ is 0, the exponent part of 2 ⁶² to 2 ⁵² is 11 bits output from the exponent constant adding means 5, and the mantissa part of 2 ⁵¹ to 2 ⁰ is the addition part 21. 2 ⁵³ to 2 ² are selected and 5E
3C2048114B97C1 is output from the square root arithmetic unit shown in FIG.

(Embodiment 2) FIG. 4 is a block diagram of a floating point square root arithmetic unit according to a second embodiment of the present invention. The floating point square root arithmetic unit of this embodiment is IEEE
A standard double-precision floating-point number is input, the square root of the same double-precision floating-point number is output, the bit length as the data of the partial square root is 12, and there is an overlap of 1 bit between the partial square roots. In FIG. 4, 31 is an input register, 32 is an exception detecting means, 33 is an exponential constant subtracting means, 34 is a shifter, 3
5 is exponential constant adding means, 36 is a leading bit adding circuit, 37 is normalizing means, 38 is table information storing means, 39 is a multiplexer, 40 is a surplus holding means, 41
Is a merged square root holding means, 42 is a partial square root holding means (b
i), 43 is a shifter, 44 is an inverting means, 45 is a multiplicand generating means, 46, 47 and 48 are multiplexers, 49 is an (R + S × T) arithmetic means, 50 is a multiplexer, 51
Is a constant subtracting means, 52 is a multiplexer, 53 is a digit aligning means, and 54 is an adding means.

The operation of the floating point square root extraction arithmetic unit shown in FIG. 4 will be described below by using specific numerical examples. The process in which the operands are input and then processed by each means is the same as in FIGS. 2 and 3 used in the first embodiment. First, 7C88B89EAF092E9 as an operand
F is input and set in the input register 31. When the input operand is negative, the exception detection means 32 detects it as a data exception and notifies the instruction execution control unit outside the floating point square root arithmetic unit that an exception has occurred. In this numerical example (hereinbelow, this assumption is omitted), since the operand is positive, no exception is detected. The exponent constant subtraction means 33 subtracts 3FF from the exponents of 2 ⁶² to 2 ⁵² of the output of the input register 31, and then the shifter 34.
By 1 bit to the right by means of the exponential constant adding means 35
Then, 3FF is added again and the resulting exponent is obtained. The leading bit adding circuit 36 adds a leading bit of 1 to the head of the mantissa part of 2 ⁵¹ to 2 ⁰ of the output of the input register 31. The normalizing means 37 shifts the input to the left by 1 bit when the 2 ⁵² bits of the output of the input register 31 are 1, and the input register 3
When 2 ⁵² bits of the output of 1 are 0, the input is shifted 2 bits to the left and output. 12 bits from 2 ⁵⁴ to 2 ⁴³ of the normalization means 37 are input to the table information storage means 38,
091A0 is output. Further, as the least significant bit of this output, a bit obtained by inverting the 2 ⁴² bit of the normalizing means 37 is added, but in this example, 1 is added and (R
+ S × T) The actual multiplier in the calculation means 49 is 091A1.
Becomes The multiplexer 39 selects the output of the normalizing means 37, and this output is set in the surplus holding means 40. At this time, the merged square root holding means 41 is reset to zero. The multiplexers 46, 47 and 48 respectively select '0', the output of the residue holding means 40 and the output of the table information storage means 38, and the (R + S × T) operation means 4
In 62, 62E27ABC24BA7C and 091A1 are multiplied, and 084077F3C120B983FC
At the same time that the product is obtained, the result of rounding the product at the 2 ⁵⁸ 's place in the first iteration and at the 2 ⁵⁹ 's place in the second and subsequent iterations is output to the multiplexer 50. In the multiplexer 50, 2 ⁷¹ to 2 ^{59 of the} (R + S × T) computing means 49.
13 bits are selected as the first partial square root of the code 1 bit and the data 12 bits, and the partial square root holding means 42 is selected.
This partial square root is set to. In the shifter 43, the output of the surplus holding means 40 is shifted to the left by 11 bits. The inverting means 44 inputs the partial square root, inverts the bits, extends the 4-bit code to the upper bit, and outputs 1 to the least significant bit.
Is added and output. Further, in the multiplicand generating means 45,
In the first iteration, the output of the partial square root holding means 42 is embedded from 2 ⁵⁶ to 2 ⁴⁴ , and the other bits are output as zero. The multiplexers 46, 47, 48 select the output of the shifter 43, the output of the multiplicand generating means 45, and the output of the inverting means 44, respectively. In the (R + S × T) computing means 49, the output of the multiplexer 46 is R, and the multiplexer 47 is
Is output as S and the output of the multiplexer 48 is input as T, and the operation of (R + S × T) is executed. (R + S × T)
The output 0FD5E125D3E000 of the calculation means 49 is selected by the multiplexer 39 and set in the remainder holding means 40. On the other hand, the constant subtraction means 51 subtracts 1 from the LSB of the output of the partial square root holding means 42. The multiplexer 52 selects the output of the constant subtracting means 51 when the output of the (R + S × T) computing means 49 is negative, and selects the output of the partial square root holding means 42 otherwise. In the first iteration, the above conditions are judged and the partial square root holding means 4
Select 2 outputs. The digit alignment means 53 executes digit alignment for merging the partial square roots in each iteration. Specifically, when the partial square root is negative, the multiplexer 5
Suppress the first 2 bits of 13 bits of the output of 2 to zero,
If the partial square root is positive, the multiplexer 52
13 bits of the output of the above are shifted and output so that the weights of the bits of the upper merged square root are balanced. For the first partial square root, align the input data from 2 ⁵⁶ to 2 ⁴⁴ and output. The adding means 54 inputs the output of the merged square root holding means 41 and the output of the digit aligning means 53 to perform addition, and sets the result in the merged square root holding means 41.

Next, the second iterative calculation is started. The output of the table information storage means 38 is the same as that of the first time even after the second time. The multiplexers 46, 47 and 48 are respectively
'0', 0FD5E125D3E000 of the _first surplus R ₁ set in the surplus holding means 40, the output 091A1 of the table information storage means 38 are selected, and (R + S × T)
The calculation means 49 executes (S × T) and calculates the product 009021A.
Outputs 0905CC1FE000. The multiplexer 50 selects 2 0090 from 2 ⁷² to 2 ^{60 as} the second partial square root of code 1 bit and data 12 bits, and this partial square root is set in the partial square root holding means 42. In the shifter 43, the output of the surplus holding means 40 is 11 to the left.
Bit-shifted. The inverting means 44 inverts 0090, expands the 4-bit code to the higher order and outputs 1FF6F, and adds 1 as the least significant bit and outputs (R
+ S × T) The calculation means 49 is substantially 1FF as a multiplier.
The operation is performed at 70. On the other hand, in the multiplicand generating means 45, the output of the merged square root holding means 41 is shifted to the left by 1 bit and the output of the partial square root holding means 42 is set to 1
12 bits excluding the first 3 bits from 2 ⁴⁴ to 2 ³³
Embedded in, and outputs 0E1012000000. The multiplexers 46, 47 and 48 respectively output the shifter 43, the multiplicand generating means 45 and the inverting means 4.
4 output is selected. The (R + S × T) operation means 49 inputs the output of the multiplexer 46 as R, the output of the multiplexer 47 as S, and the output of the multiplexer 48 as T, and executes the operation of (R + S × T). (R + S × T)
The output 1E672E9F000000 of the computing means 49 is selected by the multiplexer 39 and set in the surplus holding means 40. The multiplexer 52 selects and outputs the output of the partial square root holding means 42, and the digit aligning means 53 aligns the 13-bit input from 2 ⁴⁵ to 2 ³³ . In the adding means 54, the output of the merged square root holding means 41 and the output of the digit adjusting means 53 are input and addition is performed.
It outputs 2000000000. The merged square root holding means 41 sets the output of the adding means 54.

Next, the third iterative calculation is started. The output of the table information storage means 38 is the same as that of the first time. The multiplexers 46, 47 and 48 are respectively “0” and 1E672 of the _second remainder R ₂ set in the remainder holding means 40.
E9F000000, the output 091A1 of the table information storage means 38 is selected, the (R + S × T) operation means 49 executes (S × T), and the product 0114B904C60FF0.
000000 is output. 2 ⁷² from 2 after rounding at 2 ⁵⁹
The multiplexer 50 selects 0115 of ^{60 as} the third partial square root of the code 1 bit and the data 12 bits, and this partial square root is set in the partial square root holding means 42. In the shifter 43, the output of the surplus holding means 40 is shifted to the left by 11 bits. In the inverting means 44, 0115 is inverted, the 4-bit code is extended to the upper bit and becomes 1FEEA, and 1 is added as the least significant bit and output (R
+ S × T) The calculation means 49 is substantially 1FE as a multiplier.
Calculation is performed in EB. On the other hand, in the multiplicand generating means 45, the output of the merged square root holding means 41 is shifted to the left by 1 bit and the output of the partial square root holding means 42 is set to 1
12 bits except the first 3 bits are 2 ³³ to 2 ²²
, And outputs 0E1024045400000. The multiplexers 46, 47 and 48 respectively output the shifter 43, the multiplicand generating means 45 and the inverting means 4.
4 output is selected. The (R + S × T) operation means 49 inputs the output of the multiplexer 46 as R, the output of the multiplexer 47 as S, and the output of the multiplexer 48 as T, and executes the operation of (R + S × T). (R + S × T)
The output C2056D11C00000 of the computing means 49 is selected by the multiplexer 39 and set in the residue holding means 40. The multiplexer 52 uses the constant subtraction means 5
1 output is selected and output, and the digit alignment means 53 outputs 13
Align bit inputs from 2 ³⁴ to 2 ²² . Adder 5
In 4, the output of the merged square root holding means 41 and the output of the digit alignment means 53 are input and addition is performed.
Outputs 5000000. The merged square root holding means 41 sets the output of the adding means 54.

Next, the fourth iterative calculation is started. The output of the table information storage means 38 is the same as that of the first time. The multiplexers 46, 47 and 48 are respectively “0”, C2056 of the _third residue R ₃ set in the residue holding means 40.
D11C00000, the output 091A1 of the table information storage means 38 is selected, the (R + S × T) operation means 49 executes (S × T), and the product 1DCBE1830A5E9C
000000 is output. 2 ⁷² from 2 after rounding at 2 ^59
The 1 DCC of ⁶⁰ is selected by the multiplexer 50 as the fourth partial square root of the code 1 bit and the data 12 bits, and this partial square root is set in the partial square root holding means 42. In the shifter 43, the output of the surplus holding means 40 is shifted to the left by 11 bits. In the inverting means 44, 1DCC is inverted, and the 4-bit code is extended to the high-order to become 00233, and 1 is added as the lowest-order bit and output (R
+ S × T) In the calculation means 49, a multiplier is 002.
Calculation is performed at 34. On the other hand, in the multiplicand generating means 45, the output of the merged square root holding means 41 is shifted to the left by 1 bit and the output of the partial square root holding means 42 is set to 1
12 bits except the first 3 bits are 2 ²² to 2 ¹¹
Embedded, and outputs 0E102408A6E6000. The multiplexers 46, 47 and 48 respectively output the shifter 43, the multiplicand generating means 45 and the inverting means 4.
4 output is selected. The (R + S × T) operation means 49 inputs the output of the multiplexer 46 as R, the output of the multiplexer 47 as S, and the output of the multiplexer 48 as T, and executes the operation of (R + S × T). (R + S × T)
The output E45EBEFB2B8000 of the computing means 49 is selected by the multiplexer 39 and set in the surplus holding means 40. The multiplexer 52 uses the constant subtraction means 5
1 output is selected and output, and the digit alignment means 53 outputs 13
Of the input bits, the first 2 bits are suppressed to 0 and set to 1
Align one bit from 2 ²¹ to 2 ¹¹ . In the adding means 54, the output of the merged square root holding means 41 and the digit aligning means 53
The output of is input and addition is performed.
Outputs E5000. The merged square root holding means 41 sets the output of the adding means 54.

Next, the fifth iterative calculation is started. The output of the table information storage means 38 is the same as that of the first time. The multiplexers 46, 47 and 48 are respectively "0" and E45EB of the _fourth residue R ₄ set in the residue holding means 40.
EFB2B8000, the output 091A1 of the table information storage means 38 is selected, the (R + S × T) calculation means 49 executes (S × T), and the product 1F04849C25F99D
Outputs B8000. 2 ⁷² from 2 after rounding at 2 ⁵⁹
1F05 of ⁶⁰ is selected by the multiplexer 50 as the fifth partial square root of code 1 bit and data 12 bits, and this partial square root is set in the partial square root holding means 42. In the shifter 43, the output of the surplus holding means 40 is shifted to the left by 11 bits. In the inverting means 44, 1F05 is inverted, the 4-bit code is extended to the higher order and becomes 000FA, and 1 is added as the least significant bit and output (R
+ S × T) In the calculation means 49, a multiplier is practically 00F
The operation is performed at B. On the other hand, in the multiplicand generating means 45, the output of the merged square root holding means 41 is shifted to the left by 1 bit and the output of the partial square root holding means 42 is set to 1
12 bits excluding the first 3 bits from 2 ¹¹ to 2 ⁰
Embedded, and outputs 0E102408A5CBF05. The multiplexers 46, 47 and 48 respectively output the shifter 43, the multiplicand generating means 45 and the inverting means 4.
4 output is selected. The (R + S × T) operation means 49 inputs the output of the multiplexer 46 as R, the output of the multiplexer 47 as S, and the output of the multiplexer 48 as T, and executes the operation of (R + S × T). (R + S × T)
The calculation means 49 outputs 932D2104EF49E7. The multiplexer 52 selects and outputs the output of the constant subtracting means 51, and the digit aligning means 53 suppresses the leading 2 bits of the 13-bit input to zero and aligns 11 bits from 2 ¹⁰ to 2 ⁰ . In the adding means 54, the output of the merged square root holding means 41 and the output of the digit adjusting means 54 are input and addition is performed.
Is output.

As a final result, the sign bit of 2 ⁶³ is 0, the exponent part of 2 ⁶² to 2 ⁵² is 11 bits output from the exponent constant adding means 35, and the mantissa part of 2 ⁵¹ to 2 ⁰ is the addition part 54. 2 ⁵³ to 2 ² are selected and 5
E3C2048114B97C1 is output from the square root arithmetic unit shown in FIG.

(Embodiment 3) FIGS. 5 and 6 are block diagrams of a floating point vector square root arithmetic unit according to a third embodiment of the present invention. The floating-point vector square root arithmetic unit of the present embodiment inputs a double-precision floating-point vector of the IEEE standard in element order, outputs a square root vector of the same double-precision floating-point number in element order, and outputs a bit length as partial square root data. Is 12 and there is a 1-bit overlap between the partial square roots. 5 and 6, 61 is an input register,
62_1 to 62_12 are exception detection information holding means, 63
Is exponential constant subtracting means, 64 is a shifter, 65 is exponential constant adding means, 66_1 to 66_12 are exponent holding means, 67
Is a leading bit addition circuit, 68 is a normalizing means, 6
Reference numeral 9 is a normalized operand register, 70 is table information storage means, 71_2 to 71_10 are table output information holding means, 72_2 to 72_12 are surplus holding means, and 73.
_1 to 73_5 are multiplication means, 74_1 to 74_5 are partial square root holding means, 75_1 to 75_5 are shifters,
76_1 to 76_5 are inverting means, and 77_1 to 77_
5 is the multiplicand generating means, and 78_1 to 78_5 are (R + S
× T) arithmetic means, 79_1 to 79_5 are constant subtraction means, 80_1 to 80_5 are multiplexers, 81_2
To 81_5 are addition means, 82_4 to 82_12 are merged square root holding means, and 83 is exception detection means.

Hereinafter, FIGS. 5 and 6 will be described using specific numerical examples.
The operation of the floating point vector square root calculating unit shown in FIG. The process in which the operand of one element of the vector is input and then processed by each means is the same as in FIGS. 2 and 3 used in the first embodiment. The following describes how one element is processed for each stage.

Stage 0: 7C88B89EAF092E9F is first input as an operand and set in the input register 61. The exponent constant subtracting means 63 subtracts 3FF from the exponents of 2 ⁶² to 2 ⁵² of the output of the input register 61. On the other hand, the leading bit adding circuit 67 adds the leading bit 1 to the head of the mantissa part of 2 ⁵¹ to 2 ⁰ of the output of the input register 61.
The normalizing means 68 shifts the input to the left by 1 bit when the 2 ⁵² bits of the output of the input register 61 is 1, and moves the input to the left when the 2 ⁵² bits of the output of the input register 61 is 0. 2 bits are shifted and output.

Stage 1: Introduction Input Register 61
1 bit at the head of the output of the exception detection information holding means 62_1
In addition, the output of the exponent constant subtraction means 63 is the exponent holding means 66_
The output of the normalizing means 68 is set to 1 in the normalizing operand register 69. Index holding means 66_
The output of 1 is shifted 1 bit to the right by the shifter 64,
12 bits of 2 ⁵⁴ to 2 ⁴³ output from the normalized operand register 69 are input to the table information storage means 70, and 091A0 is output. Further, as the least significant bit of this output, 2 of the output of the normalized operand register 69
^{Although the} inverted ⁴² bits are added, 1 is added in this example, and the substantial multiplier in the multiplication units 73_1 to 73_5 is 091A1.

Stage 2: First, the output of the exception detection information holding means 62_1 is 62_2, the output of the shifter 64 is the exponent holding means 66_2, and the normalized operand register 6
9 is output to the surplus holding means 72_2, and output of the table information storage means 70 is table output information holding means 71_2.
Are set respectively. 3FF is added to the output of the exponent holding unit 66_2 by the exponent constant adding unit 65, and the resulting exponent is obtained. 62 by multiplication means 73_1
The multiplication of E27ABC24BA7C and 091A1 is performed to obtain the product of 0384077F3C120B983FC.

Stage 3: First, the output of the exponent constant adding means 65 is sent to the exponent holding means 66_3 and the multiplying means 73_
13-bit sign bit of 1 of 2 ⁷¹ to 2 ^59, the partial square root holding means 74_1 as the first partial square root of the data 12 bits, the output of the exception detection information holding unit 62_2 is 62_3, the output of the remainder holding means 72_2 Is 72_3
The output of the table output information holding means 71_2 is 71_
3 are set respectively. The shifter 75_1 shifts the output of the surplus holding means 72_3 to the left by 11 bits.
The inverting means 76_1 inputs the output of the partial square root holding means 74_1, inverts the bits, adds 1 to the least significant bit, and outputs it. Also, the multiplicand generating means 77_1
Then, in the first iteration, the output of the partial square root holding means 74_1 is embedded from 2 ⁵⁶ to 2 ⁴⁴ and the other bits are output as zero. In the (R + S × T) computing means 78_1, the output of the shifter 75_1 is input as R, the output of the multiplicand generating means 77_1 is input as S, and the output of the inverting means 76_1 is input as T,
The calculation of (R + S × T) is executed. The (R + S × T) computing means 78_1 outputs 0FD5E125D3E000. On the other hand, the constant subtraction means 79_1 subtracts 1 from the LSB of the output of the partial square root holding means 74_1. The multiplexer 80_1 selects the output of the constant subtracting means 79_1 when the output of the (R + S × T) computing means 78_1 is negative, and selects the output of the partial square root holding means 74_1 otherwise. In this example, the output of the partial square root holding means 74_1 is selected by judging the above conditions.

Stage 4: First, the output of the (R + S × T) computing means 78_1 is supplied to the remainder holding means 72_4, and the 13 bits of the output of the multiplexer 80_1 are transferred from 2 ⁵⁶ to 2 ^44.
And the data in which the other bits are set to zero are merged square root holding means 82_4 and exception detection information holding means 62_3.
Output of 62_4 and output of exponent holding means 66_3 is 6
6_4, the output of the table output information holding means 71_3 is set to 71_4. Surplus holding means 72
0FD5E12 of the _first remainder R ₁ set to _4
5D3E000 is multiplied by 091A1 output from the table output information holding means 71_4 by the multiplication means 73_2, and the product 009021A0905CC1FE000 is output.

Stage 5: Introduction Multiplication Means 73_2
The output of 2 ⁷² to 2 ⁶⁰ of 0090 is the second partial square root of the code 1 bit and the data 12 bits to the partial square root holding means 74_2, the output of the exception detection information holding means 62_4 to 62_5 and the output of the exponent holding means 66_4. Is 66_
5, the output of the remainder holding means 72_4 is set to 72_5, the output of the merged square root holding means 82_4 is set to 82_5, and the output of the table output information holding means 71_4 is set to 71_5. In the shifter 75_2, the surplus holding means 72
Shift the output of _5 to the left by 11 bits. Inverting means 76
In _2, 0090 is inverted and becomes 1F6F, 1 is added as the least significant bit and output (R + S × T)
In the calculating means 78_2, 1F70 is calculated as a multiplier. On the other hand, in the multiplicand generating means 77_2,
With the output of the merging square holding means 82_5 shifted 1 bit to the left, embedded 12 bits except the first bit of the output 13-bit partial square root holding means 74_2 from 2 ⁴⁴ to 2 ^33, and outputs the 0E1012000000000. In the (R + S × T) computing means 78_2, the shifter 7
The output of 5_2 is input as R, the output of the multiplicand generating means 77_2 is input as S, the output of the inverting means 76_2 is input as T, and (R +
S * T) is executed. (R + S × T) computing means 7
8_2 outputs 1E672E9F000000. The multiplexer 80_2 has a partial square root holding unit 74_2.
Select the output of and output. In the adding means 81_2, the output of the merged square root holding means 82_5 and the multiplexer 80
For the output of _2, the 13 bits are aligned from 2 ⁴⁵ to 2 ³³ and input, and the addition is performed.
Output 000.

Stage 6: First, the output of (R + S × T) computing means 78_2 is to the remainder holding means 72_6, the output of the adding means 81_2 is to the merged square root holding means 82_6,
The output of the exception detection information holding means 62_5 is set to 62_6, the output of the exponent holding means 66_5 is set to 66_6, and the output of the table output information holding means 71_5 is set to 71_6. The 1E672E9F000000 of the second remainder R ₂ set in the remainder holding means 72_6 is multiplied by 091A1 output from the table output information holding means 71_6 by the multiplication means 73_3, and the product 0114B904C is obtained.
60FF000000 is output.

Stage 7: Introduction Multiplying Means 73_3
2 ⁷² 2 ⁶⁰ 0115 sign bit of the output of the rounded at 2 ^59, the partial square root holder 74_3 as the third partial square root of the data 12 bits, the output of the exception detection information holding unit 62_6 is to 62_7, Index holding means 66_6
Is output to 66_7, and the output of the surplus holding means 72_6 is 7
2_7, the output of the merged square root holding means 82_6 is 82_.
7, the output of the table output information holding means 71_6 is 71.
_7, respectively. The shifter 75_3 shifts the output of the surplus holding means 72_7 to the left by 11 bits. 0115 is inverted by the inverting means 76_3, and 1EE
The value becomes A, 1 is added as the least significant bit, and the value is output. In the (R + S × T) operation means 78_3, the operation is substantially performed by 1EEB as a multiplier. On the other hand, in the multiplicand generating means 77_3, the output of the merged square root holding means 82_7 is shifted to the left by 1 bit, and the leading 13 bits of the 13 bits output by the partial square root holding means 74_3 are excluded.
2 bits are embedded from 2 ³³ to 2 ²² and 0E102404
5400000 is output. (R + S × T) computing means 7
In 8_3, the output of the shifter 75_3 is input as R, the output of the multiplicand generating means 77_3 is input as S, and the output of the inverting means 76_3 is input as T, and the operation of (R + S × T) is executed. (R + S
× T) The calculating means 78_3 is C2056D11C0000.
Outputs 0. The multiplexer 80_3 selects and outputs the output of the constant subtraction unit 79_3. Adder 81_
In 3, the output of the merged square root holding means 82_7 and the output of the multiplexer 80_3 are aligned by inputting 13 bits from 2 ³⁴ to 2 ²² and input to perform addition.
Outputs 045000000.

Stage 8: First, the output of the (R + S × T) computing means 78_3 is to the remainder holding means 72_8, the output of the adding means 81_3 is to the merged square root holding means 82_8,
The output of the exception detection information holding means 62_7 is set to 62_8, the output of the exponent holding means 66_7 is set to 66_8, and the output of the table output information holding means 71_7 is set to 71_8. The multiplication unit 73_4 multiplies C2056D11C00000 of the third residue R ₃ set in the residue holding unit 72_8 by 091A1 output from the table output information holding unit 71_8, and the product 1DCBE1830
A5E9C00000 is output.

Stage 9: Introduction Multiplier 73_4
The output of 2 ⁷² to 2 ⁶⁰ of 1DCC after rounding at 2 ⁵⁹ is the partial square root holding means 74_4 as the fourth partial square root of the code 1 bit and data 12 bits, and the output of the exception detection information holding means 62_8 is 62_9. Index holding means 66_8
Is output to 66_9, and the output of the surplus holding means 72_8 is 7
2_9, the output of the merged square root holding means 82_8 is 82_.
9, the output of the table output information holding means 71_8 is 71.
_9, respectively. The shifter 75_4 shifts the output of the remainder holding means 72_9 to the left by 11 bits. 1DCC is inverted by the inverting means 76_4, and 023
3, the value is added with 1 as the least significant bit and output, and the (R + S × T) operation means 78_4 performs the operation at 0234 as a practical multiplier. On the other hand, in the multiplicand generating means 77_4, the output of the merged square root holding means 82_9 is shifted to the left by 1 bit, and the leading 13 bits of the 13 bits output by the partial square root holding means 74_4 are excluded.
2 bits are embedded from 2 ²² to 2 ¹¹ and 0E102408
Outputs A6E6000. (R + S × T) computing means 7
In 8_4, the output of the shifter 75_4 is input as R, the output of the multiplicand generating means 77_4 is input as S, and the output of the inverting means 76_4 is input as T, and the operation of (R + S × T) is executed. (R + S
× T) The calculating means 78_4 is E45EBEFB2B800.
Outputs 0. The multiplexer 80_4 selects and outputs the output of the constant subtraction unit 79_4. Adder 81_
4, the output of the merged square root holding means 82_9 and the output of the multiplexer 80_4 among the 13 bits are suppressed to 0 for the first 2 bits and 2 ²¹ to 2 ¹¹ for 11 bits.
Aligned with, input and add, 07081204
52E5000 is output.

Stage 10: Introduction (R + S × T)
The output of the computing means 78_4 is supplied to the remainder holding means 72_10,
The output of the adding means 81_4 is the merged square root holding means 82_1.
0, the output of the exception detection information holding means 62_9 is 62_1.
0, the output of the index holding means 66_9 is 66_10, and the output of the table output information holding means 71_9 is 71_10.
Are set respectively. E45EBEFB2B8 of the fourth residue R ₄ set in the residue holding means 72_8
000 is multiplied by 091A1 output from the table output information holding means 71_10 by the multiplication means 73_5, and the product 1
F04849C25F99DB8000 is output.

Stage 11: Introduction Multiplier 73_
The output from 2 ⁷² to 2 ⁶⁰ after being rounded at 2 ⁵⁹ of 5 is the partial square root holding means 74_5 as the fifth partial square root of the code 1 bit and the data 12 bits, and the output of the exception detection information holding means 62_10 is 62_11. , Index holding means 6
The output of 6_10 is 66_11, and the surplus holding means 72_1
The output of 0 is 72_11 and the merged square root holding means 82_1
The output of 0 is 82_11, and the table output information holding means 7
The output of 1_10 is set to 71_11. The shifter 75_5 shifts the output of the remainder holding means 72_11 to the left by 11 bits. 1F in the inverting means 76_5
05 is inverted to become 00FA, 1 is added as the least significant bit, and the result is output, and the (R + S × T) computing means 78
In _5, the calculation is substantially performed with 00FB as a multiplier. On the other hand, the multiplicand generator 77_5, with one bit shifts the output of the merging square holding means 82_11 left, embedded 12 bits except the first bit of the 13 bit output of the partial square root holding means 74_5 from 2 ¹¹ to 2 ^0, Outputs 0E102408A5CBF05.
The (R + S × T) calculating means 78_5 inputs the output of the shifter 75_5 as R, the output of the multiplicand generating means 77_5 as S, and the output of the inverting means 76_5 as T, and executes the calculation of (R + S × T). The (R + S × T) computing means 78_5 is 9
32D2104EF49E7 is output. The multiplexer 80_5 selects and outputs the output of the constant subtraction unit 79_5. The adding means 81_5 uses the merged square root holding means 8
Regarding the output of 2_11 and the output of the multiplexer 80_5, 13 bits are aligned from 2 ¹² to 2 ⁰ and input to perform addition, and 0708120452E5F04 is output.

Stage 12: Introduction (R + S × T)
The output of the calculation means 78_5 is supplied to the remainder holding means 72_12,
The output of the adding means 81_5 is the merged square root holding means 82_1.
2, the output of the exception detection information holding means 62_11 is 62_.
12, the output of the exponent holding means 66_11 is 66_12.
Are set respectively. In the exception detection means 83, if the input operand is negative from the output of the exception detection information holding means 62_12, it is detected as a data exception, and an exception has occurred to the instruction execution control unit outside the floating point vector square root operation unit. To notify. In this numerical example, the operand is positive, so no exception is detected.

As a final result, the exponent holding means 66 is 0 as the sign bit of 2 ⁶³ and the exponent part of 2 ⁶² to 2 ^52.
Output to 11 bits _12, from merging square holding means 2 ⁵³ outputs the 82_12 as mantissa from 2 ⁵¹ 2 ⁰ 2
² is selected and 5E3C2048114B97
It is output as C1 from the vector square root calculating device shown in FIGS.

(Fourth Embodiment) FIG. 7 is a block diagram of a fixed point square root arithmetic unit according to a fourth embodiment of the present invention. The fixed-point square root arithmetic unit of the present embodiment inputs a 64-bit fixed-point number in 2's complement notation, outputs a square root of 32 bits in 2's complement notation, and has a bit length of 12 as data of partial square root. There is a 1-bit overlap between the partial square roots. In FIG. 7, 101 is an input register,
102 is an exception detecting means, 103 is a normalized shift number detecting means, 104 is a normalizing means, 105 is a table information storing means, 106 is a shifter, 107 is a multiplexer, 108
Is a remainder holding means, 109 is a multiplication means, 110 is a multiplexer, 111 is a merged square root holding means, 112 is an inverting means, 113 is a multiplicand generating means, and 114 is (R + S × T).
Arithmetic means, 115 constant subtraction means, 116 multiplexer, 117 digit alignment means, 118 addition means, 11
9 is a digit adjustment shift number calculating means, and 120 is a digit adjusting means.

The operation of the fixed-point square root extraction arithmetic unit shown in FIG. 7 will be described below by using specific numerical examples. FIG. 8 shows a process in which an operand is input and then processed by each means. First, 0006 as an operand
Input 14CB57ED84AD and input register 1
It is set to 01. The exception detecting means 102 detects a data exception when the first two bits of the input operand are 10 or 11, and detects an overflow exception when the first two bits are 01, and the exception is sent to the instruction execution control unit outside the fixed point square root arithmetic unit. Notify that it is happening. In this numerical example (this assumption is omitted below), no exception is detected. The normalization shift number detecting means 103 detects the shift number for performing bit normalization in units of 2 bits, and 12 is output. The normalizing means 104 receives an instruction of the shift number 12 from the normalizing shift number detecting means 103, shifts the input data to the left by 12 bits, and outputs it. The table information storage means 105 has a normalization means 104.
12 ⁶³ bits from 2 ⁶³ to 2 ⁵² are input, and 0CFA4 is output. Further, as the least significant bit of this output, an inversion of the 2 ⁵¹ bits of the normalizing means 4 is added, but in this example, 0 is added, and the substantial multiplier in the multiplying means 109 becomes 0 CFA4. .. Multiplexer 10
In the case of 7, the normalizing means 10 in which 4-bit zero is added to the head 10
4 is selected, and this output is set in the surplus holding means 108. At this time, the merged square root holding means 111 is reset to zero. 0614CB5 by multiplying means 109
7ED84AD000 and 0CFA4 are multiplied,
The product of 04EEB5BE5D6270E1D4000 is obtained, and at the same time, the result of rounding the product at the 2 ⁶⁷ 's place in the first iteration and at the 2 ⁶⁸ 's place in the second and subsequent iterations is output to the multiplexer 110. Code 1 bit 13 bits 2 ⁸⁰ 2 ⁶⁸ multiplexers 110 in the multiplication means 109, selects as the first partial square root of the data 12 bits. The inverting means 112 inputs the partial square root, inverts the bits, adds 1 to the least significant bit, and outputs it. The sign of the first partial square root is positive and the sign bit is 0. In the first iteration, the multiplicand generating means 113 embeds the output of the multiplexer 110 from 2 ⁵⁴ to 2 ⁴² and outputs the other bits as zero. (R + S
XT) In the calculating means 114, the output of the remainder holding means 108 is R, the output of the multiplicand generating means 113 is S, and the inverting means 112.
The output of is input as T, and the operation of (R + S × T) is executed. (R + S × T) Output FFFF0 of the calculation means 114
317ED84AD000 is shifted to the left by 11 bits by the shifter 106, selected by the multiplexer 107, and set in the residue holding means 108. On the other hand, in the constant subtraction means 115, the output of the multiplexer 110 is L
Subtract 1 from SB. The multiplexer 116 is (R + S
× T) When the output of the calculation means 114 is negative, the output of the constant subtraction means 115 is selected, and in other cases, the output of the multiplexer 110 is selected. In the first iteration, the above condition is judged and the output of the constant subtracting means 115 is selected. The digit alignment means 117 performs digit alignment for merging the partial square roots in each iteration. Specifically, when the partial square root is negative, the first 2 bits of 13 bits of the output of the multiplexer 116 are suppressed to zero, and when the partial square root is positive, the 13 bits of the output of the multiplexer 116 are suppressed. , And outputs so as to shift so that the bit weights of the upper merged square roots are balanced. For the first partial square root, the input data is aligned from 2 ⁵⁴ to 2 ⁴² and output. In the adding means 118, the merged square root holding means 111
And the output of the digit alignment means 117 are input to perform addition, and the result is set in the merged square root holding means 111.

Next, the second iterative calculation is started. The output of the table information storage means 105 is the same as that of the first time after the second time. 0CFA in F818BF6C2568000000 of the _first residue R ₁ set in the residue holding means 108.
4 is multiplied by the multiplication means 109 to obtain the product F996F2A.
313870EA000000 is output. 1CCB sign bit from 2 ⁸¹ 2 ^69, data 12-bit 2
Selected by multiplexer 110 as the th partial square root. The inverting means 112 inverts 1 CCB, and
334, which is output with 1 added as the least significant bit, and the (R + S × T) computing means 114 substantially performs the computation at 0335 as the multiplier. On the other hand, in the multiplicand generating means 113, the output of the merged square root holding means 111 is shifted to the left by 1 bit, and the multiplexer 110
12 bits excluding the first bit of the 13 bits output from are embedded from 2 ⁴² to 2 ³¹
00 is output. In the (R + S × T) computing means 114, the output of the remainder holding means 108 is input as R, the output of the multiplicand generating means 113 is input as S, and the output of the inverting means 112 is input as T,
The calculation of (R + S × T) is executed. (R + S × T) Output of computing means 114 0001AAA45D6800000
Is shifted to the left by 11 bits by the shifter 106 and selected by the multiplexer 107.
Set to 8. The multiplexer 116 selects and outputs the output of the multiplexer 110, and the digit alignment means 1
At 17, the leading 2 bits of the 13-bit input are suppressed to zero and the 11 bits are aligned from 2 ⁴¹ to 2 ³¹ . In the adding means 118, the output of the merged square root holding means 111,
The output of the digit alignment means 117 is input to perform addition, and 1
Outputs 3BA65800000000. The merged square root holding means 111 sets the output of the adding means 118.

Next, the third iterative calculation is started. The output of the table information storage means 105 is the same as the first output. 0D5 of the _second residue R ₂ set in the residue holding means 108
522EB400000000 is multiplied by 0CFA4 by multiplying means 109 and the product 0AD061C697750 is obtained.
00000000 is output. 2 ⁸¹ to 2 ⁶⁹ of 056
8 is selected by the multiplexer 110 as the third partial square root of the code 1 bit and the data 12 bits. The inverting means 112 inverts 0568 to become 1A97, adds 1 as the least significant bit, and outputs (R
+ S × T) In the calculation means 114, substantially 1A as a multiplier
The operation is performed at 98. On the other hand, the multiplicand generating means 113
Then, the output of the merged square root holding unit 111 is shifted to the left by 1 bit, and the 12 bits except the leading bit of the 13 bits output from the multiplexer 110 are changed from 2 ³¹ to 2 2.
Embed in ²⁰ and output 02774CB56800000. In the (R + S × T) computing means 114, the output of the remainder holding means 108 is R, the output of the multiplicand generating means 113 is S,
The output of the inverting means 112 is input as T, and (R + S ×
The calculation of T) is executed. (R + S × T) computing means 114
The output of 00002C3685C000000 is output. The multiplexer 116 selects and outputs the output of the multiplexer 110, and the digit aligning means 117 aligns the 13-bit input from 2 ³² to 2 ²⁰ . Adding means 11
In 8, the output of the merged square root holding means 111 and the output of the digit alignment means 117 are input and addition is performed. 13BA65
Outputs D68000000. The digit adjustment shift number calculation means 119 outputs 1 from the normalized shift number detection means 103.
After shifting 2 from the right by 1 bit to 6, add a constant 25 and output 31, and the digit adjusting means 120 adds the means 11
The output of 8 is shifted to the right by 31 which is the instruction from the digit adjustment shift number calculation means 119, and the final result is 02774.
Output CBA.

(Embodiment 5) FIG. 9 is a block diagram of a fixed point square root arithmetic unit according to a fifth embodiment of the present invention. The fixed-point square root arithmetic unit of the present embodiment inputs a 64-bit fixed-point number in 2's complement notation, outputs a square root of 32 bits in 2's complement notation, and has a bit length of 12 as data of partial square root. There is a 1-bit overlap between the partial square roots. In FIG. 9, 201 is an input register,
Reference numeral 202 is an exception detection means, 203 is a normalized shift number detection means, 204 is a normalization means, 205 is a table information storage means, 206 is a shifter, 207 is a multiplexer, 208
Is a surplus holding means, 209 is a merged square root holding means, 210
Is a partial square root holding means, 211 is an inverting means, 212 is a multiplicand generating means, 213 to 215 are multiplexers, 2
16 is an (R + S × T) operation means, 217 is a multiplexer, 218 is a constant subtraction means, 219 is a multiplexer,
220 is a digit adjusting means, 221 is an adding means, 222 is a digit adjusting shift number calculating means, and 223 is a digit adjusting means.

The operation of the fixed-point square root extraction arithmetic unit shown in FIG. 9 will be described below by using specific numerical examples. The process from the input of the operand to the processing by each means is the same as that of FIG. 8 used in the fourth embodiment. First, 000614CB57ED84AD as an operand
Is input and set in the input register 201. In the exception detecting means 202, the first 2 bits of the input operand are 1
When it is 0 or 11, it is detected as a data exception, and when it is 01, it is detected as an overflow exception and notifies the instruction execution control unit outside the fixed-point square root arithmetic unit that an exception has occurred. In this numerical example (this assumption is omitted below), no exception is detected. The normalization shift number detecting means 203 detects the shift number for performing bit normalization in units of 2 bits, and 12 is output. In the normalizing means 204, the normalizing shift number detecting means 2
From 03, input the input data 1 in response to the instruction of shift number 12
Shift left by 2 bits and output. 12 bits from 2 ⁶³ to 2 ⁵² of the normalization means 204 are input to the table information storage means 205, and 0CFA4 is output. Further, as the least significant bit of this output, a bit obtained by inverting the 2 ⁵¹ bits of the normalizing means 204 is added, but in this example, 0 is added, and the (R + S × T) computing means 216 substantially outputs. The multiplier is 0CFA4. The multiplexer 207 selects the output of the normalizing means 204 having a 4-bit zero added to the head, and this output is set in the remainder holding means 208. At this time, the merged square root holding unit 209 is reset to zero. Multiplexers 213, 214, 21
5 selects “0”, the output of the remainder holding means 208, and the output of the table information storage means 205, respectively, and (R + S ×
T) 0614CB57ED84AD0 by the arithmetic means 216
The multiplication of 00 and 0CFA4 is performed and 04EEB5BE
At the same time that the product of 5D6270E1D4000 is obtained, the result of rounding the product at the 2 ⁶⁷ 's place in the first iteration and at the 2 ⁶⁸ 's place in the second and subsequent iterations is output to the multiplexer 217. The multiplexer 217 (R + S × T) code 1 bit 13 bits 2 ⁸⁰ 2 ⁶⁸ arithmetic means 216 selects as the first partial square root of the data 12 bits, the partial square root is set to the partial square root holder 210 It The inversion means 211 has a partial square root holding means 21.
The output of 0 is input, bit-inverted, the 4-bit code is extended to the upper bit, 1 is added to the least significant bit, and output. The multiplicand generating means 212 has 2 ^{54 in the} first iteration.
From 2 to 2 ⁴² , the output of the partial square root holding means 210 is embedded, and the other bits are output as zero. The multiplexers 213, 214, and 215 are the surplus holding means 2 respectively.
08 output, multiplicand generating means 212 output, inverting means 2
11 output is selected, and in the (R + S × T) computing means 216, the output of the multiplexer 213 is R, and the multiplexer 2
The output of 14 is input as S and the output of the multiplexer 215 is input as T, and the operation of (R + S × T) is executed. (R + S
XT) Output of operation means 216 FFFF0317ED84
AD000 is shifted to the left by 11 bits by the shifter 206, selected by the multiplexer 207, and set in the residue holding means 208. On the other hand, the constant subtraction means 21
8 is 1 from the LSB of the output of the partial square root holding means 210.
pull. The multiplexer 219 selects the output of the constant subtracting means 218 when the output of the (R + S × T) computing means 216 is negative, and the partial square root holding means 21 otherwise.
Select 0 output. In the first iteration, the above condition is judged and the output of the constant subtracting means 218 is selected. The digit alignment means 220 performs digit alignment for merging the partial square roots at each iteration. Specifically, when the partial square root is negative, the first 2 bits of the 13 bits of the output of the multiplexer 219 are suppressed to zero, and when the partial square root is positive, the 13 bits of the output of the multiplexer 219 are suppressed. ,
The shift is performed so that the weights of the bits of the upper merged square roots are balanced, and the result is output. For the first partial square root, the input data is aligned from 2 ⁵⁴ to 2 ⁴² and output.
The adding means 221 inputs the output of the merged square root holding means 209 and the output of the digit aligning means 220 to perform addition, and sets the result in the merged square root holding means 209.

Next, the second iterative calculation is started. The output of the table information storage unit 205 is the same as that of the first time even after the second time. The multiplexers 213, 214, 215 respectively select '0', F818BF6C2568000000 of the _first remainder R ₁ set in the remainder holding means 208, and the output 0CFA4 of the table information storage means 205,
The (R + S × T) computing means 216 executes (S × T),
The product F996F2A313870EA000000 is output. Code 1 bit 1CCB from 2 ⁸¹ 2 ^69, selected by multiplexer 217 as the second partial square root of the data 12 bits, the partial square root is set to the partial square root holding means 210. 1 CC in the reversing means 211
B is inverted, and the 4-bit code is extended to the higher order.
And 1 is added as the least significant bit and output,
In the (R + S × T) calculating means 216, the calculation is practically carried out at 00335 as a multiplier. On the other hand, in the multiplicand generating means 212, the output of the merged square root holding means 209 is set to the left by 1.
Bit-shifting and partial square root holding means 210
12 bits excluding the first bit of the 13 bits output from are embedded from 2 ⁴² to 2 ³¹
00 is output. Multiplexers 213, 214, 21
5 selects the output of the remainder holding means 208, the output of the multiplicand generating means 212, and the output of the inverting means 211, respectively.
In the (R + S × T) computing means 216, the multiplexer 21
3 is R, the output of the multiplexer 214 is S and the output of the multiplexer 215 is T, and (R + S ×
The calculation of T) is executed. (R + S × T) computing means 216
Output 0001AAA45D6800000 is shifter 2
It is shifted 11 bits to the left by 06, selected by the multiplexer 207, and set in the residue holding means 208. The multiplexer 219 selects and outputs the output of the partial square root holding unit 210, and the digit aligning unit 220 suppresses the leading 2 bits of the 13-bit input to zero and aligns 11 bits from 2 ⁴¹ to 2 ³¹ . . The addition unit 220 inputs the output of the merged square root holding unit 209 and the output of the digit alignment unit 220 to perform addition, and 13BA
Output 658000000. The merged square root holding means 209 sets the output of the adding means 221.

Next, the third iterative calculation is started. The output of the table information storage unit 205 is the same as the first output. The multiplexers 213, 214 and 215 are respectively
'0', 0D5522EB400000000 of the _second remainder R ₂ set in the remainder holding means 208, and the output 0CFA4 of the table information storage means 205 are selected, and (R
+ S × T) calculation means 216 executes (S × T), and the product 0
Outputs AD061C69775000000000. 0568 of 2 ⁸¹ to 2 ⁶⁹ is a code 1 bit, data 1
Multiplexer 2 as the 3rd partial square root of 2 bits
This partial square root is selected in 17 and set in the partial square root holding means 210. 056 in the inverting means 211
8 is inverted, 4-bit code is extended to the upper, and 1FA97
And 1 is added as the least significant bit and output,
In the (R + S × T) calculating means 216, 1FA98 is used as a multiplier. On the other hand, in the multiplicand generating means 212, the output of the merged square root holding means 209 is set to the left by 1.
Bit-shifting and partial square root holding means 210
12 bits excluding the first bit of the 13 bits output by are embedded from 2 ³¹ to 2 ²⁰ and 0274CB568000
00 is output. Multiplexers 213, 214, 21
5 selects the output of the remainder holding means 208, the output of the multiplicand generating means 212, and the output of the inverting means 211, respectively.
In the (R + S × T) computing means 216, the multiplexer 21
3 is R, the output of the multiplexer 214 is S and the output of the multiplexer 215 is T, and (R + S ×
The calculation of T) is executed. (R + S × T) computing means 216
Outputs 00002C3685C000000. The multiplexer 219 selects and outputs the output of the partial square root holding means 210, and the digit aligning means 220 aligns the 13-bit input from 2 ³² to 2 ²⁰ . Adder 221
13BA65D
Outputs 68000000. In the digit adjustment shift number calculation means 222, 12 from the normalized shift number detection means 203
After shifting 1 bit to the right by 6 and adding constant 25,
31 is output, and the digit adjusting means 223 shifts the output of the adding means 221 to the right by 31 which is the instruction from the digit adjusting shift number calculating means 222, and the final result is 02774CB.
Output A.

(Sixth Embodiment) FIGS. 10 and 11 are block diagrams of a fixed-point vector square root arithmetic unit according to a sixth embodiment of the present invention. The fixed-point vector square root computing unit of this embodiment inputs a 64-bit fixed-point number vector in 2's complement representation in element order and inputs 3 in 2's complement representation.
A 2-bit square root vector is output in element order, the bit length as the data of the partial square root is 12, and there is an overlap of 1 bit between the partial square roots. In FIGS. 10 and 11, 30
1 is an input register, 302_1 to 302_8 are exception detection information holding means, 303 is a normalized shift number detection means, 3
04_1 to 304_8 are normalized shift number holding means, 3
Reference numeral 05 is a normalization means, 306 is a normalization operand register, 307 is a table information storage means, and 308_2 to 3
08_6 is table output information holding means, 309_2 to 309_8 are remainder holding means, and 310_1 to 310_3
Are multiplication means, 311_1 to 311_3 are partial square root holding means, 312_1 to 312_3 are inverting means, 313
_1 to 313_3 are multiplicand generating means, 314_1 to 314_3 are (R + S × T) calculating means, 316_1 to 316_3 are constant subtracting means, and 317_1 to 317_3.
Are multiplexers, 318_1 to 318_2 are addition means, 319_4 to 319_8 are merged square root holding means,
320_1 to 320_3 are shifters, 321 is an exception detection means, 322 is a digit adjustment shift number calculation means, and 323 is a digit adjustment means.

The operation of the fixed-point vector square root arithmetic unit shown in FIGS. 10 and 11 will be described below by using specific numerical examples. The process in which the operand of one element of the vector is input and then processed by each means is the same as in FIG. 8 used in the fourth embodiment. The following describes how one element is processed for each stage.

Stage 0: First, 000614CB57ED84AD is input as an operand and set in the input register 301. The normalization shift number detecting means 303 detects the shift number for performing bit normalization in units of 2 bits, and 12 is output. In the normalizing means 305, the normalizing shift number detecting means 303
In response to the shift number 12 instruction, the input data is shifted left 12 bits and output.

Stage 1: Introduction Input Register 30
The first 2 bits of the output of 1 are exception detection information holding means 302
_1, the output of the normalization means 305 is set in the normalization operand register 306, and the output of the normalization shift number detection means 303 is set in the normalization shift number holding means 304_1. 12 bits from 2 ⁶³ to 2 ⁵² of the normalized operand register 306 are input to the table information storage means 307, and 0CFA4 is output. Further, 2 of the normalized operand register 306 is set as the least significant bit of this output.
^Although the one bit of ⁵¹ is inverted, it is added.
In this example, 0 is added to the multiplication means 310_1 to 310-3.
The actual multiplier at _3 is 0CFA4.

Stage 2: First, the output of the exception detection information holding means 302_1 is input to 302_2, the output of the normalized operand register 306 is prefixed with 4-bit zero, and the remainder holding means 309_2 is output to the table information storage means 307. Is table output information holding means 308_2
And the output of the normalized shift number holding means 304_1 is 304
It is set to _2. The multiplication means 310_1 multiplies 0614CB57ED84AD000 and 0CFA4 to obtain 04EEB5BE5D6270E1D4.
The product of 000 is required.

Stage 3: Introduction Multiplier 310_
13-bit sign bit of 1 of 2 ⁸⁰ to 2 ^68, the partial square root holding means 311_1 as the first partial square root of the data 12 bits, the output of the exception detection information holding unit 302_2 is 302_3, the output of the remainder holding means 309_2 Is 309_3, the output of the table output information holding means 308_2 is 308_3, and the normalized shift number holding means 304_
The two outputs are set to 304_3, respectively. The inverting means 312_1 inputs the output of the partial square root holding means 311_1, inverts the bits, and sets 1 to the least significant bit.
Is added and output. Also, the multiplicand generating means 313_1
Then, from 2 ⁵⁴ to 2 ⁴² , partial square root holding means 311_
The output of 1 is embedded and the other bits are output as zero. The (R + S × T) calculation means 314_1 inputs the output of the remainder holding means 309_3 as R, the output of the multiplicand generation means 313_1 as S, and the output of the inversion means 312_1 as T, and executes the calculation of (R + S × T). (R + S × T)
Output of calculation means 314_1 FFFF0317ED84A
D000 is shifted to the left by 11 bits by the shifter 320_1. On the other hand, the constant subtraction means 316_1 subtracts 1 from the LSB of the output of the partial square root holding means 311_1.
The multiplexer 317_1 has a constant subtracting means 316_1 when the output of the (R + S × T) computing means 314_1 is negative.
Of the partial square root holding means 311_1. In other cases, the output of the partial square root holding means 311_1 is selected. In this example, the output of the constant subtracting means 316_1 is selected by judging the above conditions.

Stage 4: Introduction Shifter 320_1
Of the output of the multiplexer 3 to the residue holding means 309_4.
Data for which 13 bits output from 17_1 are aligned from 2 ⁵⁴ to 2 ⁴² and the other bits are set to zero are merged square root holding means 319_4, the output of exception detection information holding means 302_3 is 302_4, and table output information holding means 308_.
The output of 3 is 308_4, and the normalized shift number holding means 30
The outputs of 4_3 are set to 304_4, respectively.
The first residue R set in the residue holding means 309_4
The F818BF6C2568000000 of 1 is multiplied by 0CFA4 output from the table output information holding means 308_4 by the multiplication means 310_2, and the product F996F2A31 is obtained.
3870EA000000 is output.

Stage 5: Introduction Multiplier 310_
1CCB sign bit from 2 ⁸¹ 2 ⁶⁹ output of 2, the partial square root holding means 311_2 as the second partial square root of the data 12 bits, exception detection information holding means 302_
4 to 302_5, the residue holding means 309_4 to 309_5, the merged square root holding means 319_4 to 319_5, and the table output information holding means 308_.
The output of 4 is 308_5, and the normalized shift number holding means 30
The outputs of 4_4 are set to 304_5, respectively.
1CCB is inverted by the inverting means 312_2, and
And 1 is added as the least significant bit and output,
In the (R + S × T) calculating means 314_2, the calculation is substantially carried out at 0335 as a multiplier. On the other hand, in the multiplicand generating means 313_2, the output of the merged square root holding means 319_5 is shifted to the left by 1 bit, and the 12 bits except for the leading bit of the 13 bits output by the partial square root holding means 311_2 are embedded from 2 ⁴² to 2 ³¹ . 027766
Outputs 580000000. In the (R + S × T) computing means 314_2, the output of the remainder holding means 309_5 is R,
The output of the multiplicand generating means 313_2 is S, and the inverting means 312 is
The output of _2 is input as T, and the operation of (R + S × T) is executed. (R + S × T) Output 0 of calculation means 314_2
001AAA45D6800000 is a shifter 320_2
Is shifted to the left by 11 bits. The multiplexer 317_2 selects the output of the partial square root holding means 311_2, suppresses the leading 2 bits to zero, and outputs 11 bits, and the adding means 318_1 outputs the merged square root holding means 31.
The output of 9_5 and the output of the multiplexer 317_2 are aligned from 2 ⁴¹ to 2 ³¹ , input to perform addition, and 13BA65800000000 is output.

Stage 6: Introduction Shifter 320_2
Output to the remainder holding means 309_6 and addition means 318_
The output of 1 is to the merged square root holding unit 319_6, the output of the exception detection information holding unit 302_5 is 302_6, the output of the table output information holding unit 308_5 is 308_6,
The output of the normalized shift number holding means 304_5 is 304_6.
Are set respectively. 0D5522EB40 of the second remainder R ₂ set in the remainder holding means 309_6
Table output information holding means 308_4 at 0000000
0CFA4 output by the above is multiplied by the multiplication means 310_3, and the product 0AD061C69775000000000000 is multiplied.
Is output.

Stage 7: Introduction Multiplier 310_
0568 the sign bit from the second output of the 2 ⁸¹ 2 ^69, the partial square root holder 311_3 as the third partial square root of the data 12 bits, exception detection information holding means 302_
The output of 6 is 302_7, the output of the remainder holding means 309_6 is 309_7, the output of the merged square root holding means 319_6 is 319_7, and the normalized shift number holding means 304_6.
Are set to 304_7, respectively. The inverting means 312_3 inverts 0568 to become 1A97, adds 1 as the least significant bit, and outputs (R
+ S × T) The calculating means 314_3 substantially calculates 1A98 as a multiplier. On the other hand, the multiplicand generating means 3
In 13_3, the output of the merged square root holding means 319_7 is shifted to the left by 1 bit, and the first bit of the 13 bits output by the partial square root holding means 311_3 is excluded.
2 bits are embedded from 2 ³¹ to 2 ²⁰ and 02774CB5
6800000 is output. (R + S × T) computing means 3
In 14_3, the output of the remainder holding means 309_7 is R, the output of the multiplicand generating means 313_3 is S, and the inverting means 312_3.
The output of is input as T, and the operation of (R + S × T) is executed. (R + S × T) Output 000 of the calculating means 314_3
02C3685C000000 is shifted to the left by 11 bits by the shifter 320_3. Multiplexer 31
7_3 selects the output of the partial square root holding means 311_3 and outputs 13 bits, and the adder 318_3 outputs the output of the merged square root holding means 319_7 and the multiplexer 3
For the output of 17_3, it is aligned from 2 ³² to 2 ²⁰ and is input and added, 13BA65D68000000
Is output.

Stage 8: Introduction Shifter 320_3
Output to the remainder holding means 309_8 and addition means 318_
The output of 2 is set to the merged square root holding unit 319_8, the output of the exception detection information holding unit 302_7 is set to 302_8, and the output of the normalized shift number holding unit 304_7 is set to 304_8. The exception detection unit 321 detects that the two bits output from the exception detection information holding unit 302_8 are 10 or 11 as a data exception, and detects 01 as an overflow exception, and controls the instruction execution outside the fixed-point vector square root operation unit. Notify the department that an exception has occurred. No exception is detected in this numerical example. The digit adjustment shift number calculating means 322 shifts 12 from the normalization shift number holding means 304_8 right by 1 bit to 6 and then adds a constant 25 and outputs 31, and the digit adjusting means 323 holds the merged square root holding means. The output of 319_8 is an instruction 31 from the digit adjustment shift number calculation means 322.
Only rightward and output the final result 02774CBA.

(Embodiment 7) FIG. 16 is a block diagram of a floating point square root arithmetic unit according to a seventh embodiment of the present invention. The floating point square root arithmetic unit of this embodiment is IEEE
The double precision floating point number of the E standard is input, the square root of the same double precision floating point number is output, the bit length as the data of the partial square root is 12, and there is an overlap of 1 bit between the partial square roots. In FIG. 16, 501 is an input register, 50
2 is exception detection means, 503 is exponential constant subtraction means, 504
Is a shifter, 505 is an exponent constant adding means, 506 is a leading bit adding circuit, 507 is a normalizing means, 508 is table information storing means, 509 is a shifter, 510 is a multiplexer, 511 is a surplus holding means, 512 is multiplying means, 513 Is a multiplexer, 514 is a merged square root holding means, 515 is an inverting means, 516 is a multiplicand generating means, 5
Reference numeral 17 is an (R + S × T) operation means, 518 is a constant subtraction means, 519 is a multiplexer, 520 is a digit alignment means,
Reference numeral 521 is an addition unit.

The operation of the floating point square root extraction arithmetic unit shown in FIG. 16 will be described below by using specific numerical examples. 17,
FIG. 18 shows a process in which an operand is input and then processed by each means. First, 7C88B89EAF092E9F is input as an operand and set in the input register 501. Exception detection means 502
Then, when the input operand is negative, it is detected as a data exception and the instruction execution control unit outside the floating point square root operation unit is notified that an exception has occurred. In this numerical example (hereinbelow, this assumption is omitted), since the operand is positive, no exception is detected. Exponent constant subtraction means 5 is applied to the exponents from 2 ⁶² to 2 ⁵² of the output of the input register 501.
After 3FF is subtracted by 03, the shifter 504 shifts it to the right by 1 bit, and the exponent constant adding means 505 adds 3FF again to obtain the resulting exponent. In the leading bit adding circuit 506, the input register 501
The leading bit 1 is added to the head of the mantissa part of 2 ⁵¹ to 2 ⁰ of the output of 1. In the normalizing means 507,
If the 2 ⁵² bits of the output of the input register 501 are 1, the input is shifted 12 bits to the left, and the input register 5
When 2 ⁵² bits of the output of 01 are 0, the input is shifted left 13 bits and output. Table information storage means 508
The 12 bits from 2 ⁶⁵ to 2 ⁵⁴ of the normalizing means 507 are input to and the output is 091A0. Further, as the least significant bit of this output, the inverted bit of 2 ⁵³ of the normalization means 507 is added, but in this example, 1 is added, and the substantial multiplier in the multiplication means 512 becomes 091A1. .. The multiplexer 510 selects the output of the normalizing means 507, and this output is set in the residue holding means 511. At this time, the merged square root holding unit 514 is reset to zero. 31713D5E12 by multiplying means 512
5D3E000 and 091A1 are multiplied, and 1C2
The product of 03BF9E0905CC1FE000 is obtained, and at the same time, the result of rounding the product at the 2 ^69th place in the first iteration and at the 2 ^70th place in the second and subsequent iterations is the multiplexer 5
It is output to 13. The multiplexer 513 selects 13 bits from 2 ⁸² to 2 ⁷⁰ of the multiplication means 512 as the first partial square root of the code 1 bit and the data 12 bits. The inverting means 515 inputs the partial square root, inverts the bits, adds 1 to the least significant bit, and outputs it. Further, in the multiplicand generating means 516, in the first iteration, the output of the multiplexer 513 is embedded from 2 ⁵⁶ to 2 ⁴⁴ and the other bits are output as zero. (R + S ×
T) In the calculating means 517, the output of the remainder holding means 511 is R, the output of the multiplicand generating means 516 is S, and the inverting means 515.
The output of is input as T, and the operation of (R + S × T) is executed. (R + S × T) Output 0000F of calculating means 517
D5E125D3E000 is shifted to the left by 11 bits by the shifter 509, selected by the multiplexer 510, and set in the surplus holding means 511. On the other hand, in the constant subtracting means 518, the output of the multiplexer 513 is L
Subtract 1 from SB. The multiplexer 519 uses (R + S
× T) When the output of the calculation means 517 is negative, the output of the constant subtraction means 518 is selected, and in other cases, the output of the multiplexer 513 is selected. In the first iteration, the above condition is judged and the output of the multiplexer 513 is selected.
The digit alignment means 520 performs digit alignment for merging the partial square roots at each iteration. Specifically, when the partial square root is negative, the leading 2 bits of the 13 bits of the output of the multiplexer 519 are suppressed to zero, and when the partial square root is positive, the 13 bits of the output of the multiplexer 519 are suppressed. , And outputs so as to shift so that the bit weights of the upper merged square roots are balanced. For the first partial square root, align the input data from 2 ⁵⁶ to 2 ⁴⁴ and output. In the adding means 521, the merged square root holding means 514
And the output of the digit alignment means 520 are input to perform addition, and the result is set in the merged square root holding means 514.

Next, the second iterative calculation is started. The output of the table information storage means 508 is the same as that of the first time even after the second time. 091A to 07EAF092E9F000000 of the _first residue R ₁ set in the residue holding means 511.
1 is multiplied by the multiplication means 512, and the product 04810D0 is obtained.
482E60FF000000 is output. 2 ⁸³ to 2 ⁷¹ 0090 is a code 1 bit, data 12 bits 2
Selected by multiplexer 513 as the th partial square root. The inversion means 515 inverts 0090 and
The result is F6F, 1 is added as the least significant bit, and the result is output, and the (R + S × T) operation means 517 substantially performs the operation at 1F70 as a multiplier. On the other hand, the multiplicand generating means 516 shifts the output of the merged square root holding means 514 to the left by 1 bit, and the multiplexer 510.
12 bits excluding the first bit of 13 bits output by are embedded from 2 ⁴⁴ to 2 ³³ , and 0E10120000000
00 is output. In the (R + S × T) computing means 517, the output of the remainder holding means 511 is input as R, the output of the multiplicand generating means 516 is input as S, and the output of the inverting means 515 is input as T,
The calculation of (R + S × T) is executed. (R + S × T) Output of computing means 517 0001E672E9F000000
Is shifted to the left by 11 bits by the shifter 509 and selected by the multiplexer 510.
Set to 1. The multiplexer 519 selects and outputs the output of the multiplexer 513, and the digit alignment means 5
At 20, the 13-bit input is aligned from 2 ⁴⁵ to 2 ³³ . The adding means 521 inputs the output of the merged square root holding means 514 and the output of the digit adjusting means 520, performs addition, and outputs 070812000000. The merged square root holding means 514 sets the output of the adding means 521.

Next, the third iterative calculation is started. The output of the table information storage means 508 is the same as that of the first time. 0F3 of the _second residue R ₂ set in the residue holding means 511
3974F800000000 is multiplied by 091A1 by multiplication means 512 and the product 08A5C826307F8 is obtained.
00000000 is output. 2 after rounding at ^70s
The multiplexer 513 selects 0115 from ⁸³ to 2 ^{71 as} the third partial square root of the code 1 bit and the data 12 bits. The inversion means 515 inverts 0115 to 1EEA, adds 1 as the least significant bit and outputs it, and the (R + S × T) operation means 517 substantially performs an operation with 1EEB as a multiplier. On the other hand, in the multiplicand generating means 516, the output of the merged square root holding means 514 is shifted to the left by 1 bit, and the 12 bits excluding the head bit of the 13 bits output from the multiplexer 513 are embedded from 2 ³³ to 2 ²² to 0E10240454.
000000 is output. (R + S × T) computing means 517
Then, the output of the remainder holding means 511 is R, and the multiplicand generating means 5
The output of 16 is input as S and the output of the inverting means 515 is input as T, and the calculation of (R + S × T) is executed. (R + S × T)
Output of arithmetic means 517 FFFC2056D11C000
00 is shifted to the left by 11 bits by the shifter 509, selected by the multiplexer 510, and set in the residue holding means 511. The multiplexer 519 selects and outputs the output of the constant subtraction means 518, and the digit alignment means 520 aligns the 13-bit input from 2 ³⁴ to 2 ²² . The adding means 521 inputs the output of the merged square root holding means 514 and the output of the digit adjusting means 520, performs addition, and outputs 070812045000000. The merged square root holding means 514 sets the output of the adding means 521.

Next, the fourth iterative calculation is started. The output of the table information storage means 508 is the same as that of the first time. E10 of the _third residue R ₃ set in the residue holding means 511
2B688E00000000 is multiplied by 091A1 by multiplication means 512 and the product EE5F0C1852F4E
00000000 is output. 2 after rounding at ^70s
The multiplexer 513 selects 1DCC from ⁸³ to 2 ^{71 as} the fourth partial square root of the code 1 bit and the data 12 bits. The inverting means 515 inverts 1DCC to become 0233, adds 1 as the least significant bit and outputs it, and the (R + S × T) operation means 517 substantially performs the operation at 0234 as a multiplier. On the other hand, in the multiplicand generating means 516, the output of the merged square root holding means 514 is shifted to the left by 1 bit, and the 12 bits excluding the head bit of the 13 bits output from the multiplexer 513 are embedded from 2 ²² to 2 ¹¹ to 0E102408A6.
Outputs E6000. (R + S × T) computing means 517
Then, the output of the remainder holding means 511 is R, and the multiplicand generating means 5
The output of 16 is input as S and the output of the inverting means 515 is input as T, and the calculation of (R + S × T) is executed. (R + S × T)
Output FFFE45EBEFB2B80 of computing means 517
00 is shifted to the left by 11 bits by the shifter 509, selected by the multiplexer 510, and set in the residue holding means 511. The multiplexer 519 selects and outputs the output of the constant subtracting means 518, and the digit aligning means 520 suppresses the leading 2 bits of the 13-bit input to zero and aligns 11 bits from 2 ²¹ to 2 ¹¹ .
The adding means 521 inputs the output of the merged square root holding means 514 and the output of the digit adjusting means 520, performs addition, and outputs 0708120452E5000. The merged square root holding means 514 sets the output of the adding means 521.

Next, the fifth iterative calculation is started. The output of the table information storage means 508 is the same as that of the first time. F22 of the _fourth residue R ₄ set in the residue holding means 511
F5F7D95C000000 is multiplied by 091A1 by multiplication means 512 to obtain product F82424E12FCCE
DC000000 is output. 2 after rounding at ^70s
1F05 of ⁸³ to 2 ⁷¹ is selected by the multiplexer 513 as the fifth partial square root of the code 1 bit and the data 12 bits. The inverting means 515 inverts 1F05 to become 00FA, adds 1 as the least significant bit and outputs it, and the (R + S × T) operation means 517 substantially performs the operation at 00FB as a multiplier. On the other hand, in the multiplicand generating means 516, the output of the merged square root holding means 514 is shifted to the left by 1 bit, and the 12 bits excluding the head bit of the 13 bits output from the multiplexer 513 are embedded from 2 ¹¹ to 2 ⁰ to 0E102408A5.
Outputs CBF05. (R + S × T) computing means 517
Then, the output of the remainder holding means 511 is R, and the multiplicand generating means 5
The output of 16 is input as S and the output of the inverting means 515 is input as T, and the calculation of (R + S × T) is executed. (R + S × T)
The calculation means 517 is FFF932D2104EF49E7.
Is output. The multiplexer 519 is a constant subtraction unit 5
The output of 18 is selected and output, and the digit alignment means 520 suppresses the leading 2 bits of the 13-bit input to zero and aligns 11 bits from 2 ¹⁰ to 2 ⁰ . Adder 5
In No. 21, the output of the merged square root holding unit 514 and the output of the digit alignment unit 520 are input and addition is performed.
It outputs 20452E5F04.

[0097] As a final result, the output to 11-bit exponent constant addition means 505 as the 0,2 ⁶² as a sign bit of the 2 ⁶³ 2 ⁵² exponent, addition means 521 as mantissa from 2 ⁵¹ 2 ⁰ 2 ⁵³ to 2 ² are selected and output as 5E3C2048114B97C1 from the square root arithmetic unit shown in FIG.

[0098]

As described above, according to the present invention, the remainder holding means, the table information storage means for storing the approximate reciprocal of the square root, the multiplication means for obtaining the partial square root, and the merged square roots obtained from the higher order by the iterative calculation from the remainder. By providing an (R−S × T) calculation means for obtaining the product of the partial square root and the partial square root, the bit length of the multiplier is smaller than the operand length for fixed-point numbers and the mantissa part for floating-point numbers. Since the square root calculation can be executed by using the multiplier, it is possible to provide a data processing device capable of simultaneously executing the multiplication instruction and the square root calculation instruction without causing a large increase in the amount of hardware. Also, the performance is comparable to that of the Kaihei arithmetic unit based on the Newton-Raphson method. Moreover, there is provided a partial square root calculating addition means for inputting the high order of the product output from the multiplying means or the (R−S × T) computing means and rounding it by one bit smaller than the least significant bit of the partial square root. Therefore, the calculation speed is improved.

When a guard bit, a round bit, and a sticky bit are used to round the square root of the result, LSB or less, one bit at a time, a guard bit and a round bit, and then the remaining bit and the remainder respectively. Since the bitwise OR is a sticky bit, it is a second effect of the present invention that it is not necessary to perform a check as compared with the Newton-Raphson method.

[Brief description of drawings]

FIG. 1 is a block diagram of a floating point square root arithmetic unit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing the output of each component in the previous figure by a specific numerical example.

FIG. 3 is a diagram showing an output of each component following the numerical example of the previous figure.

FIG. 4 is a block diagram of a floating point square root arithmetic unit according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a half of a floating point vector square root calculating unit according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing the other half of the floating point vector square root calculation device of the previous figure.

FIG. 7 is a block diagram of a fixed point square root arithmetic unit according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing the output of each component in the previous figure by a specific numerical example.

FIG. 9 is a block diagram of a fixed point square root arithmetic unit according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram showing a half part of a fixed-point vector square root calculation device according to a sixth embodiment of the present invention.

FIG. 11 is a block diagram showing the other half of the fixed-point vector square root computing device of the previous figure.

FIG. 12 is an internal block diagram of multiplication means of the floating point square root arithmetic unit according to the first embodiment of the present invention.

FIG. 13 is a diagram showing a relationship between a numerical aperture A and an approximate inverse M of a square root.

FIG. 14 is a diagram showing a relationship between A and A × M × M when the numerical aperture A is multiplied twice by the approximate inverse M of the square root.

FIG. 15 is a diagram for explaining improvement in accuracy of an approximate reciprocal M of a square root.

FIG. 16 is a block diagram of a floating point square root arithmetic unit according to a seventh embodiment of the present invention.

FIG. 17 is a diagram showing the output of each component in the previous figure by a specific numerical example.

FIG. 18 is a diagram showing the output of each component following the numerical example of the previous figure.

[Explanation of symbols]

 7 Normalization Means 8 Table Information Storage Means 10 Residue Holding Means 11 Multiplying Means 14 Merged Square Root Holding Means 15 Inversion Means 16 Multiplicand Generating Means 17 (R + S × T) Arithmetic Means

Claims (15)

[Claims] 1. A square root arithmetic unit for obtaining a square root of a floating point number input operand having 2 as an exponent base, and exponent constant subtraction means for removing exponent bias of the input operand, An exponent shift means for shifting the output of the exponent constant subtraction means to the right by one bit, an exponential constant addition means for adding an exponent bias to the output of the exponent shift means, and a value excluding the exponent bias is an even number. If it is an odd number, the normalizing means for shifting the mantissa of the input operand to the left by one bit, and the table information for indexing the approximate reciprocal of the square root using the upper bits of the output of the normalizing means as an address. A storage means, a surplus holding means for holding a surplus when iteratively obtains a square root by a constant number of bits from the upper order, and the surplus holding means. Multiply means for inputting the remainder to be output and the approximate reciprocal of the square root output from the table information storage means as a multiplicand and a multiplier, respectively, and a high order of the product output from the multiplying means are input. Adder means for calculating a partial square root for rounding by one bit smaller than the least significant bit of the partial square root; merged square root holding means for holding a merged square root obtained by merging the partial square roots in each iteration; Inversion means for inverting the partial square root output by the calculation addition means bit by bit, and a partial square root output by the partial square root calculation addition means by shifting the output of the merged square root holding means by 1 bit to the left. And a multiplicand generating means for generating a multiplicand, and the remainder output from the remainder holding means is overlapped between adjacent partial square roots from the bit length of the partial square root. And remainder shift means for shifting to the left by the number obtained by subtracting the appropriate bit length, the remainder after shifting to output of the remainder shift means (R)
And a multiplicand (S) output from the multiplicand generating means and a multiplier (T) output from the inverting means, respectively,
Any one of (R + S × T) arithmetic means for performing (R + S × T) arithmetic operation, an output of the normalization means and an output of the (R + S × T) arithmetic means as an input of the remainder holding means. A holding data switching multiplexer for selecting, a constant subtracting means for subtracting 1 from the least significant bit of the partial square root output by the partial square root calculating adder, and a portion output by the partial square root calculating adder A correction multiplexer for selecting any one of the square root and the output of the constant subtraction means and outputting it as a corrected partial square root, and the correction multiplexer for the merged square root output from the merged square root holding means. A digit aligning unit for performing digit alignment so that the corrected partial square roots output by the merge unit can be merged, and the merge output from the merge square root holding unit. No. arithmetic apparatus characterized by having a merging root calculation adding means for outputting the square root of the merged square root, which is updated by adding the output of the digit adjustment means. 2. A square root arithmetic unit for obtaining a square root of a floating-point number input operand having 2 as an exponent base, and exponent constant subtracting means for removing exponent bias of the input operand, An exponent shift means for shifting the output of the exponent constant subtraction means to the right by one bit, an exponential constant addition means for adding an exponent bias to the output of the exponent shift means, and a value excluding the exponent bias is an even number. If it is an odd number, the normalizing means for shifting the mantissa of the input operand to the left by one bit, and the table information for indexing the approximate reciprocal of the square root using the upper bits of the output of the normalizing means as an address. Storing means, remainder holding means for holding the remainder when the square root is iteratively determined by a certain number of bits in order from the higher order, the partial square root at each iteration Partial square root holding means for holding, and merged square root holding means for holding a merged square root obtained by merging the partial square roots in each iteration, and the residue output by the residue holding means is adjacent from the bit length of the partial square root. Remainder shift means for shifting to the left by a number obtained by subtracting the overlapping bit length between the partial square roots, inverting means for inverting the partial square root output by the partial square root holding means for each bit, and the merged square root holding A multiplicand generating means for generating a multiplicand by shifting the output of the means to the left by 1 bit and the partial square root output by the partial square root holding means; a constant zero and the residue after the shift output from the residue shift means. A remainder multiplexer for selecting any of the above, and a remainder output from the remainder holding means and an output of the multiplicand generating means. A multiplicand multiplexer for selecting any of the following, a multiplier multiplexer for selecting one of the approximate reciprocal of the square root output from the table information storage means and the output of the inverting means, and the remainder The output (R) of the multiplexer for the multiplicand, the output (S) of the multiplexer for the multiplicand, and the output (T) of the multiplexer for the multiplier are input to obtain (R + S × T).
And (R + S × T) computing means for performing the computation, and for selecting either the output of the normalizing means or the output of the (R + S × T) computing means as the input of the residue holding means. A holding data switching multiplexer and the upper part of the product output from the (R + S × T) computing means are input to perform rounding at a bit smaller than the least significant bit of the partial square root, and the rounded result is held in the partial square root. Adding means for calculating a partial square root, a constant subtracting means for subtracting 1 from the least significant bit of the partial square root output by the partial square root holding means, a partial square root output by the partial square root holding means, and A correction multiplexer for selecting any one of the outputs of the constant subtraction means and outputting it as a corrected partial square root, and an output from the merged square root holding means. Digit aligning means for performing digit alignment with respect to the merged square root so that the corrected partial square roots output by the correction multiplexer can be merged, and the merged square root output from the merged square root holding means and the output of the digit aligning means. And a merged square root calculation addition means for adding and to output an updated merged square root. 3. A square root arithmetic unit for obtaining a square root vector in an element order of an element order input operand of a vector consisting of a floating point number having a base of 2 as an exponent, the preprocessing being performed on the input operand. And the pre-processing unit for applying the partial square root, and the number of 1s equal to the number of repetitions when repeating the process of obtaining the partial square root until the bit length of the merged square root obtained by merging A main part having a main circuit from a second stage to a final stage; and a post-processing part for performing post-processing on the output of the main part, wherein the pre-processing part holds the input operand. An input register, exponential constant subtraction means for removing the exponent bias from the exponent part of the output of the input register, and holding the output of the exponential constant subtraction means Exponent holding means; normalizing means for shifting the mantissa part of the output of the input register to the left by 1 bit when the exponent bias is odd so that the value is even, and the normalizing means , A normalization operand register for holding the output of the exponent, an exponent shift means for shifting the output of the exponent holding means to the right by one bit, and an exponent constant for adding an exponent bias to the output of the exponent shift means. And a table information storage unit for indexing an approximate reciprocal of a square root with an upper bit of the output of the normalization operand register as an address. Exponent holding means respectively connected to the exponent constant adding means, the normalization operand register and the table information storing means of the preprocessing unit for synchronizing the operation. A remainder holding means and a table output information holding means, a multiplication means for inputting an output of the remainder holding means as a multiplicand and an output of the table output information holding means as a multiplier, and a multiplication, and a product output by the multiplication means. Of the partial square root, and rounding it by one bit smaller than the least significant bit of the partial square root, and a partial square root for holding the partial square root output by the partial square root calculating adder. Holding means, a remainder shift means for shifting the remainder output by the remainder holding means to the left by a number obtained by subtracting the bit length overlapping between adjacent partial square roots from the bit length of the partial square root, the partial square root holding means Inverting means for inverting the partial square root output by each bit, and generating a multiplicand from the partial square root output by the partial square root holding means. For generating a multiplicand, and a remainder (R) after the shift output from the remainder shift means.
And a multiplicand (S) output from the multiplicand generating means and a multiplier (T) output from the inverting means, respectively,
(R + S × T) calculation means for performing calculation of (R + S × T), constant subtraction means for subtracting 1 from the least significant bit of the partial square root output from the partial square root holding means, and the partial square root holding means And a correction multiplexer for selecting and outputting any one of the partial square root output by the above and the output of the constant subtracting means as a corrected partial square root, and the main circuits of the second and subsequent stages in the main part. Respectively, an exponent holding means, a remainder holding means, a merged square root holding means, and a table output information holding means for synchronizing pipeline operations, an output of the remainder holding means, a multiplicand, and an output of the table output information holding means. Is inputted as a multiplier to perform multiplication, and the higher order of the product output from the multiplying means is inputted and 1 bit smaller than the least significant bit of the partial square root. Adding means for calculating a partial square root for rounding at a certain place, a partial square root holding means for holding a partial square root output by the adding means for calculating a partial square root, and a partial square root for a remainder output by the remainder holding means. Remainder shift means for shifting to the left by a number obtained by subtracting the overlapping bit lengths between adjacent partial square roots of the partial square root, and inverting means for inverting the partial square root output by the partial square root holding means for each bit. And a multiplicand generating means for generating a multiplicand by shifting the output of the merged square root holding means to the left by 1 bit and the partial square root output by the partial square root holding means, and after the shift output by the remainder shift means. Remainder (R)
And a multiplicand (S) output from the multiplicand generating means and a multiplier (T) output from the inverting means, respectively,
(R + S × T) calculation means for performing calculation of (R + S × T), constant subtraction means for subtracting 1 from the least significant bit of the partial square root output from the partial square root holding means, and the partial square root holding means Of the partial square root to be output and the output of the constant subtracting means to select and output as a corrected partial square root, and for the merged square root output from the merged square root holding means, Digit aligning means for performing digit alignment so that the corrected partial square roots output by the compensation multiplexer can be merged, and the merged square root output from the merged square root holding means and the output of the digit aligning means are added to update. And a merged square root calculating addition means for outputting the merged square root, and in the second and subsequent main circuits, the exponent holding means is the preceding stage. The index holding means, said residue retaining means preceding (R + S
XT) the calculating means, the merged square root holding means is the first-stage correction multiplexer in the second stage, the merged square root calculation adding means of the previous stage in the third and subsequent stages, and the table output information holding means is the previous stage. Of the table output information holding means, and the post-processing section is connected to the exponent holding means and the merged square root calculating addition means of the main circuit at the final stage in the main part in order to synchronize the pipeline operation. And a square root holding means for storing a square root. 4. A square root arithmetic unit for obtaining a square root of a fixed-point number input operand, comprising shift number detecting means for obtaining a shift number when bit-normalizing the input operand in units of 2 bits. Normalizing means for shifting the input operand to the left by the shift number output by the shift number detecting means, and table information for indexing an approximate reciprocal of a square root with the upper bits of the output of the normalizing means as an address. A storage means, a surplus holding means for holding a surplus when iteratively obtains a square root by a certain number of bits from the upper order, a surplus output from the surplus holding means, and a surplus output from the table information storage means. Multiplying means for inputting the approximate reciprocal of the square root as a multiplicand and a multiplier, respectively, and a product output from the multiplying means. Partial square root calculating and adding means for inputting the high order and rounding it by one bit smaller than the least significant bit of the partial square root, and merged square root holding means for holding the merged square root obtained by merging the partial square roots at each iteration An inversion means for inverting the partial square root output from the partial square root calculation adding means bit by bit; and an output of the merged square root holding means left shifted by 1 bit to obtain the partial square root calculation addition means. Multiplicand generating means for generating a multiplicand by the output partial square root, a remainder (R) output by the remainder holding means, a multiplicand (S) output by the multiplicand generating means, and a multiplier output by the inverting means. (R + S × T) calculating means for inputting (T) and (R + S × T), and the output of the (R + S × T) calculating means is the bit length of the partial square root. Shift means for shifting to the left by a number obtained by subtracting the bit length overlapping between adjacent partial square roots, and any one of the output of the normalizing means and the output of the shift means as an input of the residue holding means. A holding data switching multiplexer for selecting whether or not, a constant subtracting means for subtracting 1 from the least significant bit of the partial square root output by the partial square root calculating adder, and an output by the partial square root calculating adder A correction multiplexer for selecting and outputting one of the partial square root and the output of the constant subtracting means as a corrected partial square root, and the correction square for the merged square root output from the merged square root holding means. Digit aligning means for performing digit alignment so that the corrected partial square roots output from the multiplexer can be merged, and the merged square root holding means. And a merged square root calculation addition for outputting the merged square root updated by adding the merged square root output from the digit alignment means and the output of the digit alignment means, and the merged square root calculation addition for obtaining the square root of the final result. A digit adjustment shift number calculation means for calculating the shift number of the right shift to be applied to the merged square root output from the means from the output of the shift number detection means, and the merged square root output from the merged square root calculation addition means. A square root arithmetic unit comprising: a digit adjusting unit for performing a right shift according to the number of shifts output by the adjusting shift number calculating unit and outputting a square root of a final result. 5. The square root computing device according to claim 4, wherein an output of the merged square root holding means is an input of the digit adjusting means. 6. A square root arithmetic unit for obtaining a square root of a fixed-point number input operand, wherein a normalized shift number detection for obtaining a shift number when bit-normalizing the input operand in units of 2 bits. Means, a normalization means for shifting the input operand to the left by the shift number output by the normalization shift number detection means, and an approximate reciprocal of square root with the upper bit of the output of the normalization means as an address. Table information storage means, a square root holding means for holding a remainder when iteratively obtaining a square root by a certain number of bits from a higher order, a partial square root holding means for holding a partial square root at each iteration, And a merged square root holding means for holding a merged square root obtained by merging the partial square roots in each iteration, and a unit for outputting the partial square root holding means Multiplicand generating means for generating a multiplicand by inverting means for inverting the square root for each bit, and shifting the output of the merged square root holding means by 1 bit to the left, and the partial square root output by the partial square root holding means. A remainder multiplexer for selecting one of a constant zero and a remainder output from the remainder holding means, and a remainder output from the remainder holding means and an output of the multiplicand generating means. A multiplicand multiplexer for selecting any one, a multiplier multiplexer for selecting one of the approximate reciprocal of the square root output from the table information storage means and the output of the inverting means, and the remainder The output (R) of the multiplexer, the output (S) of the multiplexer for the multiplicand, and the output (T) of the multiplexer for the multiplier are respectively Input each, (R + S × T)
And (R + S × T) operation means for performing the above operation, and the output of the (R + S × T) operation means is shifted to the left by a number obtained by subtracting the bit length overlapping between adjacent partial square roots from the bit length of the partial square root. A shift means for switching, a held data switching multiplexer for selecting one of the output of the normalizing means and the output of the shift means as an input of the remainder holding means, and (R + S × T) Partial square root calculation addition means for inputting the upper product of the output of the arithmetic means, rounding it by one bit smaller than the least significant bit of the partial square root, and giving the rounding result to the partial square root holding means, Constant subtraction means for subtracting 1 from the least significant bit of the partial square root output by the partial square root holding means; partial square root output by the partial square root holding means and the constant subtraction means A correction multiplexer for selecting any one of the outputs of the means and outputting it as a correction portion square root; and a correction portion output by the correction multiplexer for the merged square root output from the merged square root holding means. A digit aligning means for performing digit alignment so that the square roots can be merged, and a merged square root output from the merged square root holding means and an output of the digit aligning means are added to output an updated merged square root. To calculate the shift number of the right shift to be applied to the merged square root output from the merged square root calculation addition means and the merged square root calculation addition means to obtain the square root of the final result from the output of the normalized shift number detection means. Digit adjustment shift number calculation means, and the merged square root output from the merged square root calculation addition means is the digit adjustment shift number calculation means. Perform a right shift by the shift number outputted, square root operation apparatus characterized by having a digit adjusting means for outputting the square root of the final result. 7. The square root computing device according to claim 6, wherein an output of the merged square root holding means is an input of the digit adjusting means. 8. A square root arithmetic unit for obtaining a square root vector in an element order of input operands of a vector consisting of fixed point numbers, the preprocessing unit for preprocessing the input operands. And when the process of obtaining the partial square root is repeated until the bit length of the merged square root obtained by merging the partial square roots is equal to or larger than the bit length of the square root of the result to be obtained, the number of iterations from the first stage to the last stage A main section having a main circuit; and a post-processing section for performing post-processing on the output of the main section, wherein the pre-processing section includes an input register for holding the input operand, and the input register. Shift number detecting means for obtaining a shift number when bit-normalizing the output of 2 to 2 bits, and a shift output by the normalizing shift number detecting means. A normalizing means for shifting the output of the input register to the left by a number; a normalizing operand register for holding the output of the normalizing means; and a holding means for holding the output of the normalized shift number detecting means. And a table information storage unit for indexing the approximate reciprocal of the square root using the higher order bits of the output of the normalized operand register as an address, and the main circuit of the first stage in the main section. Is a residue holding means connected to the normalized operand register of the preprocessing section, the table information storage means, and the normalized shift number holding means for synchronizing the pipeline operation,
Table output information holding means and normalized shift number holding means, multiplication means for inputting the output of the remainder holding means as a multiplicand and the output of the table output information holding means as a multiplier, and performing multiplication, and In order to hold the partial square root output unit of the partial square root calculation addition unit for inputting the high-order product to be output and rounding it by one bit smaller than the least significant bit of the partial square root Partial square root holding means, inversion means for inverting the partial square root output by the partial square root holding means for each bit, and multiplicand generating means for generating a multiplicand from the partial square root output by the partial square root holding means, , The remainder (R) output by the remainder holding means, the multiplicand (S) output by the multiplicand generating means, and the multiplier output by the inverting means. (R + S × T) calculating means for inputting (T) and (R + S × T), and the output of the (R + S × T) calculating means is adjacent to the bit length of the partial square root. Shift means for shifting to the left by a number obtained by subtracting the overlapping bit length between the square roots, constant subtraction means for subtracting 1 from the least significant bit of the partial square root output by the partial square root holding means, and the partial square root A correction multiplexer for selecting either the partial square root output by the holding means or the output of the constant subtraction means and outputting it as the corrected partial square root is provided. The main circuits respectively include a residue holding unit, a merged square root holding unit, a table output information holding unit, a normalized shift number holding unit, and a residue holding unit for synchronizing pipeline operations. 1 is smaller than the least significant bit of the partial square root by inputting the force as a multiplicand and the output of the table output information holding means as a multiplier and performing multiplication, and inputting the high order of the product output by the multiplying means. Adder for calculating a partial square root for rounding at a place, a partial square root holding means for holding a partial square root output by the adder for calculating a partial square root, and a partial square root output by the partial square root holding means Inverting means for inverting each, and a multiplicand generating means for generating a multiplicand by shifting the output of the merged square root holding means to the left by 1 bit and the partial square root output by the partial square root holding means, The remainder (R) output from the remainder holding means, the multiplicand (S) output from the multiplicand generating means, and the multiplier (T) output from the inverting means are respectively input. And (R + S × T) computing means for performing (R + S × T) computation, and the output of the (R + S × T) computing means from the bit length of the partial square root to the overlapping bit length between adjacent partial square roots. Shift means for shifting to the left by the subtracted number, constant subtraction means for subtracting 1 from the least significant bit of the partial square root output by the partial square root holding means, and partial square root output by the partial square root holding means A correction multiplexer for selecting any one of the outputs of the constant subtraction means and outputting it as a corrected partial square root; and an output of the correction multiplexer for the merged square root output from the merged square root holding means. A digit aligning means for performing digit alignment so that the corrected partial square roots can be merged, and the merged square root and the digit output from the merged square root holding means. And a merged square root calculation addition means for adding the output of the matching means to output an updated merged square root, and in the main circuit of the second and subsequent stages, the surplus holding means is the shift means of the preceding stage. The merged square root holding means is the correction multiplexer of the first stage in the second stage, the merged square root calculation addition means of the preceding stage in the third and subsequent stages, and the table output information holding means is the table output information holding means of the preceding stage. Further, the normalized shift number holding means is connected to the normalized shift number holding means of the preceding stage, and the post-processing unit merges the main circuit of the final stage in the main unit in order to synchronize the pipeline operation. Combined square root holding means and normalized shift number holding means respectively connected to the adding means for square root calculation and the normalized shift number holding means, and for calculating the merged square root in order to obtain the square root of the final result. Digit adjustment shift number calculation means for calculating the shift number of the right shift to be applied to the merged square root output from the addition means from the output of the normalized shift number detection means, and the merged square root output from the merged square root calculation addition means And a digit adjusting means for performing a right shift according to the shift number output by the digit adjusting shift number calculating means and outputting the square root of the final result. 9. A square root arithmetic unit for calculating a square root of a floating-point number input operand having 2 as an exponent base, and exponential constant subtraction means for eliminating exponent bias of the input operand. An exponent shift means for shifting the output of the exponent constant subtraction means to the right by one bit, an exponential constant addition means for adding an exponent bias to the output of the exponent shift means, and a value excluding the exponent bias is an even number. If it is an odd number, the normalizing means for shifting the mantissa of the input operand to the left by one bit, and the table information for indexing the approximate reciprocal of the square root using the upper bits of the output of the normalizing means as an address. A storage means, a surplus holding means for holding a surplus when iteratively obtains a square root by a constant number of bits from the upper order, and the surplus holding means. Multiply means for inputting the remainder to be output and the approximate reciprocal of the square root output from the table information storage means as a multiplicand and a multiplier, respectively, and a high order of the product output from the multiplying means are input. Adder means for calculating a partial square root for rounding by one bit smaller than the least significant bit of the partial square root; merged square root holding means for holding a merged square root obtained by merging the partial square roots in each iteration; Inversion means for inverting the partial square root output by the calculation addition means bit by bit, and a partial square root output by the partial square root calculation addition means by shifting the output of the merged square root holding means by 1 bit to the left. A multiplicand generating means for generating a multiplicand, a remainder (R) output by the remainder holding means, and a multiplicand (S) output by the multiplicand generating means. The multiplier (T) output from the inverting means is respectively input, and the (R + S × T) operation means for performing the operation of (R + S × T), and the output of the (R + S × T) operation means are partial square roots. Calculation result shifting means for shifting to the left by a number obtained by subtracting the bit length overlapping between adjacent partial square roots from the output of the normalizing means and the calculation result shifting means as inputs to the residue holding means. A holding data switching multiplexer for selecting any one of the outputs of the above, a constant subtracting means for subtracting 1 from the least significant bit of the partial square root output by the partial square root calculating adding means, and the partial square root A correction multiplexer for selecting either the partial square root output by the calculation addition means or the output of the constant subtraction means and outputting it as a corrected partial square root, A digit aligning unit for performing digit alignment to merge the corrected partial square root output from the correction multiplexer with respect to the merged square root output from the merged square root holding unit, and the merged square root holding unit output. A square root calculation device for adding a merged square root and an output of the digit aligning means to output an updated merged square root. 10. A square root arithmetic unit for calculating a square root of a floating-point number input operand having 2 as an exponent base, and exponent constant subtraction means for removing exponent bias of the input operand, An exponent shift means for shifting the output of the exponent constant subtraction means to the right by one bit, an exponential constant addition means for adding an exponent bias to the output of the exponent shift means, and a value excluding the exponent bias is an even number. If it is an odd number, the normalizing means for shifting the mantissa of the input operand to the left by one bit, and the table information for indexing the approximate reciprocal of the square root using the upper bits of the output of the normalizing means as an address. Storing means, remainder holding means for holding the remainder when the square root is iteratively obtained by iterating by a certain number of bits from the top, partial square root at each iteration And a merged square root holding means for holding a merged square root obtained by merging the partial square roots in each iteration, and a partial square root output by the partial square root holding means is inverted bit by bit. And a multiplicand generating means for generating a multiplicand by shifting the output of the merged square root holding means to the left by 1 bit and the partial square root output by the partial square root holding means, and a constant zero and the remainder. A remainder multiplexer for selecting one of the remainder output from the holding means, and a remainder output from the remainder holding means and an output of the multiplicand generating means Selects one of the multiplicand multiplexer, the approximate reciprocal of the square root output from the table information storage means, and the output of the inversion means. And the multiplier multiplexer for, the output of the remainder multiplexer (R), the output of the multiplicand multiplexer (S), and each input and output of the multiplier multiplexer (T), (R + S × T)
And (R + S × T) operation means for performing the above operation, and the output of the (R + S × T) operation means is shifted to the left by a number obtained by subtracting the bit length overlapping between adjacent partial square roots from the bit length of the partial square root. An operation result shift means for performing the operation, and a held data switching multiplexer for selecting one of the output of the normalization means and the output of the operation result shift means as an input of the remainder holding means; R + S × T) For calculating the partial square root for inputting the upper product of the output from the calculating means, rounding the result by one bit smaller than the least significant bit of the partial square root, and giving the rounding result to the partial square root holding means. Adder means, a constant subtraction means for subtracting 1 from the least significant bit of the partial square root output by the partial square root holding means, and a partial square root output by the partial square root holding means A correction multiplexer for selecting either the root or the output of the constant subtraction means and outputting it as a corrected partial square root; and the correction multiplexer for the merged square root output from the merged square root holding means. A digit aligning means for performing digit alignment so as to merge the corrected partial square roots, and a merged square root updated by adding the merged square root output from the merged square root holding means and the digit aligning means output. And a square root calculation adding means for outputting. 11. A square root arithmetic unit for obtaining a square root vector in element order for an element-order input operand of a vector consisting of floating-point numbers with 2 as an exponent base, the pre-processing being performed on the input operand. And the pre-processing unit for applying the partial square root, and the number of 1s equal to the number of repetitions when repeating the process of obtaining the partial square root until the bit length of the merged square root obtained by merging A main part having a main circuit from the second stage to the final stage; and a post-processing part for performing post-processing on the output of the main part, wherein the pre-processing part holds the input operand. An input register, exponential constant subtraction means for removing the exponent bias from the exponent part of the output of the input register, and an output for the exponential constant subtraction means. Exponent holding means, and normalizing means for shifting the mantissa part of the output of the input register to the left by one bit when the exponent bias is odd so that the value becomes even. A normalization operand register for holding the output of the exponent, an exponent shift means for shifting the output of the exponent holding means to the right by one bit, and an exponent for adding an exponent bias to the output of the exponent shift means. And a table information storage unit for indexing the approximate reciprocal of the square root using the upper bits of the output of the normalized operand register as an address. The main circuit of the first stage in the main unit is a pipe In order to synchronize the line operation, the exponent holding means respectively connected to the exponent constant adding means, the normalized operand register and the table information storing means of the preprocessing section. A remainder holding means and a table output information holding means, a multiplication means for inputting the output of the remainder holding means as a multiplicand and an output of the table output information holding means as a multiplier, and a multiplication means, and an output of the multiplication means. Partial square root calculating and adding means for inputting the upper part of the product and rounding it by one bit smaller than the least significant bit of the partial square root; and a part for holding the partial square root output from the partial square root calculating and adding means. Square root holding means, inverting means for inverting the partial square root output by the partial square root holding means for each bit, multiplicand generating means for generating a multiplicand from the partial square root output by the partial square root holding means, and The remainder (R) output by the remainder holding means, the multiplicand (S) output by the multiplicand generating means, and the multiplier (T) output by the inverting means. And (R + S × T) calculating means for calculating (R + S × T) and the output of the (R + S × T) calculating means from the bit length of the partial square root to the adjacent partial square roots. Operation result shifting means for shifting to the left by the number obtained by subtracting the overlapping bit length, constant subtraction means for subtracting 1 from the least significant bit of the partial square root output by the partial square root holding means, and the partial square root holding A correction multiplexer for selecting one of the partial square root output by the means and the output of the constant subtraction means and outputting it as a corrected partial square root. The circuits respectively store exponent holding means, remainder holding means, merged square root holding means, table output information holding means, and output of the remainder holding means for synchronizing pipeline operations. Number, the multiplication means for inputting the output of the table output information holding means as a multiplier, and the multiplication of the product output by the multiplication means, and inputting the higher order one bit less than the least significant bit of the partial square root. Partial square root calculation adding means for rounding, partial square root holding means for holding the partial square root output by the partial square root calculation adding means, and partial square root output by the partial square root holding means for each bit Inversion means for inverting, an output of the merged square root holding means is shifted to the left by 1 bit, and a multiplicand generating means for generating a multiplicand with the partial square root output by the partial square root holding means; and the remainder holding The remainder (R) output from the means, the multiplicand (S) output from the multiplicand generating means, and the multiplier (T) output from the inverting means are respectively input, and ( (R + S × T) operation means for performing an operation of (R + S × T), and a number obtained by subtracting the bit length of the partial square root from the output of the (R + S × T) operation means Shift means for shifting only to the left, constant subtraction means for subtracting 1 from the least significant bit of the partial square root output by the partial square root holding means, partial square root output by the partial square root holding means, and A correction multiplexer for selecting one of the outputs of the constant subtraction means and outputting it as a corrected partial square root, and an output of the correction multiplexer for the merged square root output from the merged square root holding means. Digit aligning means for performing digit alignment so that the corrected partial square roots can be merged; the merged square root output from the merged square root holding means; Merged square root calculation addition means for adding the output of the matching means and outputting the updated merged square root, and in the main circuit of the second and subsequent stages, the exponent holding means is the exponent holding means of the preceding stage. In addition, the remainder holding means is the operation result shift means of the previous stage, and the merged square root holding means is 1 in the second stage.
The table output information holding unit is connected to the correction multiplexer of the first stage, and the merged square root calculation adding unit of the previous stage in the third and subsequent stages, and the table output information holding unit of the previous stage is connected to the post-processing unit. In order to synchronize the line operation, there is provided an exponent holding means and a merged square root holding means respectively connected to the exponent holding means and the merged square root calculating addition means of the final stage main circuit in the main part. Arithmetic unit. 12. A square root arithmetic unit for obtaining a square root for an input operand normalized to a unit of 2 bits, wherein table information for indexing an approximate reciprocal of a square root with an upper bit of the input operand as an address. A storage means, a surplus holding means for holding a surplus when iteratively obtains a square root by a certain number of bits from the upper order, a surplus output from the surplus holding means, and a surplus output from the table information storage means. Approximate reciprocal of square root is input as a multiplicand and a multiplier, respectively, and a multiplying unit for performing multiplication, and an upper part of a product output from the multiplying unit is input to round one bit less than the least significant bit of the partial square root. Adder means for calculating a partial square root for performing, and a merged square root holding means for holding a merged square root obtained by merging the partial square roots in each iteration. An inversion means for inverting the partial square root output from the partial square root calculation adding means for each bit; and an output of the partial square root calculation adding means by shifting the output of the merged square root holding means by 1 bit to the left. And a multiplicand generating means for generating a multiplicand with the partial square root, and the remainder output from the remainder holding means is shifted to the left by a number obtained by subtracting the bit length overlapping between adjacent partial square roots from the bit length of the partial square root. For inputting the post-shifting remainder (R) output from the shift means, the multiplicand (S) output from the multiplicand generating means, and the multiplier (T) output from the inverting means. , (R + S
(R + S × T) operation means for performing the operation of (× T), and for selecting either of the input operand and the output of the (R + S × T) operation means as an input of the remainder holding means. A held data switching multiplexer, a constant subtraction unit for subtracting 1 from the least significant bit of the partial square root output by the partial square root calculation addition unit, a partial square root output by the partial square root calculation addition unit, and the constant subtraction A correction multiplexer for selecting any one of the outputs of the means and outputting it as a correction portion square root; and a correction portion output by the correction multiplexer for the merged square root output from the merged square root holding means. Digit aligning means for performing digit alignment so that the square roots can be merged, and the merged square root output from the merged square root holding means No. arithmetic apparatus characterized by having a merging root calculation adding means for outputting the merged square root, which is updated by adding the output of the digit adjustment means. 13. A square root arithmetic unit for obtaining a square root for an input operand normalized to a unit of 2 bits, wherein table information for indexing an approximate reciprocal of a square root by using an upper bit of the input operand as an address. Storing means, remainder holding means for holding the remainder when the square root is iteratively determined by a certain number of bits from the top, partial square root holding means for holding the partial square root at each iteration, and each iteration In the merged square root holding means for holding the merged square root obtained by merging the partial square roots in, and the remainder output by the remainder holding means is subtracted from the bit length of the partial square root minus the bit length overlapping between adjacent partial square roots. Shift means for shifting to the left, inverting means for inverting the partial square root output by the partial square root holding means for each bit, A multiplicand generating means for generating a multiplicand by shifting the output of the combined square root holding means to the left by 1 bit and the partial square root output by the partial square root holding means, and a constant zero and after the shift output from the shifting means. A remainder multiplexer for selecting one of the remainders, and a multiplicand multiplexer for selecting one of the remainder output from the remainder holding means and the output of the multiplicand generating means, A multiplier multiplexer for selecting one of the approximate reciprocal of the square root output from the table information storage means and the output of the inverting means, the output of the remainder multiplexer (R), and the multiplicand multiplexer (S + T) and the output (T) of the multiplier multiplexer are input to obtain (R + S × T)
(R + S × T) arithmetic means for performing the arithmetic operation, and holding data switching for selecting either of the input operand as the input of the remainder holding means and the output of the (R + S × T) arithmetic means. Multiplexer and the (R + S × T) computing means output the higher order of the product, rounds the result by one bit smaller than the least significant bit of the partial square root, and gives the rounding result to the partial square root holding means. Partial square root calculation adding means, constant subtraction means for subtracting 1 from the least significant bit of the partial square root output by the partial square root holding means, partial square root output by the partial square root holding means and the constant subtraction means Output from the merged square root holding means and a correction multiplexer for selecting and outputting any one of Digit aligning means for performing digit alignment so that the corrected partial square roots output from the correction multiplexer can be merged with respect to the merged square root, and the merged square root output from the merged square root holding means and the output from the digit aligning means. And a square root calculation addition means for adding and to output an updated merged square root. 14. A square root arithmetic unit for obtaining a square root for an input operand normalized to a unit of 2 bits, wherein table information for indexing an approximate reciprocal of a square root with an upper bit of the input operand as an address. A storage means, a surplus holding means for holding a surplus when iteratively obtains a square root by a certain number of bits from the upper order, a surplus output from the surplus holding means, and a surplus output from the table information storage means. Approximate reciprocal of square root is input as a multiplicand and a multiplier, respectively, and a multiplying unit for performing multiplication, and an upper part of a product output from the multiplying unit is input to round one bit less than the least significant bit of the partial square root. Adder means for calculating a partial square root for performing, and a merged square root holding means for holding a merged square root obtained by merging the partial square roots in each iteration. An inversion means for inverting the partial square root output from the partial square root calculation adding means for each bit; and an output of the partial square root calculation adding means by shifting the output of the merged square root holding means by 1 bit to the left. Multiplicand generating means for generating a multiplicand with the partial square root, a remainder (R) output by the remainder holding means, a multiplicand (S) output by the multiplicand generating means, and a multiplier output by the inverting means ( T) and (R + S × T) calculating means for calculating (R + S × T), and (R + S × T) calculating means outputs the adjacent partial square root from the bit length of the partial square root. Shift means for shifting to the left by a number obtained by subtracting the overlapping bit lengths, and selecting one of the input operand and the output of the shift means as an input of the remainder holding means A holding data switching multiplexer, a constant subtracting means for subtracting 1 from the least significant bit of the partial square root output by the partial square root calculating adder, and a partial square root output by the partial square root calculating adder. A correction multiplexer for selecting any one of the outputs of the constant subtraction means and outputting it as a corrected partial square root; and an output of the correction multiplexer for the merged square root output from the merged square root holding means. A digit alignment means for performing digit alignment so that the corrected partial square roots can be merged, and the merged square root output from the merged square root holding means and the output of the digit alignment means are added to output an updated merged square root. And a square root calculation adding unit for calculating the square root. 15. A square root arithmetic unit for obtaining a square root for an input operand normalized to a unit of 2 bits, wherein table information for indexing an approximate reciprocal of a square root by using an upper bit of the input operand as an address. Storing means, remainder holding means for holding the remainder when the square root is iteratively determined by a certain number of bits from the top, partial square root holding means for holding the partial square root at each iteration, and each iteration The merged square root holding means for holding the merged square root obtained by merging the partial square roots at, the inverting means for inverting the partial square root output by the partial square root holding means for each bit, and the output of the merged square root holding means A multiplicand generating means for generating a multiplicand with the partial square root output from the partial square root holding means after shifting by 1 bit to the left; And a remainder multiplexer for selecting one of the remainder output from the remainder holding means, and one of the remainder output from the remainder holding means and the output of the multiplicand generating means. A multiplicand multiplexer for selecting, a multiplier multiplexer for selecting one of the approximate reciprocal of the square root output from the table information storage means and the output of the inverting means, and the output of the remainder multiplexer ( R), the output (S) of the multiplicand multiplexer, and the output (T) of the multiplier multiplexer, respectively, to obtain (R + S × T).
And (R + S × T) operation means for performing the above operation, and the output of the (R + S × T) operation means is shifted to the left by a number obtained by subtracting the bit length overlapping between adjacent partial square roots from the bit length of the partial square root. A shift means for storing the data, a hold data switching multiplexer for selecting one of the input operand and the output of the shift means as an input of the remainder holding means, and the (R + S × T) operation means. The upper part of the product to be output is input, rounding is performed by a bit smaller than the least significant bit of the partial square root, and the rounding result is added to the partial square root holding means. Constant subtraction means for subtracting 1 from the least significant bit of the partial square root output by the holding means; partial square root output by the partial square root holding means and the constant subtraction A correction multiplexer for selecting any one of the outputs of the stages and outputting it as a correction portion square root; and a correction portion output by the correction multiplexer for the merged square root output from the merged square root holding means. A digit aligning unit for performing digit alignment so that the square roots can be merged, and a merged square root output from the merged square root holding unit and an output of the digit aligning unit are added to output an updated merged square root. A square root calculation device comprising: a merged square root calculation addition means.