JPH05313779A - Clock oscillation circuit - Google Patents

Abstract

PURPOSE:To automatically reduce the power consumption without requiring software by providing a detection means detecting the access state of the computer and a clock signal control means making an automatic control of stopping clock signals and reducing the frequency with the input of the signals detected by the detection means on a clock sending circuit. CONSTITUTION:A clock signal control means of a clock sending circuit 4 supplying clock signals to the CPU 1 comprises the power saving circuit to reduce the frequency of the clock signals in the DMA of the computer, and consists of a frequency divider 3, OR gate 6, AND gates 7, 8, and an invertor 9. When an I/O device 5 makes DMA operation, the CPU 1 suspends the processing and outputs acknowledgement signals to DMAC 2. The DMAC 2 occupies the instruction of sending signals to output DACK signals to the I/O device 5. In this case, the frequency of the clock signal is reduced and the frequency-divided clock signals are automatically inputted through the clock sending circuit 4 and through the power saving circuit to the CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock oscillator circuit for supplying a clock signal to a CPU of a computer, and more particularly to a technique for controlling the clock signal.

[0002]

2. Description of the Related Art A computer designed to be compact and lightweight usually has a battery drive function. When used, these types of computers are classified into those using a commercial power source through an adapter and those using a battery-powered function. Here, in the latter case, since the usage time of the computer is limited according to the capacity of the battery itself, the computer is usually provided with a power saving function for reducing the consumption of the battery capacity. For example, in the technique disclosed in Japanese Patent Laid-Open No. 63-292312, is it possible to reduce the frequency of the clock signal and output it to a clock signal generation circuit that supplies the clock signal to the CPU (central processing unit) of the computer? , And a switching circuit for switching whether to output as it is according to the state.

In such a conventional technique, in order to reduce power consumption under computer usage conditions, software is used (software-like interrupt processing from a keyboard or the like).
The frequency of the clock signal is lowered by the switching circuit depending on whether or not there is an interrupt process. That is, the switching circuit lowers and outputs the frequency of the clock signal when there is no software interruption, and outputs the clock signal frequency as it is when there is software interruption.

[0004]

As described above, the conventional clock signal generation circuit switches the frequency of the clock signal by software (operation of a keyboard or the like) when reducing the power consumption under the use condition of the computer. However, there is a disadvantage that the work efficiency is inferior because the manual operation is required. Further, since the processing is performed by software, there is a disadvantage that the computer processing after the operation of the keyboard or the like is required, and the processing capacity by the computer is reduced accordingly.

Therefore, an object of the present invention is to reduce power consumption under computer usage conditions automatically without the intervention of software. Therefore, work efficiency can be improved and computer processing capability can be improved. It is to provide a clock oscillating circuit capable of increasing the power consumption.

[0006]

According to the present invention, there is provided detection means for detecting during DMA (Direct Memory Access) of a computer, other bus operation due to this, or idle time of a CPU of a computer, and the detection means of this detection means. The clock oscillation circuit is provided with clock signal control means for inputting a detection signal and automatically controlling stop of the clock signal supplied to the CPU of the computer or reduction of the frequency of the clock signal.

[0007]

In the clock oscillating circuit of the present invention, the detecting means detects during the DMA of the computer, the other bus operation by the detecting means, or the idle time of the CPU of the computer, and the clock signal control means by the detecting signal of the detecting means, Automatic control of stop of clock signal or decrease of frequency of clock signal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the clock oscillator circuit of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a block diagram for lowering the frequency of a clock signal in a DMA according to an embodiment of the clock oscillator circuit of the present invention, and FIG. 2 is a clock in a DMA according to an embodiment of the clock oscillator circuit of the present invention. It is a block diagram at the time of trying to stop a signal. Further, FIG. 3 is a block diagram for reducing the frequency of a clock signal during another bus operation during DMA according to an embodiment of the clock oscillator circuit of the present invention, and FIG. 4 is an example of the clock oscillator circuit of the present invention. FIG. 11 is a block diagram in the case where the clock signal is stopped during another bus operation during DMA according to the embodiment.

In FIG. 1, a CPU 1 of a computer constitutes a C-MOS integrated circuit, and is a detection means DMAC.
(Direct memory access controller) Transmits signals to and from. DMAC2 is CPU1 and I /
It also transmits signals to and from the O device 5. Also, CPU1
Oscillator circuit 4 for supplying a clock signal to the
Includes clock signal control means. The clock signal control means constitutes a power saving circuit for reducing the frequency of the clock signal during the DMA of the computer, and the power saving circuit includes the frequency divider 3, the OR gate 6, the AND gates 7 and 8, and the inverter 9. Consists of.

The output terminal of the OR gate 6 is connected to the CPU 1, the upper input terminal in the figure is connected to the output terminal of the AND gate 7, and the lower input terminal in the figure is connected to the output terminal of the AND gate 8. .. The upper input terminal of the AND gate 7 in the figure is connected to the frequency divider 3, and the lower input terminal of the figure is the I / O.
It is connected to the input signal line of the device 5. The upper input terminal of the AND gate 8 in the figure is connected to the clock oscillation circuit 4, and the lower input terminal in the figure is connected to the output terminal of the inverter 9. The input terminal of the inverter 9 is connected to the input signal line of the I / O device 5.

On the other hand, the clock signal control means in FIG. 2 constitutes a power saving circuit for stopping the clock signal during DMA, and this power saving circuit comprises an OR gate 6, an AND gate 8 and an inverter 9. The output terminal of the OR gate 6 is connected to the CPU 1, the input terminal on the upper side in the figure is connected to the input signal line of the I / O device 5, and the input terminal on the lower side in the figure is connected to the output terminal of the AND gate 8. is doing. The upper input terminal of the AND gate 8 in the figure is connected to the clock oscillation circuit 4, and the lower input terminal in the figure is connected to the output terminal of the inverter 9. The input terminal of the inverter 9 is connected to the input signal line of the I / O device 5.

The operation of the clock oscillation circuit 4 of the present embodiment having the configuration shown in FIGS. 1 and 2 will be specifically described. In FIG. 1, when the I / O device 5 performs DMA operation, I / O
The device 5 outputs the DREQ signal to the DMAC2. When this DREQ signal is input to the DMAC2, the DMAC
2 is H for monopolizing the command of signal transmission (bus control right)
The OLD signal (request signal) is output to the CPU 1.
When this HOLD signal is input to the CPU1, the CPU1
Temporarily suspends processing (idle state in which CPU 1 does not perform substantial processing), and sends a HOLDACK signal (acknowledgement signal) to D
Output to MAC2. DMA this HOLDACK signal
At the time point (input) detected by C2, the DMAC2 monopolizes the signal transmission command and outputs the DACK signal indicating that the DMA operation is in progress to the I / O device 5.

Then, during the DMA operation by the DACK signal, the CPU 1 is automatically input with the frequency-divided clock signal whose frequency is lowered through the clock oscillation circuit 4 and the power saving circuit. As a result, the CPU 1 constituting the C-MOS integrated circuit can reduce power consumption according to the low frequency of the clock signal due to its structure.

On the other hand, in FIG. 2, when the DMAC 2 monopolizes the signal transmission command and outputs the DACK signal indicating the DMA operation to the I / O device 5, the CPU 1 receives the clock oscillation circuit 4 and the power saving circuit. Then, the clock signal for stopping the clock signal (DC level) is automatically input. As a result, the operable CPU 1 can reduce the power consumption even with the DC level clock signal. Further, in FIGS. 1 and 2, when the DACK signal is not output to the I / O device 5, the clock signal from the clock oscillation circuit 4 is input to the CPU 1 as it is.

As described above, the clock oscillating circuit 4 configured as shown in FIGS. 1 and 2 can automatically save the power consumption under the use condition of the computer in a hardware manner (without software intervention). The efficiency in the aspect can be improved. Moreover, during the DMA operation, the CPU 1 has the bus control right exclusively for the DMAC 2 (an idle state in which the CPU 1 does not perform any substantial processing). Can maintain and enhance ability. In FIG. 3, the CPU 1 of the computer constitutes a C-MOS integrated circuit and transmits signals to and from the bus arbiter 10.
The bus arbiter 10 is a CPU 1 and a bus master 11.
It also transmits signals to and from.

The clock oscillating circuit 4 for supplying a clock signal to the CPU 1 has a clock signal control means. The clock signal control means is the DMA
The power saving circuit for reducing the frequency of the clock signal during the operation of the other bus is constituted by the frequency divider 3, the OR gate 6, the AND gates 7 and 8, and the inverter 9. The bus master 11 functions as a detection means. The output terminal of the OR gate 6 is connected to the CPU 1, the input terminal on the upper side in the drawing is connected to the output terminal of the AND gate 7, and the input terminal on the lower side in the drawing is connected to the output terminal of the AND gate 8. .. The upper input terminal of the AND gate 7 in the figure is connected to the frequency divider 3, and the lower input terminal of the figure is
It is connected to the input signal line of the bus master 11.

The upper input terminal of the AND gate 8 in the figure is
Connected to the clock oscillator circuit 4, the lower input terminal in the figure is
It is connected to the output terminal of the inverter 9. Inverter 9
The input terminal of is connected to the input signal line of the bus master 11. On the other hand, the clock signal control means in FIG.
A power saving circuit for stopping the clock signal during another bus operation by the DMA is configured, and this power saving circuit includes an OR gate 6, an AND gate 8 and an inverter 9. The output terminal of the OR gate 6 is connected to the CPU 1, the input terminal on the upper side in the drawing is connected to the input signal line of the bus master 11, and the input terminal on the lower side in the drawing is connected to the output terminal of the AND gate 8. The upper input terminal of the AND gate 8 in the figure is connected to the clock oscillation circuit 4, and the lower input terminal in the figure is connected to the output terminal of the inverter 9. The input terminal of the inverter 9 is connected to the input signal line of the bus master 11.

The operation of the clock oscillator circuit 4 of the present invention having the configuration shown in FIGS. 3 and 4 will be described in detail. In FIG.
When the bus master 11 based on the DMA operates,
Similar to the above-mentioned DMA, when the HOLDACK signal is input to the bus arbiter 10, the bus master 11 monopolizes the signal transmission command (bus control right), and the MASTERACK indicating that the other bus master 11 is operating by DMA.
Detect (input) a signal. And MASTERACK
During operation of the bus master 11 by a signal, the CPU 1
A clock signal whose frequency has been lowered and whose frequency has been divided is automatically input to the circuit via the clock oscillation circuit 4 and the power saving circuit. As a result, the CPU 1 configuring the C-MOS integrated circuit can reduce power consumption according to the low frequency of the clock signal due to its structure.

On the other hand, in FIG. 4, when the bus master 11 monopolizes the signal transmission command and the MASTERACK signal indicating that the bus master 11 is in operation is input to the bus master 11, the CPU 1 receives the clock oscillation circuit 4 and the power saving circuit. ,
The stop (DC level) clock signal of the clock signal is automatically input. As a result, the operable CPU 1 can reduce power consumption even with a DC level clock signal. 3 and 4, when the MASTERACK signal is not input to the bus master 11, the clock signal from the clock oscillation circuit 4 is input to the CPU 1 as it is.

As described above, the clock oscillation circuit 4 having the configurations shown in FIGS. 3 and 4 can automatically save the power consumption under the use condition of the computer in a hardware manner (without the intervention of software). The efficiency in the aspect can be improved. Moreover, while the other bus master 11 based on the DMA is operating, the CPU 1 has the bus control right exclusively to the bus master 11 (the CPU 1 does not perform any substantial processing). Therefore, the frequency of the clock signal supplied to the CPU 1 is changed. Even if it is lowered, the processing capacity of the computer can be maintained and increased.

Next, another embodiment of the clock oscillation circuit of the present invention will be described in detail with reference to FIGS. Figure 5
Is a block diagram of another embodiment of the clock oscillation circuit of the present invention, FIG. 6 is a time chart showing signal states during device access of another embodiment of the clock oscillation circuit of the present invention, and FIG. 7 is a clock of the present invention. 9 is a time chart showing a signal state during DMA in another example of the oscillator circuit. In FIG. 5, the CPU clock oscillation circuit 15 that supplies a clock signal to the CPU 12 of the computer is
The controller 13 is provided as a clock signal control means. The controller 13 also has an address decoder (not shown) and constitutes a power saving circuit. Then, the controller 13 includes the CPU 12 and the I / O memory 1
4 and the clock oscillation circuit 1
The signal is transmitted to 5.

Further, the controller 13 has a CP and an ADS line to which a signal for starting the CPU 12 cycle is inputted.
RDY line that outputs the end signal of U12 cycle,
HLDA to which the HOLD permission signal of the CPU 12 is input
Line and HO that transmits the HOLD request signal of the CPU 12
It has an LD line. Further, the controller 13 is C
The PU 12 has a detection function as a detection unit that identifies which device the PU 12 accesses, and a function of controlling the CPU 12.

The clock oscillator circuit 15 of the present invention according to FIG.
The operation will be specifically described with reference to FIGS. 6 and 7. In FIG. 6, the CPU 13 cycle starts in the A state where the ADS signal becomes “L”, and this cycle is an access to a low speed device.
It is identified and detected by decoding the address. Next, the controller 13 waits for a prescribed number of clocks in the C state of the CPU 12 clock signal, and then outputs a clock stop (DC level) signal or a clock frequency reduction signal to the CPU clock oscillation circuit 15. The CPU clock oscillating circuit 15 supplies the CPU 12 with the signal for stopping the clock or the signal for lowering the frequency of the clock, so that the CPU 12 enters the wait state during the access to the low speed device. That is, the CPU 12 enters an idle state in which the original processing is not performed. During this state (in the figure), the power consumption can be reduced according to the stop of the clock signal and the low frequency of the clock signal. Then, the controller 13 outputs the RDY signal to the CPU 12 in the D state of the RDY signal, and ends the CPU 12 cycle.

In FIG. 7, in response to the hold request from the peripheral device, the controller 13 outputs the HOLD signal to the CPU 12 while the HOLD signal is A. When this signal is input to the CPU 12, the CPU 12 causes the HLDA
The controller 13 sends a HOLD permission signal in the B state of the signal.
Output to. This hold permission signal is sent to the controller 13
In response to the input, the controller 13 waits for a prescribed number of clocks in the C state of the CPU 12 clock signal, and then outputs a clock stop (DC level) signal or a clock frequency decrease signal to the CPU clock oscillation circuit 15.

The clock stop signal or the clock frequency drop signal is sent to the CPU clock oscillator circuit 15.
However, by supplying to the CPU 12,
When the memory is refreshed, the HLT instruction is executed, etc., the hold state is set. That is, the CPU 12 is in an idle state in which the CPU 12 does not perform its original processing during a signal time required to be stationary. During this state (in the figure,
In between), the power consumption can be reduced according to the stop of the clock signal and the low frequency of the clock signal. Then, when the hold request from the peripheral device is released, the controller 13 holds the HOLD signal in the D state of the HOLD signal.
The LD signal is released and the CPU clock signal is returned to the original state.

As described above, the CPU clock oscillation circuit 15 having the configuration shown in FIG. 5 saves power in the use of the computer in a hardware manner (no intervention of software).
Since the idle state can be detected and automatically performed,
Work efficiency can be improved. Moreover, in the idle state of the CPU 12 (the state in which the CPU 12 does not perform any substantial processing), the CPU 12 has the bus control right exclusively to the controller 13. Therefore, even if the frequency of the clock signal supplied to the CPU 12 is reduced, The processing capacity of can be maintained and increased.

[0027]

According to the invention described in the claims, it is possible to automatically reduce the power consumption under the use condition of the computer without the intervention of software. Therefore, the working efficiency can be improved and the computer can be improved. The processing capacity of can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a clock oscillator circuit according to an embodiment of the present invention.
It is a block diagram in case of intending to reduce the frequency of the clock signal in MA.

FIG. 2 is a circuit diagram of a clock oscillator circuit according to an embodiment of the present invention.
It is a block diagram in case of trying to stop the clock signal in MA.

FIG. 3 is a block diagram of a clock oscillator circuit according to an embodiment of the present invention.
FIG. 9 is a block diagram in a case where the frequency of a clock signal is reduced during another bus operation in MA.

FIG. 4 is a circuit diagram of a clock oscillator circuit according to an embodiment of the present invention.
FIG. 6 is a block diagram for stopping a clock signal during another bus operation in MA.

FIG. 5 is a block diagram of another embodiment of the clock oscillator circuit of the present invention.

FIG. 6 is a time chart showing signal states during device access according to another embodiment of the clock oscillation circuit of the present invention.

FIG. 7 is a time chart showing a signal state at the time of DMA and the like in another embodiment of the clock oscillator circuit of the invention.

[Explanation of symbols]

 1 ... CPU 2 ... DMAC 3 ... Divider 4 ... Clock oscillation circuit 5 ... I / O device 6 ... OR gate 7 ... AND gate 8 ... AND gate 9 ... Inverter 10 ... Bus arbiter 11 ... Bus master 12 ... CPU 13 ... Controller 15 ... CPU clock oscillation circuit

Claims (4)

[Claims] 1. A clock oscillating circuit for supplying a clock signal to a CPU of a computer, a detecting means for detecting an access state of the computer, and a detecting signal of the detecting means are inputted to stop the clock signal or frequency of the clock signal. And a clock signal control means for automatically controlling the drop of the clock signal. 2. The detection means is a computer DMA.
2. The clock oscillator circuit according to claim 1, wherein the clock oscillator circuit detects that the bus is in operation or during the operation of another bus. 3. The detection means is a CPU of a computer
2. The clock oscillator circuit according to claim 1, wherein the idle time is detected. 4. The clock oscillation circuit according to claim 1, wherein the clock signal control means is composed of a power saving circuit.