JPH053017B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a microprogram control unit and a hardware control device that interrupts the microprogram control unit and operates according to instructions from the microprogram control unit. The present invention relates to an information processing device configured to include the following.

[Conventional technology]

In recent years, there has been an increasing trend in the number of information processing devices using microprogram control. There is a device that has a hardware control unit that operates and performs the following operations.

The hardware control unit usually performs processing based on its own judgment, but when the microprogram control unit needs to make a decision or process, it sends information to the microprogram control unit in the form of an interrupt to determine the type of interrupt. The interrupt request is raised along with the interrupt request, and the operation is suspended until an instruction is received from the microprogram control section. On the other hand, the microprogram control section determines what is the cause of the interrupt in the hardware control section, and issues an instruction to the hardware control section according to the interrupt. In the hardware control section,
Processing is restarted in response to an instruction from the microprogram control unit, and continues until judgment and processing by the microprogram control unit are required again.

[Problem that the invention seeks to solve]

In the conventional information processing apparatus described above, even if the hardware control section raises an erroneous interrupt request due to a failure or the like, the microprogram control section gives an operation instruction for the raised interrupt request.

However, if an interrupt request is raised by mistake due to a malfunction or other cause, the interrupt cause will not be reset even if the microprogram control section issues an operation instruction to the hardware control section, and the same interrupt request will be repeated. However, there was a problem in that other processing executed by the microprogram control unit was inhibited.

Further, there is a problem in that the inside of the hardware control section changes depending on the operation instructions from the microprogram control section, which complicates failure analysis of the hardware control section.

[Means for solving problems]

The device of the present invention includes a microprogram control unit, outputs an interrupt request consisting of an interrupt request signal and specific information specifying the interrupt to the microprogram control unit, and responds to an operation instruction corresponding to the interrupt request supplied from the microprogram control unit. An interrupt request that generates the interrupt request signal in response to the occurrence of any one of a plurality of interrupt factors whose occurrence order is known in advance in an information processing device configured with a hardware control unit that operates in response. signal generating means;
Generating a prediction signal corresponding to the next interrupt factor that is provided for each of the interrupt factors and is predicted to occur next based on the operation instruction sent from the microprogram control unit based on the order of occurrence and the interrupt factor that has occurred. prediction signal generation means for generating a predicted coincidence signal when the interrupt factor generated in response to the supply of the corresponding prediction signal, which is provided for each of the interrupt factors, is predicted. , an interrupt factor specifying means for receiving the predicted coincidence signal and sending the specifying information specifying the generated interrupt factor to the microprogram control section.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The information processing device shown in FIG. 1 includes a hardware control section 1 and a microprogram control section 2.
Flip-flop 20 corresponding to each of ~c
~22, AND circuits 30~32, and OR circuit 4
0 and an encoder 50.

An interrupt request signal 60 and interrupt parameters 51 and 52 are sent from the hardware control section 1 to the microprogram control section 2, and an instruction signal 70 and instruction parameters 71 are sent from the microprogram control section 2 to the hardware control section 1. Ru.

Figure 2 shows the interrupt factor a of the hardware control unit 1.
It is a diagram showing the order of occurrence of ~c. In FIG. 2, the interrupt factor a or b occurs after the interrupt factor a, the interrupt factor c occurs after the interrupt factor b, and the interrupt factor a occurs after the interrupt factor c. A combination other than this, for example, an interrupt in which interrupt factor a is followed by interrupt factor c does not occur under normal conditions.

FIG. 3 is a diagram showing the relationship between the input and output of the encoder 50. In Fig. 3, the signal line 33
When is "1", the interrupt parameters 51 and 52, which are the outputs of the encoder 50, become "11", indicating that the interrupt factor a has been turned on. When the signal line 33 is “0” and the signal line 34 is “1”, the encoder 5
The output of 0 becomes "10", indicating that interrupt factor b has been turned on. Furthermore, when the signal lines 33, 34 are both "0" and the signal line 35 is "1", the output of the encoder 50 becomes "0", indicating that the interrupt factor c is turned on, and the signal lines 33, 34, When all 35 are "0", the output becomes "00", indicating that the interrupt is an error interrupt.

Now, if interrupt factor a is turned on in hardware control unit 1 and flip-flop 20 is in the set state at this time, interrupt factor a is turned on by OR circuit 4.
0, the interrupt request signal 60 is sent to the microprogram control unit 2, and at the same time, the interrupt factor a passes through the AND circuit 30 and the encoder 50, and becomes the interrupt parameters 51 and 52 with a value of “11”, and is sent to the microprogram control unit 2. Sent out. The hardware control section 1 then stops operating until an instruction is given from the microprogram control section 2.

When the microprogram control unit 2 receives an interrupt, it learns that the interrupt factor a has occurred because the interrupt parameters 51 and 52 are "11", and issues an instruction for this interrupt through the instruction signal 70 and instruction parameter 71. . At the same time, the flip-flops (here, flip-flops 20 and 21) corresponding to the next predicted interrupt are set, and the others are reset.

When the hardware control unit 1 receives an instruction from the microprogram control unit 2, it resumes the stopped operation,
Start moving again.

After that, the hardware control unit 1 detects the interrupt cause c.
Suppose that the switch is turned on due to a malfunction or other reason. The interrupt factor c is transmitted through the OR circuit 40 to the interrupt request signal 6.
It becomes 0 and is sent to the microprogram control section 2. However, since this interrupt factor c is not a predicted interrupt, flip-flop 22 is not set. Therefore, the signal line 35 becomes "0", and all inputs of the encoder 50 become "0". If all the inputs to the encoder 50 are "0", the output of the encoder 50 will be "00", indicating an error interrupt.

When the microprogram control unit 2 receives an interrupt, it checks the interrupt parameters 51 and 52, and since these are “00”, it knows that the hardware control unit 1 is in a failure state, and the hardware control unit 1
After collecting the data, it is possible to take measures against the failure, such as disconnecting the hardware control unit 1.

As described above, in this embodiment, all interrupt factors other than predicted interrupt causes can be reported to the microprogram control unit 2 as error interrupts, and the microprogram control unit 2 can then perform appropriate processing.

〔Effect of the invention〕

As explained above, the present invention detects failures in the hardware control section early by converting all but predicted interrupt causes into error interrupts and notifying the microprogram control section. This has the effect of facilitating failure analysis and preventing interference with other processes executed by the microprogram control unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a diagram showing the order in which interrupt factors occur in the hardware control section 1, and FIG. 3 is a diagram showing the relationship between input and output of the encoder 50. 1...Hardware control unit, 2...Microprogram control unit, 20, 21, 22...Flip-flop (F/F), 30-32...AND circuit,
33-35... Signal line, 40... OR circuit, 50
... Encoder, 51, 52 ... Interrupt parameter, 60 ... Interrupt request signal, 70 ... Instruction signal, 71 ... Instruction parameter, a, b, c ... Interrupt factor.

Claims (1)

[Scope of Claims] 1. A microprogram control unit, which outputs an interrupt request consisting of an interrupt request signal and specific information specifying the interrupt, and provides an operation instruction corresponding to the interrupt request supplied from the microprogram control unit. In an information processing device configured with a hardware control unit that operates in response to an interrupt, the interrupt request signal is generated in response to the occurrence of any one of a plurality of interrupt factors whose occurrence order is known in advance. a request signal generating means, which is provided for each of the interrupt factors, and generates an interrupt factor that is predicted to occur next based on an operation instruction sent from the microprogram control unit based on the order of occurrence and the interrupt factor that has occurred; a prediction signal generating means for generating a corresponding prediction signal; and a prediction signal generating means provided for each of the interrupt factors, generating a prediction coincidence signal when the interrupt factor generated in response to the supply of the corresponding prediction signal is predicted. An information processing device comprising: predicted coincidence signal generating means; and interrupt factor specifying means for receiving the predicted coincidence signal and sending the specific information specifying the generated interrupt factor to a microprogram control unit.