JPH05300408A - Noise reducing device - Google Patents

Abstract

PURPOSE:To provide the noise reducing device which can effectively reduce noise components contained in input video signals by lessening afterimages. CONSTITUTION:The input video signals are supplied to adding means 1, 2 and 3, the output of the adding means 1 is supplied through a delay means 4 for impressing a delay amount Z<-1> to the adding means 2, the output of this adding means 2 is supplied through a coefficient multiplying means 6 for attenuation coefficient k1 to the adding means 1 and supplied through a coefficient multiplying means 7 for an attenuation coefficient k2 to the adding means 3, and the noise reduction processing is performed by a transmission function H(z) of H(z)={(1-k2)-(k2-k1Z<-1>)}/(1-k1Z<-1>). On the other hand, the rate of changing images is detected by a scene change detecting means 5, and the above-mentioned attenuation coefficients k1 and k2 are controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise reduction device for reducing noise in a video signal, and more particularly to a noise reduction device for performing noise reduction processing by utilizing field correlation or frame correlation of an image.

[0002]

2. Description of the Related Art Generally, in a video signal transmission device or a recording / reproducing device such as a television receiver or a video tape recorder, in order to obtain a high quality video signal, the video field correlation or frame correlation is used A noise reduction device that performs noise reduction processing on a signal is used.

The above noise reducing device is provided with a memory having a storage capacity corresponding to one field period or one frame period, and the difference between the video signal delayed by one field or one frame and the input video signal obtained through this memory. Is detected as noise, and the detected output is multiplied by a noise reduction coefficient and subtracted from the input video signal to obtain a video signal with reduced noise.

[0004]

Conventionally, in this type of noise reduction device, the noise reduction effect stage is forcibly switched from the outside, so that the noise reduction effect is always constant with respect to changes in the image. It was only possible to obtain it, and sometimes it did not adapt to the state of afterimages and images. Further, if the noise reduction effect is increased, an afterimage will remain in a place where the video changes drastically, resulting in an image that is difficult to see. However, if the afterimage is not left, the noise reduction effect cannot be obtained, and it is extremely difficult to set these balances appropriately.

In view of the problems of the conventional noise reducing apparatus as described above, the present invention provides a noise reducing apparatus capable of effectively reducing the afterimage and suppressing the noise component contained in the input video signal. For the purpose of provision. It is another object of the present invention to provide a noise reduction device capable of adaptively controlling the noise reduction effect with respect to changes in video.

[0006]

In order to solve the above-mentioned problems, a noise reduction device according to the present invention includes first to third adding means to which an input video signal is supplied, and the first adding means. giving a delay amount z ^-1 corresponding to one frame period or one field period to the addition output signal by a delay means for supplying the delayed output signal to said second adding means, adds the output by the second adding means A scene change detecting means for detecting the rate of change of the scene of the image represented by the input video signal on the basis of the signal; and the addition output signal from the second adding means multiplied by a _first attenuation coefficient k ₁ 1
The first coefficient multiplying means for supplying to the adding means of
A second coefficient multiplying means for multiplying the addition output signal from the adding means by the second attenuation coefficient k ₂ and supplying the third attenuation means with the second damping coefficient k ₂ , and the first and second coefficient multiplying means. And the second attenuation coefficients k ₁ and k ₂ are controlled according to the rate of change of the scene of the image detected by the scene change detection means, and H (z) = {(1-k ₂ )-(k _1- k ₂ ) z ^-1 } / (1-k ₁ z ^-1 ) The transfer function H (z) of which the input video signal is subjected to noise reduction processing is output from the third adding means. It is characterized by that.

[0007]

In the noise reducing apparatus according to the present invention, the delay means gives the delay output z ^-1 corresponding to one frame period or one field period to the addition output signal from the first addition means to which the input video signal is supplied. , And supplies the delayed output signal to the second adding means. The second adding means supplies the added output signal indicating the difference between the input video signal and the delayed output signal to the scene change detecting means, the first coefficient multiplying means and the second first coefficient multiplying means. The scene change detection means controls the first and second attenuation coefficients k ₁ and k ₂ of the first and second coefficient multiplication means according to the rate of change of the scene of the image. The first coefficient multiplying means includes the second coefficient
The summing output signal from the summing means is multiplied by the first attenuation coefficient k ₁ and supplied to the first summing means. Also, the second
The coefficient multiplying means of (3) multiplies the addition output signal from the second adding means by the second attenuation coefficient k ₂ and supplies the multiplied output signal to the third adding means. Then, the third addition means, by adding combining the output signal and the input video signal by the second coefficient multiplying means, H (z) = {( 1-k 2) - (k 1 -k ₂ ) An output video signal that has been subjected to noise reduction processing by a transfer function H (z) of z ⁻¹ } / (1-k ₁ z ⁻¹ ) is output.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a noise reducing device according to the present invention will be described in detail below with reference to the drawings.

The noise reducing apparatus according to the present invention has first to third adding means 1, 2, 3 to which an input video signal S _IN is supplied, as shown in FIG. A predetermined delay amount z ^{−1 is} added to the addition output signal from the first adding unit 1.
And the delayed output signal S _DL is added to the second adding means 2
And the scene change detection means 5 to which the addition output signal from the second addition means 2 is supplied.
And a first coefficient multiplying means 6 for multiplying the addition output signal from the second adding means 2 by the first attenuation coefficient k ₁ and supplying the multiplied signal to the first adding means 1, and the second adding means 2 And a second coefficient multiplying means 7 which multiplies the addition output signal by the second damping coefficient k ₂ and supplies it to the third adding means 3.

In this noise reduction device, the delay means 4 adds 1 to the addition output signal from the first addition means 1.
A delay amount z ^-1 corresponding to one field or one frame is given. The second adding means 2 detects the difference between the input video signal S _IN and the delayed output signal S _DL supplied from the delay means 4 as a noise component.

Further, the scene change detecting means 5 is
Based on the addition output signal from the second adding means 2,
The rate of change in the scene of the image represented by the input video signal is detected. Then, by controlling the first and second attenuation coefficients k ₁ and k ₂ of the first and second coefficient multiplying means 6 and 7 according to the rate of change of the scene of the image, the first and second attenuation coefficients k ₁ and k ₂ are changed in a scene where the change is drastic. The first and second damping coefficients k ₁ and k ₂ are reduced.

The first coefficient multiplying means 6 multiplies the addition output signal from the second adding means 2, that is, the detected noise component, by the first attenuation coefficient k ₁ , and the first adding means 1 Supply to. Further, the first adding means 1
Is the first damping coefficient k calculated by the first coefficient multiplying means 6.
₁ is hung level control noise component is subtracted from the input video signal S _IN, and supplies the input video signal S _IN having a reduced noise to the delay means 4.

That is, the second adding means 2 detects the noise component by utilizing the field correlation or the frame correlation of the image, and the noise is reduced by the first adding means 1 in the input video signal S. the difference between the delay means 4 by one field or one delayed output signal delay z ^-1 is given which corresponds to a frame S _DL and the input video signal S _iN as a noise component of the input video signal S _iN to the _iN To detect.

The second coefficient multiplying means 7 multiplies the addition output signal from the second adding means 2, that is, the detected noise component, by the second attenuation coefficient k ₂ , and the third adding means 3 Supply to. Then, the third adding means 3
Is the second damping coefficient k obtained by the second coefficient multiplying means 6.
_{By 2} to the multiplied level control noise component is subtracted from the input video signal _{S IN, H (z) =} {(1-k 2) - (k 1 -k 2) z -1} / ( The output image signal S _OUT is obtained by performing noise reduction processing on the input image signal S _IN by the transfer function H (z) of 1-k ₁ z ⁻¹ ).

In the noise reducing apparatus having such a configuration, the noise component detected by the second adding means 2 is included in the input video signal S _IN by varying the _first attenuation coefficient k ₁ by which the noise component is multiplied. The characteristics of the processing system for detecting the noise component generated can be adaptively variably controlled, and the second attenuation coefficient k ₂ for multiplying the noise component detected by the second adding means ₂ can be used. By varying the characteristics, it is possible to adaptively variably control the characteristics of the processing system for reducing the noise component included in the input video signal S _IN . Then, based on the noise component detected by the second adding means 2, the scene change detecting means 5 detects the rate of change in the scene of the image, and the first change is performed.
By controlling the first and second attenuation coefficients k ₁ and k ₂ of the second coefficient multiplying means 6 and 7 to be small, the afterimage is suppressed to a small amount, and the noise component included in the input video signal S _IN is reduced. Can be effectively reduced.

Next, a concrete embodiment of the noise reducing apparatus according to the present invention will be described in detail with reference to FIGS.

The noise reduction device shown in FIG. 2 is composed of a large-scale integrated circuit which is made into one chip, and has a BUF block 1
1, DET block 12, CNT block 13, IIR
Block 14, MEM block 15, GAI block 1
6, TOU block 17, OBF block 18 and SE
The P block 19 is provided so as to function as a signal adaptive noise reduction device or as a delay element for one frame by itself.

The BUF block 11 is a block for performing conversion processing such as data rate conversion on the input video signal S _IN , and corresponds to the delay of the video signal by the decimation filter, and outputs an address control signal, a real-time control signal and the like. Delay. The video signal output from the BUF block 11 is supplied to the DET block 12, IIR block 14 and TOU block 17. The address control signal is the above D
It is supplied to the ET block 12, the MEM block 15, and the OBF block 18. Further, the real-time control signal is supplied to the CNT block 13.

Further, the DET block 12 has the B
Input video signal S _IN supplied through the UF block 11
Is a block that performs various detection processes such as level detection, edge detection, and scene change detection, and includes a level detection circuit 21, an edge detection circuit 22, and a scene change detection circuit 23, and outputs each detection output to the CNT block 13. Supply.

The level detection circuit 21 is composed of a limiter circuit 31, a detection point selector 32 and an absolute value conversion circuit 33 as shown in FIG. 3, for example. In FIG. 3, the limiter circuit 31 applies a limiter according to the level detection point to the input video signal S _IN supplied through the BUF block 11. For example, if the 8-bit input video signal S _IN with the MSB as a sign bit is expressed as I (8: 1), when selecting the level detection point for 4 bits of I (6: 3), I8 (M
If SB), I7, and T6 are the same, the input video signal I (8:
I (6: 3) of 1) is output as it is, and if even one is different, I8 (MSB), that is, according to the code,
I (6: 3) = 0111 or I (6: 3) = 1000 is output. The output of the limiter circuit 31 is supplied to the detection point selector 25. The detection point selector 25 is, for example, I (6: 3) or I (7: 4).
It is composed of respective detection point circuits 32A and 232 in which level detection points are set and a selector 32C for selecting these outputs, and the level detection selected by the selector 32C is supplied to the absolute value conversion circuit 33. The absolute value conversion circuit 33 includes the detection point selector 32.
The level detection by means of the selector 33B is constituted by the selector 33B directly or through the inversion circuit 33A. Then, the selector 33 of the absolute value conversion circuit 33
B performs a selection operation according to the sign bit (MSB) of the input video signal S _IN , and outputs an absolute value level detection signal.

Further, the edge detecting circuit 22 is constructed as shown in FIG. 4, for example, when the edge of the chroma signal is detected. The edge detection circuit 22 uses the input video signal S _IN supplied through the BUF block 11 for 2 clocks (1 clock for detecting a luminance signal) by the input video signal S _IN and the delay circuits 41 and 43. )
Edge detection is performed by adding and mixing the input video signal delayed and inverted by the inversion circuit 42 by the adder 44. Note that overflow may occur, so
In the edge detection circuit 22 shown in FIG. 4, the adder 4
The addition / mixing output, that is, the edge detection output by 4 is passed through the overflow limiter 45 and further through the detection point selector 46 in the same manner as the level detection circuit 21 described above, and then converted into an absolute value by the absolute value conversion circuit 37. And output via the edge width adjusting circuit 48.

The edge width adjusting circuit 48 has, for example, as shown in FIG. 5, an input signal and an input signal and a delay circuit 48A for two clocks (1 when detecting a luminance signal) in order to give the edge a width. (Clock) Delayed signal is compared and the larger one is selected by the selector 38B and output. As shown in FIG. 6, the edge width adjusting circuit 48 has a low-pass filter configuration in which an input signal and a signal obtained by delaying the input signal by two clocks by the delay circuit 48C are added by the adder 48D and output. You can also do it.

The scene change detection circuit 23 is also provided.
Corresponds to the scene change detecting means 5 in the noise reduction device shown in FIG. 1 and is configured as shown in FIG. 7, for example. This scene change detection circuit 23
Includes an absolute value conversion circuit 51 to which difference information indicating the difference between the input video signal and one field or one frame before is supplied from the IIR block 14. The absolute value conversion circuit 51 converts the difference information into absolute value information and supplies it to the level comparator 53 via the limiter circuit 52. The level comparator 53 supplies an output of logic “H” to the counter 55 via the AND circuit 54 when the difference absolute value information supplied via the limiter circuit 52 is larger than a predetermined value. The scene change detection circuit 23 also includes an H, V, CK counter 56 that determines the valid data of the difference information. This H, V, CK
The counter 56 of the AND circuit 54, for example, sets the data of the points at every 16 clocks (CK) for every 16 lines (H) for each field (V) as valid data, as indicated by a circle in FIG. Perform gate control. As a result, the counter 55 counts the number of valid data whose output of the comparator 53 output via the AND circuit 54, that is, the difference absolute value information is larger than a predetermined value. The count value of the counter 55 indicates the rate of change in the scene of the image due to the input video signal S _IN .

Further, the CNT block 13 has the I
A block for controlling the operation of the IR block 14 and the GAI block 16, which comprehensively judges various detection outputs by the DET block 12 and outputs an optimized control signal to the IIR block 14 and the GAI block 16. give. Further, when a real-time control signal from the outside is supplied through the BUF block 11, the control operation according to the real-time control signal is preferentially performed.

Further, the IIR block 14 is connected to the B
Input video signal S _IN supplied through the UF block 11
And a video signal S _DL one frame before read from the MEM block 15, and extracts a noise component. The extracted output, that is, the noise component, is extracted from the DET block 12 and the GAI block 16
Supply to.

The IIR block 14 has a first adder 61 to which the input video signal S _IN from the BUF block 11 and the video signal S _DL from the MEM block 15 are supplied.
And first and second pre-limiters 62 and 63 to which the addition output of the first adder 61 is supplied, and a coefficient ROM to which the output of the first pre-limiter 62 is supplied.
64 and the output of the coefficient ROM 64 are the attenuator 65
And a second adder 66 to which the input video signal from the BUF block 11 is supplied.

The first adder 61 is the second adding means 2 in the principle configuration of the noise reducing apparatus shown in FIG.
Corresponding to the input video signal _IN supplied through the BUF block 11 and the video signal S _DL one frame before read from the MEM block 15 and an addition output indicating a difference is output from the DET block 12. The scene change detection circuit 23 is supplied with the first and second
To the pre-limiters 62 and 63.

The first pre-limiter 62 detects the added output of the first adder 61, which is based on the motion of a predetermined limiter level L ₁ or higher, and is shown by a solid line in FIG. As described above, the limiter level L ₁ or lower is extracted as a noise component, and the coefficient ROM
Supply to 63. Also, the second pre-limiter 63
The noise for the added output by the first adder 61, a predetermined limiter level L ₂ above performs motion detection attributed to the motion, as indicated by a broken line in FIG. 9, the limiter level L ₂ or less It is supplied to the GAI block 16 as a component. Here, the limiter levels L ₁ and L of the first and second pre-limiters 62 and 63, respectively.
₂ is set to L ₁ <L ₂ .

The coefficient ROM 64 is for converting the noise level according to a predetermined conversion characteristic, and indicates the noise component supplied from the first adder 61 via the first pre-limiter 62. Level data obtained by multiplying the noise level by a coefficient is read using the data as a read address. This coefficient ROM6
The noise level data read from No. 4 is supplied to the second adder 66 via the attenuator 65.
Further, the attenuator 65 is provided with the coefficient ROM 64.
A predetermined amount of attenuation is given to the noise level data read out from by the bit shift. The coefficient ROM6
4 and the attenuator 65 are the first coefficient multiplication means 6 in the principle configuration of the noise reduction device shown in FIG.
Equivalent to. The second adder 66 corresponds to the first adding means 1 in the principle configuration of the noise reduction device shown in FIG. 1, and is supplied from the coefficient ROM 64 via the attenuator 65. A noise level reduced video signal is supplied to the MEM block 15 as an addition output signal obtained by subtracting the noise level data from the input video signal supplied via the BUF block 11.

Here, in this embodiment, the coefficient ROM is used.
Level data of three types of conversion characteristics are written in advance in 64, and the conversion characteristics of the coefficient ROM 64 and the attenuation amount of the attenuator 65 are controlled by the IIR control signal from the CNT block 13. As a result, the characteristics of the IIR block 14 are finely adjusted in 0.25 steps, and the lower bits are used effectively.

Further, the MEM block 15 corresponds to the delay means 4 in the principle configuration of the noise reduction device shown in FIG. 1 described above, and is composed of a frame memory having a storage capacity of one frame, and the IIR block. The video signal supplied from the second adder 66 of 14 is stored,
The video signal of one frame before is supplied to the first adder 61 of the IIR block 14 and the TOU block 17.

The GAI block 16 corresponds to the second coefficient multiplying means 7 in the principle configuration of the noise reduction device shown in FIG. 1 described above, and the gain of the noise component extracted by the IIR block 14 is obtained. Is supplied to the TOU block 17 by changing the
It comprises a coefficient ROM 71 similar to the IR block 14, an attenuator 72 by bit shift, etc., and a gain control signal from the CNT block 13 variably controls the attenuation amount of the attenuator 72 in 1/8 steps.

Further, the TOU block 17 includes the B
It performs a process of reducing noise of an input video signal supplied via the UF block 11, and includes an adder 81 and a changeover switch 82.

In the TOU block 17, the adder 81 corresponds to the second adding means 3 in the principle configuration of the noise reduction device shown in FIG. 1 and is supplied via the BUF block 11. A noise-reduced video signal is generated by subtracting and combining the noise component whose gain is adjusted by the GAI block 16 with respect to the input video signal. Then, in the noise reduction operation mode, the noise-reduced video signal obtained by the adder 81 is output via the changeover switch 82. In the delay operation mode, the video signal of one frame before read from the MEM block 15 is output via the changeover switch 82.

The OBF block 18 has the T
A block that performs conversion processing such as data rate conversion on the video signal supplied from the OU block 17, and delays the address control signal and the real-time control signal in response to the delay of the video signal by the interpolation filter. Output.

The SEP block 19 converts serial data from a microcomputer (not shown) into parallel data to control the operation of each block.

In the noise reduction device having such a configuration, the CNT block 13 is the DET block 1
The IIR block 1 according to various detection outputs by 2
4 and GAI block 16 are controlled as follows.

That is, when the edge level indicated by the edge detection output from the edge detection circuit 22 is low, the CNT block 13 determines that portion is a large screen portion and deeply applies noise reduction processing. like,
The coefficient k ₁ of the IIR block 14 and the coefficient k ₂ of the GAI block 16 are increased. In this way, by reflecting the edge detection output in the noise reduction processing, it is possible to apply the noise reduction processing deeper in a large area where noise is conspicuous on the screen so that the noise is less noticeable. Further, since the moving portion in the still image can be detected by the edge detection, by making the noise reduction processing of the moving portion shallow, the afterimage can be reduced and the overall noise reducing effect can be maintained.

In the CNT block 13, the smaller the rate of change of the video scene of the video scene indicated by the detection output by the scene change detection circuit 23, the more the I
The coefficient k ₁ of the IR block 14 and the GAI block 1
The coefficient k ₂ of 6 is controlled to be large. In this way, by changing the noise reduction effect according to the rate of change of the video scene, it is possible to obtain a high noise reduction effect with less afterimage. Also, when the scene is completely changed, the loop coefficient k ₁ of the IIR block 14 is minimized. As a result, afterimages can be reduced.

Further, the CNT block 13 receives the coefficient k _{1 of the} IIR block 14 according to the signal level indicated by the level detection output from the level detection circuit 21.
And control the coefficient k ₂ of the GAI block 16. When the level is low in the luminance signal, noise is conspicuous. Therefore, when the level is low, the coefficient k ₁ of the IIR block 14 and the coefficient k ₂ of the GAI block 16 can be increased to make the noise inconspicuous. it can. Further, since noise is conspicuous when the level is high in the chroma signal, noise is made inconspicuous by increasing the coefficient k ₁ of the IIR block 14 and the coefficient k ₂ of the GAI block 16 when the level is high. be able to. ..

[0041]

As is evident from the foregoing description, in the noise reducing device according to the present invention, H (z) = {( 1-k 2) - (k 1 -k 2) z -1} / (1-k 1 z ^-1 ) Since the output video signal is obtained by subjecting the input video signal to the noise reduction processing by the transfer function H (z), the first attenuation by which the noise component detected by the second adding means is multiplied. By varying the coefficient k ₁ , it is possible to adaptively variably control the characteristics of the processing system for detecting the noise component included in the input video signal, and the above second
By varying the _second attenuation coefficient k ₂ that multiplies the noise component detected by the adding means, the characteristics of the processing system for reducing the noise component included in the input video signal are adaptively variably controlled. be able to. Then, based on the noise component detected by the second adding means,
The scene change detection means 5 detects the rate of change in the scene of the image, and controls so as to reduce the first and second attenuation coefficients k ₁ and k ₂ of the first and second coefficient multiplication means. By doing so, it is possible to suppress the afterimage to be small and effectively reduce the noise component included in the input video signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a noise reduction device according to the present invention.

FIG. 2 is a block diagram showing a specific configuration of a noise reduction device according to the present invention.

FIG. 3 is a block diagram showing a configuration of a level detection circuit that constitutes a detection block in the noise reduction device shown in FIG.

FIG. 4 is a block diagram showing a configuration of an edge detection circuit which constitutes a detection block in the noise reduction device shown in FIG.

5 is a block diagram showing a configuration of an edge width adjustment circuit that constitutes the edge detection circuit shown in FIG.

6 is a block diagram showing another configuration of an edge width adjustment circuit that constitutes the edge detection circuit shown in FIG.

7 is a block diagram showing a configuration of a scene change detection circuit that constitutes a detection block in the noise reduction device shown in FIG.

8 is a diagram of a screen used for explaining the operation of the scene change detection circuit shown in FIG.

9 is a characteristic diagram showing the operation of each limiter circuit that constitutes the IIR block in the noise reduction device shown in FIG.

[Explanation of symbols]

1, 66 ... First adding means (adder) 2, 61 ... Second adding means (adder) 3, 81 ... Third adding means (adder) 4, 15 ... Delay means (MEM block) 5,23 ... Scene change detection means (scene change detection circuit) 6, 14 ... First coefficient multiplication means (IIR block) 7, 16 ... Second coefficient multiplication Means (GAI block)

Claims (1)

[Claims] 1. A first to a third to which an input video signal is supplied
And a delay amount z ⁻¹ corresponding to one frame period or one field period is given to the addition output signal from the first addition unit.
A delay unit that supplies the delayed output signal to the second adding unit, and a scene change that detects the rate of change in the scene of the image represented by the input video signal based on the added output signal from the second adding unit. Detection means, first coefficient multiplication means for multiplying the addition output signal from the second addition means by the first attenuation coefficient k ₁ and supplying the first addition coefficient to the first addition means, and addition by the second addition means A second coefficient multiplying means for multiplying the output signal by a second damping coefficient k ₂ and supplying the multiplied signal to the third adding means, wherein the first and second damping means of the first and second coefficient multiplying means are provided. The coefficients k ₁ and k ₂ are controlled according to the rate of change of the scene of the image detected by the scene change detection means, and H (z) = {(1-k ₂ ) − (k ₁ −k ₂ ). z ^-1} / in _(1-k 1 z ^-1) transfer functions H (z) Noise reducing apparatus characterized by an output video signal subjected to the noise reduction processing to the input video signal outputted from said third addition means I.