JPH05299575A - Semiconductor device with built-in memory - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor device including a large-capacity memory. [Configuration] RAM and ROM chips 12 and 13 having a memory circuit formed therein and an MPU 11 having an arithmetic circuit formed therein are sealed in the same package 14. Further, the MPU 11, the RAM chip 12, the ROM chip 13, and the external leads 17 are electrically connected to each other in the package 14 as needed. [Effect] By independently providing memory chips (RAM chips and ROM chips) having memory circuits,
It is possible to increase the memory capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a built-in memory, particularly RAM (= Random Access Memory) and R.
A memory chip such as OM (= Read Only Memory) and M
The present invention relates to a semiconductor device with a built-in memory in which an arithmetic chip having a PU (= Micro Processing Unit) formed therein is sealed in the same package.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing a conventional example of a semiconductor device having a built-in memory. Here, in order to help understanding of the internal structure of the package, the state in which the upper part of the package is cut away is shown.

In this semiconductor device with a built-in memory, as shown in the figure, a package 1 is sealed with an MPU 4 containing a RAM circuit 2 and a ROM circuit 3. In addition, MPU
Reference numeral 4 has an arithmetic circuit (not shown), and is electrically connected to the RAM circuit 2 and the ROM circuit 3 by wiring not shown.

Bonding pads 5 are provided on the outer periphery of the MPU 4, and the bonding pads 5 are electrically connected to external leads 7 extending from the package 1 to the outside by wires 6, respectively.
Therefore, this semiconductor device has the external lead 7 and the wire 6
It is electrically connected to external peripheral circuits via
Send and receive electrical signals.

Next, the operation of the semiconductor device with a built-in memory configured as described above will be described. When the semiconductor device is externally powered on or a reset signal is applied, the MPU 4 outputs a predetermined address. This address is usually the address of the ROM circuit 3 incorporated in the MPU 4, and the ROM circuit 3 is output by this address output.
The program recorded in is started to execute. Also,
The RAM circuit 2 built in the MPU 4 stores the result processed according to the program as data.

[0006]

In the conventional semiconductor device with a built-in memory, the MPU 4 has the RAM circuit 2 and the RO circuit as described above.
The M circuit 3 is built in, that is, the RAM circuit 2, the ROM circuit 3 and the arithmetic circuit are formed on the same chip. Therefore, the area where the RAM circuit 2 and the ROM circuit 3 are formed cannot be increased in design, and as a result, the memory capacity of the RAM circuit 2 and the ROM circuit 3 becomes relatively small. In particular, when the memory capacity required for operating the MPU 4 is larger than the capacity of the built-in memory (RAM circuit 2 and / or ROM circuit 3), a large capacity RAM and / or ROM is externally added to make up the shortage. To supplement the memory capacity of. In this case, the mounting area is increased by the amount of externally attached memory elements (ROM, RAM, etc.).

The present invention has been made to solve the above problems, and a first object of the present invention is to provide a semiconductor device having a large capacity memory built therein.

In addition to the first object, it is a second object of the present invention to downsize the built-in memory semiconductor device.

[0009]

In order to achieve the above object, the invention of claim 1 is a memory chip in which a memory circuit is formed, an arithmetic chip in which an arithmetic circuit is formed, and the memory chip and an external device. And / or a plurality of external leads for exchanging electrical signals between the arithmetic chip and the outside, the memory chip and the arithmetic chip are sealed in the same package, and the memory chip and the arithmetic The chip and the external leads are electrically connected in the package as needed.

According to a second aspect of the present invention, in order to achieve the second object, a plurality of the memory chips are provided, and the memory chips are laminated with each other and the plurality of the memory chips are laminated in the laminated state. The memory chips are electrically connected to each other.

According to a third aspect of the invention, in order to achieve the second object, the memory chip is stacked on the arithmetic chip, and the memory chip and the arithmetic chip are electrically connected in the laminated state. Connected to.

[0012]

According to the present invention, the memory circuit and the arithmetic circuit are formed on different semiconductor chips, that is, the memory chip and the arithmetic chip, respectively. Then, the memory chip and the arithmetic chip are sealed in the same package and appropriately electrically connected. By independently providing the memory chip having the memory circuit in this manner, the memory capacity can be increased. Moreover, since the memory chip and the arithmetic chip are housed in the same package, an external memory element is not required, and as a result, the area for mounting is reduced.

According to the invention of claim 2, since a plurality of memory chips are stacked on each other and are electrically connected to each other in the stacked state, the semiconductor device is different from the semiconductor device according to the invention of claim 1 above. The planar size of the device is smaller.

According to the third aspect of the present invention, since a plurality of memory chips are stacked on each other and electrically connected to each other in the stacked state, the memory capacity is increased while keeping the planar size of the semiconductor device small. can do.

[0015]

1 is a perspective view showing a first embodiment of a semiconductor device with a built-in memory according to the present invention. Similar to FIG. 8, this figure also shows a state in which the upper part of the package is cut off to facilitate understanding of the configuration of the semiconductor device.

In this semiconductor device, as shown in FIG.
An MPU 11 in which an arithmetic circuit is formed and a memory chip (hereinafter referred to as a “RAM chip”) in which a RAM circuit is formed 1
2 and a memory chip formed with a ROM circuit (hereinafter referred to as “R
An “OM chip” 13 is encapsulated in the same package 14. These MPU11, RAM chip 1
2. The ROM chip 13 is provided with the bonding pad 15 respectively, and the MPU is provided by the wire 16.
11 is properly connected to the RAM chip 12 and the ROM chip 13. Furthermore, MPU11, RAM chip 1
2. The ROM chip 13 is also electrically connected to the external lead 17 extending from the package 14 to the outside via the bonding pad 15 and the wire 16.

The operation of the semiconductor device configured as described above is the same as that of the conventional example, and therefore its description is omitted here.

As described above, in the semiconductor device according to the present invention, the RAM circuit and the RO functioning as the memory circuit.
The M circuit is separated from the MPU 11 and is independent of each RA.
It is formed on the M and ROM chips 12, 13. Therefore, the sizes of the RAM and ROM chips 12, 13 are simply increased, and the RAM and ROM chips 12, 13 are increased.
If a large-capacity RAM circuit and ROM circuit are formed in 13, the memory capacity of the semiconductor device can be greatly increased. Moreover, these RAM and ROM chips 1
Since 2 and 13 are sealed in the same package 14 as the MPU 11, it is not necessary to attach a memory element to the semiconductor device in order to increase the memory capacity, and as a result, the mounting area can be reduced. it can.

In the first embodiment, the MPU 11,
Although the case where the RAM chip 12 and the ROM chip 13 are electrically connected by wire bonding has been described, the connecting method is not limited to that, and may be performed as in an embodiment described later. Has the same effect. However, the semiconductor device described later has the same basic configuration and operation as those of the first embodiment except the connection method, and therefore the description thereof will be omitted.

FIG. 2 is a plan view showing a second embodiment of the semiconductor device with a built-in memory according to the present invention. In this semiconductor device, the MPU 11, the RAM chip 12, and the ROM chip 13 are electrically connected by TAB (= Tape Automated Bonding). That is, the above connection is performed as follows. First, the wiring 19 is formed in advance on the film 18, and bumps (not shown) are formed on the electrodes of the MPU 11, the RAM chip 12 and the ROM chip 13.
Is formed. Then, the film 18 and each chip (M
After aligning the PU 11, the RAM chip 12, and the ROM chip 13), the bump is connected to the wiring 19.

FIG. 3 is a perspective view showing a third embodiment of the memory-embedded semiconductor device according to the present invention. In this semiconductor device, the bumps 20 are formed on the MPU 11, and the RAM chip 12 and the ROM are formed on the bumps 20.
The electrodes of the chip 13 are connected to each other. Therefore, as shown in FIG.
And MPU with the ROM chips 13 stacked
11 and the RAM and ROM chips 12 and 13 are electrically connected. Therefore, compared to the first embodiment, the package 1
The size of 4 can be reduced, and the mounting area can be further reduced.

Further, instead of the connection by the bump 20,
As shown in FIG. 4, a through hole 21 may be used. That is, the RAM chip 12 and the ROM chip 13
The RAM and ROM chips 12 and 13 are arranged so that the electrodes 15 of each of them are located on the electrodes 15 of the MPU 11, respectively, and a metal such as aluminum (Al) is provided in the through hole 21 formed through each of the chips 12 and 13. Is electrically connected to the electrode 15 of the MPU 11.

Further, instead of the through hole 21, FIG.
It is also possible to utilize the diffusion layer 22 as shown in FIG. In this case, in the RAM chip 12, an electrode 23 is formed on the back surface side corresponding to the electrode 15 formed on the front surface, and appropriate impurities are diffused in the region sandwiched between these electrodes 15 and 23 to make the RAM chip 12 A diffusion layer 22 having a conductivity type opposite to that of the substrate is formed. The ROM chip 13 also has the same electrode 1 as the RAM chip 12.
A diffusion layer 22 of the opposite conductivity type is formed in a region sandwiched by 5, 23. On the other hand, in the MPU 11, the bump 24 is provided on the electrode 15. Then, by connecting the electrodes 23 to the bumps 24, the MPU 11 and the RAM and ROM chips 12 and 13 are electrically connected while the RAM chip 12 and the ROM chip 13 are stacked on the MPU 11. ..

In the above embodiment, the RAM chips 12 and R
The case where the OM chips 13 are stacked on the MPU 11 has been described, but the ROM chip 13 is stacked on the RAM chip 12 to form a stacked memory chip 30 (FIG. 6), and the memory chip 30 and the MPU 11 are 1
Similar to the embodiment, they may be sealed in the same package 14. That is, as shown in FIG. 6, the bumps 25 are formed on the electrodes 15 of the RAM chip 12, and the electrodes 15 of the ROM chip 13 are connected to the bumps 25 to form the memory chip 30. The MPU 11, the memory chip 30, and the external leads 17
Are electrically connected to each other by wires 16 as shown in FIG. In this way, the RAM chip 12 and the R
By stacking with the OM chip 13, the plane size of the memory chip (RAM, ROM chip) becomes smaller than that of the first embodiment.

In the above embodiment, the RAM chip 12
Although the semiconductor device with a built-in memory including the ROM chip 13 has been described, the present invention can be applied to general semiconductor devices including at least one or more memory chips.

[0026]

As described above, according to the invention of claim 1, the memory circuit and the arithmetic circuit are formed in the memory chip and the arithmetic chip, respectively, and the memory chip and the arithmetic chip are sealed in the same package, Further, since the electric connection is made appropriately, the memory capacity can be increased.

According to the invention of claim 2, since a plurality of memory chips are stacked on each other and are electrically connected to each other in the stacked state, the semiconductor device according to the invention of claim 1 above. The semiconductor device can be downsized, and the semiconductor device can be miniaturized.

Further, according to the third aspect of the present invention, since the plurality of memory chips are stacked on each other and are electrically connected to each other in the stacked state, the memory can be formed without increasing the size of the semiconductor device. The capacity can be increased.

[Brief description of drawings]

FIG. 1 is a first semiconductor device with a built-in memory according to the present invention.
It is a perspective view showing an example.

FIG. 2 shows a second semiconductor device with a built-in memory according to the present invention.
It is a top view showing an example.

FIG. 3 is a third semiconductor device with a built-in memory according to the present invention.
It is a perspective view showing an example.

FIG. 4 is a fourth semiconductor device with a built-in memory according to the present invention.
It is sectional drawing which shows an Example.

FIG. 5 is a fifth semiconductor device with a built-in memory according to the present invention.
It is sectional drawing which shows an Example.

FIG. 6 is a sixth semiconductor memory device according to the present invention.
It is a fragmentary sectional view showing an example.

FIG. 7 is a sixth semiconductor device with a built-in memory according to the present invention.
It is a perspective view showing an example.

FIG. 8 is a perspective view showing a conventional semiconductor device with a built-in memory.

[Explanation of symbols]

 11 MPU 12 RAM chip 13 ROM chip 14 Package 17 External lead

Claims (3)

[Claims] 1. A memory chip in which a memory circuit is formed, an arithmetic chip in which an arithmetic circuit is formed, and an electric signal is exchanged between the memory chip and the outside and / or between the arithmetic chip and the outside. A plurality of external leads for encapsulating the memory chip and the arithmetic chip in the same package, and electrically between the memory chip, the arithmetic chip, and the external leads in the package as needed. A semiconductor device with a built-in memory characterized by being connected. 2. A plurality of the memory chips are provided,
2. The memory-embedded semiconductor device according to claim 1, wherein the memory chips are stacked on each other, and the plurality of memory chips are electrically connected to each other in the stacked state. 3. The semiconductor device with a built-in memory according to claim 1, wherein the memory chip is laminated on the arithmetic chip, and the memory chip and the arithmetic chip are electrically connected in the laminated state.