JPH05299497A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which controls a leak current at an edge portion of trench and also can reduce a contact resistance by forming an edge on a semiconductor substrate surface of a trench isolating portion and the part to become an active layer of the semiconductor substrate surface as the portions having a radius of curvature. CONSTITUTION:A MOS transistor consisting of a gate polysilicon 8 provided on a semiconductor substrate 1 through a gate insulating film 6 and source/drain portion 5 and a trench isolating structure for isolating adjacent MOS transistors are comprised. In such semiconductor device, an edge portion on the surface of semiconductor substrate 1 of the trench isolating portion 4 and the part to become an active layer at the surface of the semiconductor substrate 1 are formed as the portion having a radius of curvature. For instance, a structure like a mountain having a radius of curvature may be formed by forming a groove 2 at the trench isolating portion 4, then forming a silicon nitride film at a gate electrode forming portion on the semiconductor substrate 1 and thereafter executing field oxidation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of a MOS transistor and an isolation region between adjacent transistors and a manufacturing method of the structure.

[0002]

2. Description of the Related Art The miniaturization of LSI is 10 ⁸
Progress has been made until 10 ⁹ elements are formed, and M
The gate length of the OS transistor is scaled to 0.6 to 0.3 μm. Accordingly, the bird's beak cannot be suppressed by the isolation using LOCOS as the isolation method between the adjacent transistors, so that the isolation width cannot be reduced. In order to shorten the isolation width, the substrate is directly etched and the adjacent A trench isolation method is used to isolate the transistors to be used.

FIG. 7 shows a conventional MOS using trench isolation.
FIG. 8 is a view of the transistor seen obliquely from above, and FIG. 8 is a view (a cross-sectional view taken along the line bb ′ of FIG. 7) taken across a contact hole portion in the gate width direction of the transistor,
9 is a diagram (cross-sectional view taken along the line cc 'of FIG. 7) when the gate portion is crossed in the gate width direction of the transistor, and FIG. 10 is a gate portion and a contact in the gate length direction of the transistor. Figure when crossing the hole (d in Figure 7)
It is a cross-sectional view taken along the −d ′ plane.

In these figures, 1 is a semiconductor substrate made of a P-type single crystal (hereinafter referred to as substrate), 2 is a trench portion for separating an element formation region formed on the substrate 1, and 3 is on the substrate 1. The P-type island formed in 4 is an insulating film embedded in the trench 2, 5 is a source / drain of this transistor, 6 is a gate oxide film, 7 is a sidewall, and 8 is a gate polysilicon. Yes, 9 is an interlayer film (not shown in FIG. 7), 10 is a contact hole, 1
1 is Al for wiring (omitted in FIGS. 7 and 9).

Next, a conventional manufacturing method will be described with reference to FIG. First, As ⁺ , B on the P-type semiconductor substrate 1
^After ion implantation of ⁺ , P ^+, etc. is performed to form the island layer 3, photolithography and patterning of the trench are performed, and the substrate 1 is directly etched to form the trench isolation portion 2 (FIG. 11 (a )).

After that, the trench portion 2 is filled with SiO 2 and Si.
3 Fill with insulating film 4 such as N4, form gate insulating film 6, cover with gate polysilicon, photoengraving of gate,
After patterning and etching to form the gate electrode 8, ion implantation is performed to form the source / drain portions 5. After that, an insulating film is provided on the entire surface, and sidewalls 7 are formed on both side walls of the gate electrode 8 by etching back (FIG. 11B).

After that, the interlayer insulating film 9 is covered on the entire surface, contact photolithography, patterning, and etching are performed to form a contact hole 10, and a metal such as Al or W is formed on the entire surface so as to fill the inside of the contact hole 10. The wiring 11 is provided by performing photoengraving, patterning, and etching of the wiring (FIG. 11C).

[0008]

As described above, in the conventional manufacturing method, since the edge portion of the trench is rectangular,
There is a problem that there is a large amount of leakage current due to the edge portion of the trench.

Further, with the miniaturization of the MOS transistor, there has been a problem that the contact hole area on the source / drain portion of the MOS transistor is reduced and the contact contact resistance is increased, which causes a circuit delay.

The present invention has been made to solve the above problems, and provides a semiconductor device capable of suppressing the leak current at the edge portion of the trench and reducing the contact resistance, and a manufacturing method thereof. The purpose is to

[0011]

The semiconductor device according to the present invention has a smooth structure in which the edges of the trench portion and the source / drain portions have a curvature.

Further, in the method of manufacturing a semiconductor device according to the present invention, a mountain-shaped structure is formed by providing a curvature at an edge on the surface of the semiconductor substrate in the trench portion and at a position to be an active layer on the surface of the semiconductor substrate. It was done.

Also, the method of manufacturing a semiconductor device according to the present invention includes a step of forming a groove in a trench isolation portion of a semiconductor substrate, a step of forming a silicon nitride film in a gate electrode formation portion on the semiconductor substrate, and a field oxidation. And forming a field oxide film having a curvature at the edge of the groove on the surface of the semiconductor substrate and at the place to be the active layer on the surface of the semiconductor substrate, and after removing the silicon nitride film, the gate insulating film and the gate electrode. , A step of forming a source / drain portion by performing ion implantation using the gate electrode as a mask, a step of forming an interlayer film, photolithography for contact holes, etching, a source having a curvature,
And a step of forming a contact portion on the drain portion with a wiring metal.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a silicon nitride film on a gate electrode forming portion on a semiconductor substrate and a step of performing field oxidation to form an active layer on the surface of the semiconductor substrate are performed. A step of forming a field oxide film having a curvature, a step of removing the silicon nitride film and the field oxide film, a step of forming a groove in a trench isolation part of a semiconductor substrate by etching, and a step of insulating the groove for trench isolation insulation. Photographs for contact holes, a step of embedding a film, a step of forming a gate insulating film and a gate electrode, a step of implanting ions using the gate electrode as a mask to form source and drain parts, and an interlayer film. The process of plate making and etching, and forming contact parts with metal for wiring on the source and drain parts with curvature Those were example.

[0015]

According to the present invention, since the edge portion of the trench isolation has a smooth structure having a curvature, the leak current on the substrate surface of the trench can be reduced. Further, since the source and drain portions also have a structure having a curvature, the contact contact area of the substrate surface of the contact can be made larger than the contact hole area, and the contact resistance can be reduced. In addition to this, the sub-threshold swing (S.FACTOR) also becomes smaller.

Further, according to the present invention, as described above, a mountain-shaped structure is formed by providing a curvature at the edge of the trench portion on the surface of the semiconductor substrate and at a place to be an active layer on the surface of the semiconductor substrate. Therefore, it is possible to obtain an element capable of reducing the leak current at the edge portion of the trench and the contact resistance.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a view of a structure of a semiconductor device according to an embodiment of the present invention, that is, a structure of a MOS transistor and an element isolation part viewed obliquely from above, and FIG. 2 is a view when a contact hole part is crossed in a gate width direction. FIG. 3 is a view (a cross-sectional view taken along the bb ′ plane of FIG. 1), and FIG. 3 is a view when a gate portion is crossed in the gate width direction (a cross-sectional view taken along the cc ′ plane of FIG. 1), FIG. 3 is a diagram (a cross-sectional view taken along the line dd ′ in FIG. 1) when the gate portion and the contact hole portion are crossed in the gate length direction.

In these figures, 1 is a semiconductor substrate made of P-type single crystal, 2 is a trench portion for separating an element formation region formed on the substrate 1, and 3 is P formed on the substrate 1.
Type island, 4 is an insulating film buried in the trench portion, 5 is a source / drain portion of this transistor, 6 is a gate oxide film, 7 is a sidewall, 8 is a gate polysilicon, and 9 is an interlayer. A film (not shown in FIG. 1), 10 is a contact hole, 11 is an Al for wiring
(Omitted in FIGS. 1 and 3).

The MOS transistor of this embodiment is characterized in that the edge of the trench 2 of the element isolation portion on the semiconductor surface has a curvature, and the source / drain portion 5 also has a curvature in the gate width direction. is there.

A curvature is provided at the edge of the above trench,
An example of a method of manufacturing a transistor and an element isolation part in which a source / drain part also has a curvature will be described with reference to FIG.
In FIG. 5, the same reference numerals as those in FIGS. 1 to 4 indicate the same or corresponding portions, 12 is a silicon nitride film, and 13 is a field oxide film.

First, As ⁺ , P ⁺ , B ⁺ on the Si substrate 1.
Ion implantation is performed to form the island portion 3.
After that, photolithography and patterning are performed on the portions that will become the separation portions, and the Si substrate is etched to form rectangular grooves.
After that, a silicon nitride film is provided on the entire surface, and the silicon nitride film 12 is left only in the region to be the gate portion by photolithography and patterning (FIG. 5 (a)).

Then, field oxidation is performed to form a field oxide film 13 around the trench 2 and in the active layer to be the source and drain with a curvature, and then the silicon nitride film 12 is removed (FIG. 5 (b)). ..

Then, after removing the field oxide film by etching, the trench isolation portion 2 is formed, for example, with SiO2.
, Si3 N4, BPSG, etc. are buried in the insulating film for trench isolation (FIG. 5 (c)). If the field oxide film is used as an insulating film for trench isolation, this step is not necessary.

After that, a gate insulating film 6 is formed, covered with gate polysilicon, photoengraving, patterning of the gate and etching are performed to form a gate 8 (FIG. 5 (d)).
).

After that, As ⁺ , P ⁺ , B ^{+ and the} like are ion-implanted to form the N ⁻ source / drain portion 5, a sidewall is formed on the gate 8 and the N ⁺ source is again ion-implanted. After forming the drain portion, the interlayer insulating film 9 is covered, the contact hole 10 is opened, and Al,
A contact is made with W or the like and wiring 11 is performed. As a result, the element shown in FIG. 1 is obtained.

FIG. 6 shows another example of a method of manufacturing a transistor and an element isolation part in which a curvature is provided at an edge part of a trench and a source / drain part is also provided with a curvature.
In the figure, the same reference numerals as those in FIGS. 1 to 4 and 5 indicate the same or corresponding portions.

The manufacturing method will be described below. First,
After ion-implanting As ⁺ , P ⁺ , B ^+, etc. on the Si substrate 1 to form the island portion 3, a silicon nitride film is provided on the entire surface, and the silicon nitride film is formed only on a region to be a gate by photolithography and etching. 12 is patterned (FIG. 6 (a)).

Next, field oxidation is performed to form a field oxide film 13 with a curvature on the active layer which will be the source and drain portions (FIG. 6 (b)).

After that, the silicon nitride film 12 and the field oxide film 13 are removed by etching, after that, photoengraving and patterning for forming the trench isolation portion are performed, and the Si substrate is directly etched to dig a rectangular groove to form the trench isolation. Form part 2. After that, the trench isolation part 2
Is filled with an insulating film for trench isolation such as SiO2, Si3 N4, BPSG (FIG. 6 (c)).

After that, a gate insulating film 6 is formed, a gate polysilicon is covered, photolithography, gate patterning and etching are performed to form a gate 8 (FIG. 6 (d)).
).

After that, As ⁺ , P ⁺ , B ^{+ and the} like are ion-implanted to form the N ⁻ source and drain portions 5, a sidewall is formed on the gate 8, and the N ⁺ source is again ion-implanted. After forming the drain portion, the interlayer insulating film 9 is covered, the contact hole 10 is opened, and Al,
A contact is made with W or the like and wiring 11 is performed. As a result, the device having the structure shown in FIG. 1 is completed.

According to the present embodiment as described above, since the edge on the surface of the semiconductor substrate of the trench isolation portion has a curvature, it is possible to reduce the leak current at the edge portion of the trench.

Further, since the source and drain portions are also formed to have a curvature, the contact portion on the source and drain portions can have a contact area larger than the contact hole sectional area, thereby reducing the contact resistance. It is possible to obtain an element which can sufficiently cope with miniaturization of transistors. In addition, since the source and drain parts have a curvature, the subthreshold swing (S.FACTOR)
Can be made smaller, and the performance of the device can be improved.

[0034]

As described above, according to the present invention, the edge portion of the semiconductor substrate surface of the trench isolation portion and the source / source.
Since the drain portion has a mountain-shaped structure with a curvature, the leak current at the edge of the trench can be reduced, the contact area taken on the source and drain portions can be increased, and the contact resistance can be reduced. You can
Furthermore, since the source / drain portions have a mountain-shaped structure, the subthreshold swing (S.FACTOR) can be reduced, and a high-performance MOS transistor and an element having isolation can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram of a structure of a semiconductor device according to an embodiment of the present invention viewed obliquely from above.

FIG. 2 is a cross-sectional view taken along the line bb ′ of the semiconductor device of FIG.

FIG. 3 is a cross-sectional view taken along the line cc ′ of the semiconductor device of FIG.

FIG. 4 is a cross-sectional view taken along the line dd ′ of the semiconductor device of FIG.

FIG. 5 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a diagram showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 7 is a view of a structure of a conventional semiconductor device viewed obliquely from above.

8 is a cross-sectional view taken along the line bb 'of the semiconductor device of FIG.

9 is a cross-sectional view taken along the line cc 'of the semiconductor device of FIG.

10 is a cross-sectional view taken along the line dd 'of the semiconductor device of FIG.

FIG. 11 is a diagram showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Element Isolation Trench 3 Island 4 Trench Filling Insulation Film 5 Source / Drain Part 6 Gate Insulation Film 7 Sidewall 8 Gate Polysilicon 9 Interlayer Insulation Film 10 Contact Hole 11 Al Wiring 12 Silicon Nitride Film 13 Field Oxide Film

Claims (4)

[Claims] 1. A semiconductor device having a MOS transistor composed of a gate polysilicon and a source / drain portion provided on a semiconductor substrate via a gate insulating film, and a trench isolation structure for isolating adjacent MOS transistors. 2. The semiconductor device according to, wherein the edge of the trench isolation portion on the surface of the semiconductor substrate and the portion to be the active layer on the surface of the semiconductor substrate have a smooth shape with a curvature. 2. A semiconductor device having a MOS transistor composed of a gate polysilicon and a source / drain portion provided on a semiconductor substrate via a gate insulating film, and a trench isolation structure for isolating adjacent MOS transistors. The method of manufacturing a semiconductor device according to claim 1, which comprises the step of forming a mountain-shaped structure by providing a curvature at an edge on the surface of the semiconductor substrate in the trench portion and at a position to become an active layer on the surface of the semiconductor substrate. Production method. 3. A semiconductor device having a MOS transistor including a gate polysilicon provided on a semiconductor substrate via a gate insulating film and a source / drain portion, and a trench isolation structure for isolating adjacent MOS transistors. In the manufacturing method of, the step of forming a groove in the trench isolation portion of the semiconductor substrate by etching, the step of forming a silicon nitride film in the gate electrode formation portion on the semiconductor substrate, and the step of performing field oxidation on the semiconductor substrate surface of the groove A step of forming a field oxide film having a curvature at the edge of the semiconductor substrate and an active layer on the surface of the semiconductor substrate, a step of forming a gate insulating film and a gate electrode after removing the silicon nitride film, Ion implantation is performed using the electrode as a mask to form the source and drain parts, and the interlayer film is formed. Photolithography for making and contact holes,
A method of manufacturing a semiconductor device, comprising: a step of performing etching to form a contact portion on a source and drain portion having a curvature with a wiring metal. 4. A semiconductor device having a MOS transistor composed of a gate polysilicon and a source / drain portion provided on a semiconductor substrate via a gate insulating film, and a trench isolation structure for isolating adjacent MOS transistors. In the manufacturing method of 1., a step of forming a silicon nitride film on the gate electrode formation portion on the semiconductor substrate, and a step of performing field oxidation to form a field oxide film having a curvature at a place to be an active layer on the surface of the semiconductor substrate. A step of removing the silicon nitride film and the field oxide film, a step of forming a groove in a trench isolation portion of a semiconductor substrate by etching, a step of filling the groove with a trench isolation insulating film, a gate insulating film and a gate The step of forming an electrode, and ion implantation using the gate electrode as a mask to form a source And forming a drain portion, an interlayer film, photolithography for the contact hole,
A method of manufacturing a semiconductor device, comprising: a step of performing etching to form a contact portion with a metal for wiring in a source and drain portion having a curvature.