JPH05299450A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05299450A JPH05299450A JP4104905A JP10490592A JPH05299450A JP H05299450 A JPH05299450 A JP H05299450A JP 4104905 A JP4104905 A JP 4104905A JP 10490592 A JP10490592 A JP 10490592A JP H05299450 A JPH05299450 A JP H05299450A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- substrate
- chip component
- bump electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、より
詳細には基板に、高速で動作する半導体集積回路が実装
された半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor integrated circuit operating at high speed is mounted on a substrate.
【０００２】[0002]
【従来の技術及び発明が解決しようとする課題】近年、
ＳｉやＧａＡｓを材料に用いた半導体集積回路（以下
「ＩＣ」と記す）の高速度化が著しい。これに伴い、こ
れらＩＣを使用するコンピュータや通信機器高光速度化
されつつある。しかし、これらＩＣの高速化に比例し
て、システムが高速化されているわけではない。その理
由の一つは、ＩＣ単体では高速化されても、それを実装
するＩＣパッケージでの遅延や波形歪みがシステム全体
のスピードを遅らせるからである。2. Description of the Related Art In recent years,
The speed of semiconductor integrated circuits (hereinafter referred to as "IC") using Si or GaAs as a material is remarkably increased. Along with this, the optical speed of computers and communication devices using these ICs is increasing. However, the system is not speeded up in proportion to the speedup of these ICs. One of the reasons for this is that even if the speed of the IC alone is increased, the delay and waveform distortion in the IC package that mounts it slows down the speed of the entire system.
【０００３】そこで最近では、ワイヤーボンド法やフリ
ップチップ法等の、ＩＣをパッケージに実装せずに直接
基板に実装する方法が多く採用されている。ワイヤーボ
ンド法は、図３及び図４に示したように、信号伝送線路
１３を有する誘電体基板１２上に、接続用の電極パッド
１１が形成されたＩＣ１４がアルミニウムや金等の細線
ワイヤ１６を用いて接続されている。従って、パッケー
ジでの信号の遅延や歪みは生じることがない。しかし、
ワイヤ１６を用いているために信号が高速になればなる
ほど、ワイヤ１６のインダクタンスが無視できなくな
り、インピーダンス不整合が生じ、ＩＣ１４と周辺回路
での信号伝送が困難になるという課題があった。Therefore, recently, many methods such as a wire bonding method and a flip chip method for directly mounting an IC on a substrate without mounting the IC on a package have been adopted. In the wire bond method, as shown in FIGS. 3 and 4, the IC 14 having the connection electrode pad 11 formed on the dielectric substrate 12 having the signal transmission line 13 has the thin wire 16 made of aluminum or gold. Are connected using. Therefore, no signal delay or distortion occurs in the package. But,
Since the signal becomes faster due to the use of the wire 16, there is a problem that the inductance of the wire 16 cannot be ignored, impedance mismatch occurs, and signal transmission between the IC 14 and peripheral circuits becomes difficult.
【０００４】フリップチップ法は、図５及び図６に示し
たように、信号伝送線路１３を有する誘電体基板１２上
に、半田や金等のバンプ電極２１を用いてＩＣ１４を接
続し、バンプ電極２１を補強するために基板１２下方か
らバンプ電極２１を被覆するように、あるいは基板１２
及びバンプ電極２１全体を被覆するように樹脂２５が配
設されている。従って、ワイヤのインダクタンスを無視
することができ、ＩＣ１４と周辺回路での信号伝送は良
好となる。しかし、この樹脂２５は誘電率が４〜６と比
較的大きいため、ＩＣ１４内に高速信号が伝送された場
合、ＩＣ１４内の分布定数路線の電磁界に影響を与え、
信号伝送線路のロスを増大させてＩＣ１４の特性を劣化
させるという問題があった。また、能動素子の電極間に
樹脂２５が入り込んだ場合には、電極間の容量が増加す
るため、ＩＣ１４内の能動素子の高周波特性を悪化させ
るという問題があり、これは、樹脂２５の誘電率が小さ
くなれば、容量の増加も小さくなり、能動素子の特性劣
化は小さく抑えられるが、樹脂２５はバンプ電極２１の
補強のために挿入されているため、その物理定数のう
ち、誘電率のみを小さくすることは困難であるためであ
る。In the flip chip method, as shown in FIGS. 5 and 6, the IC 14 is connected to the dielectric substrate 12 having the signal transmission line 13 by using the bump electrode 21 such as solder or gold, and the bump electrode is formed. 21 so as to cover the bump electrodes 21 from below the substrate 12 to reinforce the substrate 21 or the substrate 12
A resin 25 is provided so as to cover the bump electrodes 21 as a whole. Therefore, the inductance of the wire can be ignored, and the signal transmission between the IC 14 and the peripheral circuit becomes good. However, since the resin 25 has a relatively large dielectric constant of 4 to 6, when a high-speed signal is transmitted in the IC 14, it affects the electromagnetic field of the distributed constant line in the IC 14,
There is a problem that the characteristics of the IC 14 are deteriorated by increasing the loss of the signal transmission line. Further, when the resin 25 enters between the electrodes of the active element, the capacitance between the electrodes increases, which causes a problem of deteriorating the high frequency characteristics of the active element in the IC 14, which is due to the dielectric constant of the resin 25. The smaller the value, the smaller the increase in capacitance and the smaller the characteristic deterioration of the active element. However, since the resin 25 is inserted to reinforce the bump electrode 21, only the dielectric constant of its physical constants is used. This is because it is difficult to reduce the size.
【０００５】また、特公平３−６７３３７には、図７に
示したように、基板１２とＩＣチップ１４との間の空間
に窒素ガス２６を封入する方法が開示されている。本発
明は上記記載の課題に鑑みなされたものであり、ＩＣを
基板上に実装しても高速動作が可能で、ＩＣの特性劣化
を防止することができる半導体装置を提供するものであ
る。Further, Japanese Patent Publication No. 3-67337 discloses a method of filling the nitrogen gas 26 in the space between the substrate 12 and the IC chip 14 as shown in FIG. The present invention has been made in view of the problems described above, and provides a semiconductor device capable of operating at high speed even when the IC is mounted on a substrate and preventing deterioration of the characteristics of the IC.
【０００６】[0006]
【課題を解決するための手段】上記記載の課題を解決す
るために本発明によれば、チップ部品下面の周辺部にバ
ンプ電極を複数個配置し、該バンプ電極により前記チッ
プ部品と基板とを接続させた半導体装置であって、前記
バンプ電極形成部を含むチップ部品の下面周辺部に第１
の樹脂が配設され、前記チップ部品の下面であって、該
第１の樹脂の内側に前記第１の樹脂よりも誘電率の小さ
い第２の樹脂が配設されている半導体装置が提供され
る。In order to solve the above-mentioned problems, according to the present invention, a plurality of bump electrodes are arranged in the peripheral portion of the lower surface of the chip component, and the chip electrode and the substrate are connected by the bump electrodes. A semiconductor device connected to the first part on the lower surface peripheral part of the chip component including the bump electrode forming part.
And a second resin having a dielectric constant smaller than that of the first resin is provided inside the first resin on the lower surface of the chip component. It
【０００７】本発明におけるチップ部品は、例えば、Ｇ
ａＡｓ、シリコン基板等によって形成された半導体集積
回路を示すが、半導体集積回路のみに限定されるもので
はなく、コンデンサチップ、フィルタ等の部品にも適用
することができる。また、基板としてはシリコン、アル
ミナセラミクス等の誘電体基板等を用いることができ、
特に限定されるものではない。The chip component in the present invention is, for example, G
Although a semiconductor integrated circuit formed of aAs, a silicon substrate, or the like is shown, the present invention is not limited to the semiconductor integrated circuit and can be applied to parts such as a capacitor chip and a filter. As the substrate, a dielectric substrate such as silicon or alumina ceramics can be used,
It is not particularly limited.
【０００８】本発明において、チップ部品はバンプ電極
によって基板に接続されており、バンプ電極としては、
通常、電気的な接続を得るために用いられる材料、例え
ば、金、ハンダ、銅等を用いることができる。さらに、
チップ部品の下面周辺部に配設される第１の樹脂として
は、例えば、エポキシ樹脂等を用いることができ、エポ
キシ樹脂等を用いた場合に、第１の樹脂の内側に配設さ
れる第２の樹脂として、これら樹脂よりも誘電率の小さ
い樹脂、例えば、フッ素系樹脂等が用いられる。なお、
第２の樹脂の誘電率が第１の樹脂の誘電率よりも小さけ
れば、その材料、組み合わせ等は限定されるものではな
い。In the present invention, the chip component is connected to the substrate by bump electrodes, and the bump electrodes are:
Materials typically used to obtain electrical connections, such as gold, solder, copper, etc. can be used. further,
As the first resin provided on the peripheral portion of the lower surface of the chip component, for example, an epoxy resin or the like can be used. When the epoxy resin or the like is used, the first resin provided inside the first resin can be used. As the second resin, a resin having a smaller dielectric constant than these resins, for example, a fluorine resin is used. In addition,
If the dielectric constant of the second resin is smaller than the dielectric constant of the first resin, the material, combination, etc. are not limited.
【０００９】[0009]
【作用】本発明においては、バンプ電極を補強し、信頼
性を確保する樹脂は第１の樹脂としてチップ部品の下面
周辺部のみに存在し、チップ部品の中央部には存在せ
ず、チップ部品の下面中央部に存在する第２の樹脂は誘
電率が第１の樹脂よりも小さいので、第２の樹脂がチッ
プ部品の動作に与える影響は少なく、演算回路や信号伝
送線路の特性劣化が小さくなる。In the present invention, the resin that reinforces the bump electrode and secures the reliability exists as the first resin only in the peripheral portion of the lower surface of the chip component and not in the central portion of the chip component. Since the second resin present in the central portion of the lower surface of the is smaller in dielectric constant than the first resin, the second resin has less influence on the operation of the chip component, and the characteristic deterioration of the arithmetic circuit and the signal transmission line is small. Become.
【００１０】[0010]
【実施例】本発明に係る半導体装置を図面に基づいて説
明する。図１及び図２に示したように、例えば、アルミ
ニウムによって形成された信号伝送線路３を有する誘電
体基板であるアルミナセラミクス基板２上と接続用の電
極パッド（図示せず）が形成されたＩＣ４とが、ＩＣ４
下面周辺部にバンプ電極１を用いて接続されている。ま
た、バンプ電極１を含むＩＣ４下面の周辺部には第１の
樹脂であるエポキシ樹脂５が配設されている。また、エ
ポキシ樹脂５の内側であって、ＩＣ４が載置される部分
のほぼ中央にＩＣ４よりも小さい孔が形成されており、
エポキシ樹脂５の内側であって、この孔を埋設するよう
に、エポキシ樹脂５よりも誘電率の低い第２の樹脂であ
るフッ素系樹脂６が配設されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described with reference to the drawings. As shown in FIGS. 1 and 2, for example, an IC 4 having an alumina ceramic substrate 2 which is a dielectric substrate having a signal transmission line 3 made of aluminum and an electrode pad (not shown) for connection formed thereon. And IC4
Bump electrodes 1 are used to connect to the peripheral portion of the lower surface. Further, an epoxy resin 5, which is a first resin, is provided on the peripheral portion of the lower surface of the IC 4 including the bump electrodes 1. Further, inside the epoxy resin 5, a hole smaller than the IC4 is formed in substantially the center of the portion on which the IC4 is mounted.
Inside the epoxy resin 5, a fluorine-based resin 6 that is a second resin having a lower dielectric constant than the epoxy resin 5 is provided so as to fill the hole.
【００１１】以下にその製造方法を説明する。まず、ア
ルミナセラミクス基板２上に形成された信号伝送線路３
とＩＣ４の電極パッドとを、ハンダを用いたバンプ電極
１により接続する。そして、軟化している第１の樹脂で
あるエポキシ樹脂５をＩＣ４とアルミナセラミクス基板
２との間に挿入する。この時、エポキシ樹脂５は毛管現
象により、アルミナセラミクス基板２上のＩＣ４が載置
される部分に形成された孔には入り込まず、ＩＣ４の周
辺部のみに配置されることとなる。The manufacturing method will be described below. First, the signal transmission line 3 formed on the alumina ceramic substrate 2
And the electrode pad of the IC 4 are connected by the bump electrode 1 using solder. Then, the softened epoxy resin 5, which is the first resin, is inserted between the IC 4 and the alumina ceramic substrate 2. At this time, due to the capillary phenomenon, the epoxy resin 5 does not enter into the hole formed in the portion on the alumina ceramic substrate 2 where the IC 4 is mounted, and is placed only in the peripheral portion of the IC 4.
【００１２】エポキシ樹脂５が硬化した後、アルミナセ
ラミクス基板２裏面より、アルミナセラミクス基板２に
形成された孔に第２の樹脂であるフッ素系樹脂６を埋設
し、硬化する。このような半導体装置は、ＩＣ４とアル
ミナセラミクス基板２上の信号伝送線路３とがバンプ電
極１で接続されているために、その接続インピーダンス
は非常に小さい。このため、外部からＩＣ４に入力する
信号が高速になっても、バンプ電極１の影響でＩＣ４と
外部信号伝送線路間にインピーダンスの不整合がほとん
ど生じない。さらに、バンプ電極１を補強し、信頼性を
確保するエポキシ樹脂５はＩＣ４の下面周辺部のみに存
在し、ＩＣ４の下面中央部には存在しない。そして、Ｉ
Ｃ４の下面中央部に存在するフッ素系樹脂６は誘電率が
エポキシ樹脂５よりも小さいので、フッ素系樹脂６がＩ
Ｃの動作に与える影響は小さく、演算回路や信号伝送線
路の特性劣化が小さくなる。After the epoxy resin 5 is hardened, a fluorine-based resin 6 as a second resin is buried in the holes formed in the alumina ceramics substrate 2 from the back surface of the alumina ceramics substrate 2 and hardened. In such a semiconductor device, since the IC 4 and the signal transmission line 3 on the alumina ceramic substrate 2 are connected by the bump electrode 1, the connection impedance thereof is very small. Therefore, even if the signal input to the IC 4 from the outside becomes high speed, the impedance mismatch between the IC 4 and the external signal transmission line hardly occurs due to the influence of the bump electrode 1. Furthermore, the epoxy resin 5 that reinforces the bump electrode 1 and secures the reliability exists only in the peripheral portion of the lower surface of the IC 4, and not in the central portion of the lower surface of the IC 4. And I
Since the fluorine-based resin 6 existing in the central portion of the lower surface of C4 has a smaller dielectric constant than the epoxy resin 5, the fluorine-based resin 6 is I
The influence on the operation of C is small, and the characteristic deterioration of the arithmetic circuit and the signal transmission line is small.
【００１３】従って、エポキシ樹脂５がＩＣの下面周辺
部でバンプ電極の信頼性を確保し、ＩＣ内のフッ素系樹
脂６がＩＣの伝送線路や演算回路等の高速回路の特性劣
化を抑制し、耐湿性等の信頼性を確保することができ
る。Therefore, the epoxy resin 5 ensures the reliability of the bump electrode in the peripheral portion of the lower surface of the IC, and the fluorine resin 6 in the IC suppresses the characteristic deterioration of the high speed circuit such as the transmission line of the IC and the arithmetic circuit, It is possible to secure reliability such as moisture resistance.
【００１４】[0014]
【発明の効果】本発明に係る半導体装置によれば、バン
プ電極を補強し、その信頼性を確保する樹脂は第１の樹
脂としてチップ部品の下面周辺部のみに存在し、チップ
部品の下面中央部には存在せず、チップ部品の下面中央
部に存在する第２の樹脂は誘電率が第１の樹脂よりも小
さいので、第２の樹脂がチップ部品の動作に与える影響
は小さく、演算回路や信号伝送線路の特性劣化を小さく
することができる。According to the semiconductor device of the present invention, the resin for reinforcing the bump electrode and ensuring its reliability exists as the first resin only in the peripheral portion of the lower surface of the chip component, and the center of the lower surface of the chip component is provided. The second resin, which does not exist in the central part and exists in the central portion of the lower surface of the chip component, has a smaller dielectric constant than the first resin, so that the second resin has a small influence on the operation of the chip component and the arithmetic circuit It is possible to reduce the characteristic deterioration of the signal transmission line.
【００１５】従って、第１の樹脂がチップ部品の下面周
辺部でバンプ電極の信頼性を確保し、チップ部品内の第
２の樹脂がチップ部品の伝送線路や演算回路等の高速回
路の特性劣化を抑制し、耐湿性等の信頼性を確保するこ
とができる。Therefore, the first resin ensures the reliability of the bump electrode in the peripheral portion of the lower surface of the chip component, and the second resin in the chip component deteriorates the characteristics of the high-speed circuit such as the transmission line of the chip component and the arithmetic circuit. Can be suppressed and reliability such as moisture resistance can be secured.
【図１】本発明に係わる半導体装置の要部を示す概略平
面透視図である。FIG. 1 is a schematic plan perspective view showing a main part of a semiconductor device according to the present invention.
【図２】図１におけるＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along line AA in FIG.
【図３】基板とチップ部品とをワイヤを用いて接続した
従来の半導体装置の一実施例の要部を示す概略平面透視
図である。FIG. 3 is a schematic plan perspective view showing a main part of an embodiment of a conventional semiconductor device in which a substrate and a chip component are connected by wires.
【図４】図３におけるＢ−Ｂ線断面図である。FIG. 4 is a sectional view taken along line BB in FIG.
【図５】基板とチップ部品とをバンプ電極を用いて接続
した従来の半導体装置の一実施例の要部を示す概略断面
図である。FIG. 5 is a schematic cross-sectional view showing a main part of an embodiment of a conventional semiconductor device in which a substrate and a chip component are connected by using bump electrodes.
【図６】従来の半導体装置の別の実施例の要部を示す概
略断面図である。FIG. 6 is a schematic cross-sectional view showing a main part of another embodiment of a conventional semiconductor device.
【図７】従来の半導体装置のさらに別の実施例の要部を
示す概略断面図である。FIG. 7 is a schematic cross-sectional view showing the main parts of yet another embodiment of a conventional semiconductor device.
１ バンプ電極 ２ アルミナセラミクス基板（基板） ４ ＩＣ（チップ部品） ５ エポキシ樹脂（第１の樹脂） ６ フッ素系樹脂（第２の樹脂） 1 Bump Electrode 2 Alumina Ceramics Substrate (Substrate) 4 IC (Chip Component) 5 Epoxy Resin (First Resin) 6 Fluorine Resin (Second Resin)
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/15 23/28 Ｅ 8617−4Ｍ 23/29 23/31 9355−4Ｍ Ｈ０１Ｌ 23/14 Ｃ 8617−4Ｍ 23/30 Ｂ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical display location H01L 23/15 23/28 E 8617-4M 23/29 23/31 9355-4M H01L 23/14 C 8617-4M 23/30 B
Claims (1)
複数個配置し、該バンプ電極により前記チップ部品と基
板とを接続させた半導体装置であって、前記バンプ電極
形成部を含むチップ部品の下面周辺部に第１の樹脂が配
設され、前記チップ部品の下面であって、該第１の樹脂
の内側に前記第１の樹脂よりも誘電率の小さい第２の樹
脂が配設されていることを特徴とする半導体装置。1. A semiconductor device in which a plurality of bump electrodes are arranged in the peripheral portion of the lower surface of a chip component and the chip component and the substrate are connected by the bump electrodes, the chip component including the bump electrode forming portion. A first resin is disposed on the peripheral portion of the lower surface, and a second resin having a dielectric constant smaller than that of the first resin is disposed on the lower surface of the chip component and inside the first resin. A semiconductor device characterized by being present.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4104905A JPH05299450A (en) | 1992-04-23 | 1992-04-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4104905A JPH05299450A (en) | 1992-04-23 | 1992-04-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05299450A true JPH05299450A (en) | 1993-11-12 |
Family
ID=14393145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4104905A Pending JPH05299450A (en) | 1992-04-23 | 1992-04-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05299450A (en) |
-
1992
- 1992-04-23 JP JP4104905A patent/JPH05299450A/en active Pending
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