JPH0529888A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To surely prevent omission of data in a minimum delay time by allowing a flip-flop circuit to output a clock signal in phase to a clock signal inputted in almost a same timing as a clock signal at a slowest timing among clock signals generated in the inside based on an input clock signal. CONSTITUTION:An input terminal of an inverter 27 connects between two inverters 22, 23 in a clock processing circuit in a flip-flop circuit and a clock signal CKout in phase with an inputted clock signal CKin is extracted to the outside of the flip-flop circuit from an output terminal of the inverter 27. In this case, the clock signal CKout is generated in a timing almost coincident with a clock signal phi having a latest timing to switch each gate in the inside of the flip-flop circuit. Thus, the delay time is minimized in which no data omission is caused, and a sequential logic circuit with small circuit scale operated at a high speed is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a gate array, a standard cell and the like, which is provided with a flip-flop circuit which is most suitable for forming a sequential logic circuit in an IC customized by an automatic placement and routing function. The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, it has been widely practiced to construct a semiconductor integrated circuit including a sequential logic circuit in which a large number of flip-flop circuits are combined by using a gate array technique. FIG. 5 is a diagram showing a configuration example of a conventional D-type flip-flop circuit. As shown in FIG. 5A, the D input terminal 11 is connected to the input terminal of the clocked inverter 12, and the output terminal of the clocked inverter 12 is connected to the input terminal of the inverter 13 and one end of the transfer gate 14. There is. The other end of the transfer gate 14 is connected to the output terminal of the inverter 15. The output terminal of the inverter 13 is connected to the input terminal of the inverter 15 and one end of the transfer gate 16. The other end of the transfer gate 16 is the inverter 1
7 is connected to one end of the transfer gate 18, and the other end of the transfer gate 18 is connected to the output terminal of the inverter 19 and the input terminal of the inverter 20. The output terminal of the inverter 17 is connected to the input terminal of the inverter 19 and the input terminal of the inverter 21.

In the circuit configured as described above, clock signals φ and ψ whose phases are opposite to each other are required.
As shown in the clock processing circuit of FIG. 5B, the clock signal CKin input from the clock input terminal is inverted via the inverter 22 to generate the clock signal ψ, and further passes through the inverter 23. As a result, the clock signal φ having the same phase as the input clock signal CKin is generated, and the two generated clock signals φ and ψ whose phases are opposite to each other are supplied to the circuit shown in FIG.

When the clock φ rises while the L level signal is input to the D input terminal 11 of the D type flip-flop circuit configured as described above, the H level signal has been output until then. Of the clocked inverter 12 shifts to the OFF state in which the output side is held at high impedance, and at the same time, the transfer gate 14 which has been in the OFF state until then shifts to the ON state and is composed of the inverters 13, 15 and the transfer gate 14. The H level signal is latched in the loop, the transfer gate 16 is also turned on together with this, and the H level signal is output to the outside of the flip-flop circuit via the inverters 17 and 21. An L level signal is output via 19 and 20. In this state, it is assumed that the signal at the D input terminal shifts to the H level, and when the clock φ falls in that state, the transfer gate 18 shifts to the ON state and is composed of the inverters 17, 19 and the transfer gate 18 until then. The H-level signal transmitted to the entrance of the loop of the second stage is latched in the loop of the second stage, and at the same time, the transfer gates 14 and 16 are in the off state.
The clocked inverter 12 is turned on, and an H level signal input from the D input terminal 11 is inverted by the clocked inverter 12 to become an L level signal. The inverters 13 and 15 and the transfer gate 14 are provided.
It is transmitted to the entrance of the loop of the stage.

By repeating the above operation in synchronization with the clock signal CKin, the H-level or L-level signal input from the D input terminal 11 is changed to the clock signal CKi.
It is output at each rising timing of n. 6 is shown in FIG.
FIG. 10 is a diagram showing an example of a conventional shift register configured by connecting a large number of flip-flop circuits shown in FIG.

Q output terminals 101a of the left-side flip-flop circuits 101, 102, 103, ... Adjacent to each other,
102a, 103a, ... Are buffers 251 and 2 for delaying.
, 52, 253, ... D input terminals 102b, 1 of the right flip-flop circuits 102, 103, 104 ,.
03b and 104b are connected. Further, the D input terminal 10 of the first-stage flip-flop circuit 101 on the leftmost side of the figure
Serial data is input from 1b. In addition, each flip-flop circuit 101, 102, 103, 104,
... clock input terminals 101c, 102c, 103c,
Clock signals in phase with each other are input to 104c ,. In the shift register configured as described above, a serial signal is input to the D input terminal 101b of the first-stage flip-flop circuit 101, and each flip-flop circuit 101, 102, 103, 104,
When a clock signal is input to ..., D input terminal 101b
The serial signals input from the above are sequentially moved one by one to the right flip-flop circuit at the rising timing of each clock pulse.

Here, the delay buffers 251, 25
The necessity of 2, 253, ... Will be described. 7 is a timing chart showing the operation of the first-stage flip-flop circuit 101 and the second-stage flip-flop circuit 102 for explaining the necessity of the delay buffers 251, 252, 253, ....

The clock signal input to the clock input terminal 101c of the first-stage flip-flop circuit 101 is shown in FIG.
It is assumed that it has risen like CK1 shown in. At this time,
The first-stage flip-flop circuit 1 is delayed by a predetermined time t1 for the operation of the flip-flop circuit shown in FIG.
The signal of Q1 shown in FIG. 7 is output to the Q output terminal of 01.

Further, because of the wiring capacitance 24 of the clock line 26 (see FIG. 6) for transmitting the clock signal, the clock input terminal 1 of the flip-flop circuit 102 at the next stage is
The clock signal input to 02c is delayed by time t2 compared to CK1 as shown by CK21 in FIG.
Here, each flip-flop circuit 101, 102, 10
In order to surely latch the data into the flip-flop circuits 101, 102, 103, 104 before the setup time t3 before the rising time of the clock pulse, the flip-flop circuits 101, 102, 103, 104, ... , D input terminals 101b, 102b, 103b, 104b,
Data must be set in the flip-flop circuits 101 and 102 for a predetermined hold time t4 from the time when the clock pulse rises.
D input terminals 101b and 102 of 103, 104, ...
It is necessary to keep data held in b, 103b, 104b, ..., During these setup time t3 and hold time t4, D input terminals 101b, 102b ,.
If the data input to 103b, 104b, ... Changes, the data may not be correctly latched in the flip-flop circuit. However, if buffer 251
If the output signal of Q1 is input to the next-stage flip-flop circuit 102 without delay, the hold time t4 of the next-stage flip-flop circuit 102 is delayed due to the delay of CK2 with respect to CK1 as shown in FIG. Between the D input terminal 102b of the flip-flop circuit 102
The data (Q1) input from the device may change, so that the data may not be latched properly, that is, so-called data loss (data through) may occur.

Therefore, by inserting the delay buffer 251, the signal output from the Q output terminal 101a of the flip-flop circuit 101 is delayed as indicated by the broken line Q1 in FIG. 7, and the flip-flop circuit 102 of the next stage is delayed. D
Inputting to the input terminal 102b prevents the loss of data due to the delay of CK2 with respect to CK1. In the case of the gate array, since the layout of each element is automatically performed, the clock input terminal 101c of the flip-flop circuit of the preceding stage (for example, the flip-flop circuit 101) and the flip-flop circuit of the next stage (for example, the flip-flop circuit) It is unknown at the design stage how far the distance between the clock input terminal 102c and the clock input terminal 102c is, that is, the delay time t2 shown in FIG. 7 is unknown.
If the output signal is delayed to the extent shown by the broken line Q1 in FIG. 7, data loss may still occur. Therefore, the buffers 251, 252, 253, ... Are designed so as to secure a considerably large delay time in consideration of safety.

FIG. 8 is a diagram showing another example of a conventional shift register in which the flip-flop circuit shown in FIG. 5 is connected in multiple stages, and FIG. 9 is two flip-flops constituting the shift register shown in FIG. 6 is a timing chart showing the operation of the circuits 103 and 104. In FIG. 8, components corresponding to those of the flip-flop circuit (see FIG. 6) described above are assigned the same numbers as the numbers assigned in FIG. 6, and only the differences will be described.

In the shift register shown in FIG. 8, the Q of the flip-flop circuits 101, 102, 103, ...
The output terminals 101a, 102a, 103a, ... Are directly connected to the D input terminals 102b, 103b, 104b, ... of the next-stage flip-flop circuits 102, 103, 104 ,. Buffers 261, 262, 263, ... Are provided between clock input terminals of flip-flop circuits adjacent to each other so as to be input. In this case, the flip-flop circuit 1
If the delay t5 of the clock signal CK3 input to the clock input terminal 103c of the flip-flop circuit 103 with respect to the clock signal CK4 (see FIG. 9) input to the clock input terminal 104c of No. 04 is too small, the hold time t6 of the flip-flop circuit 104 is increased. There is a possibility that the Q output signal Q3 of the flip-flop circuit 103 may change during this period. Therefore, also in this case, it is necessary to secure a sufficient delay time as t5 ′ shown in FIG.

[0013]

As described above, the Q output signal on the front stage side is sufficiently delayed and input to the D input terminal of the next stage, or the clock signal sufficiently delayed on the front and rear sides is input. Thus, data loss can be prevented. However, in such a conventional configuration, (1) the flip-flop circuits 101, 102, 103,
Buffers 251, 252, 25 independent of 104, ...
, 261, 262, 263, ..., but each buffer 251, 252, 253 ,.
.., 262, 263, ... May require only two transistors, but one basic unit composed of four to eight transistors is used, resulting in waste. (2) Since it is unclear how much delay is needed at the design stage, it is also possible to provide a plurality of buffers in series for safety, and in this case, the circuit scale will be further increased. Become. (3) Since the delay element (buffer) is intentionally provided in the middle of the circuit, the operation of the circuit becomes slow and the circuit becomes unsuitable for high speed operation. There was a problem.

In view of the above-mentioned circumstances, the present invention minimizes the delay time so as not to cause data loss, thereby eliminating waste of the circuit and providing a flip-flop circuit which constitutes a sequential logic circuit capable of high-speed operation. Another object of the present invention is to provide a semiconductor integrated circuit.

[0015]

A semiconductor integrated circuit of the present invention for achieving the above object is generated based on a clock input terminal to which a clock signal is input and a clock signal input from the clock input terminal. And a flip-flop circuit having a clock output inverter or buffer for outputting a clock signal in phase with the clock signal input from the clock input terminal at substantially the same timing as the latest clock signal for opening and closing the internal gate And a semiconductor integrated circuit.

[0016]

In the semiconductor integrated circuit of the present invention, the flip-flop circuit inputs the clock signal input at substantially the same timing as the clock signal having the latest timing among the clock signals internally generated based on the input clock signal. Since it is configured to output a clock signal in the same phase as the above, wiring to input this output clock signal to the clock input terminal of the previous stage minimizes the delay time to prevent data loss and Is reliably prevented, and a sequential logic circuit suitable for high-speed operation is constructed. In addition, since it is not necessary to provide a buffer outside the flip-flop circuit, the circuit scale can be reduced. Further, in the present invention, since the in-phase clock signal is output to the outside of the flip-flop circuit via the clock output inverter or buffer, the clock can be output to the outside without affecting the opening / closing of the gate inside the flip-flop circuit. The signal is taken out, the setup time and the hold time are held constant, and at the same time, it contributes to high-speed operation.

[0017]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a circuit diagram showing a clock processing circuit in a flip-flop circuit according to an embodiment of the present invention, and corresponds to FIG. 5B in the conventional flip-flop circuit described above. In this figure, elements corresponding to the elements of the clock processing circuit shown in FIG. 5B are shown in FIG.
The numbers and symbols are the same as the numbers given to.

In the clock processing circuit shown in FIG. 1, the middle of the two inverters 22 and 23 is connected to the input terminal of the inverter 27, and the clock signal CKout having the same phase as the input clock signal CKin is output from the output terminal of the inverter 27. It is configured so that it can be taken out of the flip-flop circuit. In this case, the clock signal CKout is generated at a timing that almost coincides with the clock signal (here, clock signal φ) having the latest timing for opening and closing each gate (see FIG. 5A) inside the flip-flop circuit. It

FIG. 2 is a shift circuit constructed by using a flip-flop circuit according to one embodiment of the present invention, that is, a flip-flop circuit including the circuit shown in FIG. 5A and the clock processing circuit shown in FIG. It is a figure showing a register. In this figure, the components corresponding to the components of the conventional shift register (see FIGS. 6 and 8) described above are denoted by the same numbers as those given in FIGS. 6 and 8, and only the differences will be described. To do.

3 and 4 are timing charts and operation explanatory diagrams of the flip-flop circuits 103 and 104 in the shift register shown in FIG. 2, respectively. In the shift register circuit shown in FIG. 2, the flip-flop circuit 10
No buffer is provided outside 1, 102, 103, 104, ..., As shown in the figure, clock output terminals 102d, 103d, 104d, ... Of flip-flop circuits 102, 103, 104 ,. , And the clock input terminals 101c, 102c, 103c, ... Of the flip-flop circuits 101, 102, 103 ,.

In the case of the shift register configured as described above, as shown in FIGS. 3 and 4, the flip-flop circuit 1
04, the clock signal CK4 input to the clock input terminal 104c rises (step (a) (FIG. 4)),
The signal Q3 output from the Q output terminal of the flip-flop circuit 103 is fetched (step (b)), and the flip-flop circuit 103 is always required after this fetching is completed.
The clock signal CK3 input from the clock input terminal 103c of the flip-flop circuit 103 rises (step (C)) so that the signal Q3 output from the Q output terminal 103a of the same changes. Flip-flop circuit 1 after a lapse of time
The signal Q3 output from the Q output terminal 103a of No. 03 changes (step (d)). Thus, as shown in FIG. 1, the clock signal C having the same timing as the clock signal φ
Kout, that is, inside each flip-flop circuit, with respect to the clock signal input to each flip-flop circuit,
Delayed by the minimum amount of time that data loss will not occur,
Clock signal CKout in phase with the input clock signal
Is generated and output, and the clock signal CKout is input to the clock input terminal of the previous stage,
Data loss is prevented with a minimum delay time and without providing an external buffer.

Further, since the delay time is minimized and it is not necessary to provide a buffer having a large delay time in consideration of safety, a sequential logic circuit suitable for high speed operation is realized and, because of the buffer, Since it is not necessary to use an extra basic unit, the circuit scale can be reduced. Although the inverter 27 is used for clock output in the clock processing circuit shown in FIG. 1, it may be a buffer instead of the inverter depending on the configuration of the clock processing circuit.

In the above embodiment, the shift register is taken as an example to describe the embodiment of the present invention. However, the present invention is not limited to the case of forming a shift register, and a sequential logic circuit is formed by using a flip-flop circuit. It can be widely applied when it is constructed.

[0024]

As described above, according to the semiconductor integrated circuit of the present invention, the flip-flop circuit constituting this semiconductor integrated circuit is opened / closed by the internal gate which is generated based on the clock signal input to the flip-flop circuit. Since there is an inverter or buffer for clock output that outputs a clock signal in phase with the clock signal input from the clock input terminal at approximately the same timing as the clock signal with the latest timing for A semiconductor integrated circuit having a sequential logic circuit that can be reliably prevented with a minimum delay time, has a smaller circuit scale than the conventional one, and can operate at high speed is realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a clock processing circuit in a flip-flop circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a shift register configured using a flip-flop circuit according to an embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of two flip-flop circuits in the shift register shown in FIG.

FIG. 4 is an operation explanatory diagram of two flip-flop circuits in the shift register shown in FIG.

FIG. 5 is a diagram showing a configuration example of a conventional D-type flip-flop circuit.

FIG. 6 is a diagram showing an example of a conventional shift register in which the flip-flop circuits shown in FIG. 5 are connected in multiple stages.

7 is a timing chart showing the operation of two flip-flop circuits in the shift register shown in FIG.

FIG. 8 is a diagram showing another example of a conventional shift register in which the flip-flop circuits shown in FIG. 5 are connected in multiple stages.

9 is a timing chart showing the operation of two flip-flop circuits in the shift register shown in FIG.

[Explanation of symbols]

11 D Input Terminal 12 Clocked Inverter 13, 15, 17, 19, 20, 21, 21, 23, 2
7 inverters 14, 16, 18 transfer gates 101, 102, 103, 104, flip-flop circuits 101a, 102a, 103a, 104a Q output terminals 101b, 102b, 103b, 104b D input terminals 101c, 102c, 103c, 104c clock input terminals 102d, 103d, 104d clock output terminals

Claims (1)

Claim: What is claimed is: 1. A clock input terminal to which a clock signal is input, and a clock signal having the latest timing for opening and closing an internal gate, which is generated based on the clock signal input from the clock input terminal. A semiconductor integrated circuit comprising a flip-flop circuit having a clock output inverter or a buffer for outputting a clock signal in phase with a clock signal input from the clock input terminal at substantially the same timing.