JPH05298877A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the occupancy area of a sense amplifier and to reduce power consumption and a peak current value. CONSTITUTION:Memory cells M are arranged at the intersecting positions of (m) bit line pairs BLj and BLj# with (n) word lines WLi. The same sense amplifier SA is connected to the one end of the respective bit line pairs BLu and BLj# with bus transistor pairs CTj and CTj#. The bus transistors CTj and CTj# are turned on based on a column address signal, select minute potential difference DELTAVj generated in the a pair of the bit line pairs BLj and BLj# and transmit it to the sense amplifier SA. Then, the information of the memory cell M read in the (m) of bit line pairs BLj and BLj# is selectively amplified by the one sense amplifier SA so that the number of the sense amplifier is reduced, the occupancy area of the sense amplifier is reduced and power consumption and the peak current value are reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (hereinafter abbreviated as DRAM).

[0002]

2. Description of the Related Art Conventionally, there is a DRAM as shown in FIG. This DRAM has m arranged in one direction.
, SAm (hereinafter, any sense amplifier is referred to as SAj) and a pair of bits connected to these sense amplifiers SAj. Line BL1, BL1 # ・ BL2, BL2 # ・…
・ BLm, BLm # (Hereinafter, any bit line pair can be BLj, BLj #
,) And n word lines WL1, WL2, ..., Which extend in the direction intersecting these bit line pairs BLj, BLj #.
WLn (hereinafter, any word line is referred to as WLi) and 2
It has book dummy word lines DWL1 and DWL2 (hereinafter, any dummy word line is referred to as DWLk).

The word line WLi and the bit line pair BLj, B
A memory cell M composed of one transistor TR and one capacitor C as shown in FIG. 2 is provided at the intersection of Lj #.
Are alternately arranged on one of the bit lines forming the bit line pair BLj, BLj #. Similarly, at the intersection of the dummy word line DWLk and the bit line pair BLj, BLj #, one of the dummy cells DM having the same structure as the memory cell M constitutes the bit line pair BLj, BLj #. They are arranged alternately on the bit lines.

The DRAM having the above structure operates as follows. In the initial state, each bit line pair BLj, BLj # (j
= 1 to m) and each dummy cell DM is precharged to 1/2 of the power supply voltage. In the above circuit, a specific word line WLi is activated, and m memory cells M at the intersections of m bit lines BLj (j = 1 to m) intersecting the word line WLi are generated. Consider the case where all are selected. In this case, at the same time as the word line WLi, the dummy word line DWL2 (if i is an even number, the dummy word line DWL2
1) is also activated, and all the m dummy cells DM at the intersections of the m bit lines BLj # (j = 1 to m) intersecting the dummy word line DWL2 are also selected.

In this way, when the m memory cells M and the m dummy cells DM are selected, all the transistors TR in the selected memory cells M and dummy cells DM are rendered conductive. The charges stored in the capacitors C in the m memory cells M and the m dummy cells DM are connected to 2m bit lines (that is, m bit line pairs BLj, BLj #). Read out. Then, the bit line pair BLj, BLj # (j = 1 to m)
There is a minute potential difference between the two.

Then, the bit line pair BLj, BLj #
Of the bit line BLj or the bit line BLj # is set to the power supply potential while the low potential side is set to the power source potential by differentially amplifying a minute potential difference generated between the bit line BLj and the bit line BLj #. A so-called sensing operation is performed in which the potential of the bit line existing in the above is set to zero potential.

After that, a specific column address signal C
The level of Sj becomes "H", the corresponding bus transistor pair Gj, Qj # becomes "on", and the specific sense amplifier S
Only the output from Aj is output to the input / output line pair IO, IO # via the bus transistors Qj, Qj #. In this way, the information stored in the specific memory cell M among the memory cells M is selectively read. Such a method of reading information is called a sense method.

[0008]

However, in the above-described conventional method of reading information by the sensing method,
There are the following problems. That is, any word line WL
When i is selected, all bit line pairs BLj, BLj # (j
It is necessary to simultaneously drive all the sense amplifiers SAj (j = 1 to m) to amplify the minute potential difference read out to (= 1 to m). Therefore, there is a problem that the number of pairs of bit lines "m" is required for the sense amplifiers, and the power supply lines of the respective sense amplifiers are at the intermediate potential for a long time, resulting in large power consumption. Further, since all the sense amplifiers operate at the same time, the peak current value is large and there is a problem that the stability of the circuit is poor.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of reducing the occupied area of the sense amplifier and reducing the power consumption and the peak current value.

[0010]

To achieve the above object, a semiconductor memory device according to the present invention includes a predetermined number of bit line pairs, word lines extending in a direction intersecting the bit line pairs, the bit lines, and In a semiconductor memory device having memory cells arranged at intersections of word lines, one sense amplifier connected to one end of each bit line pair and each bit line controlled by a column address signal. A transistor pair for turning on / off the connection between the bit line and the sense amplifier, which constitutes a pair, is selected, an electric charge is read from the memory cell by selecting an arbitrary word line, and the predetermined number of bit lines. Of the minute potential difference generated in the pair, only the minute potential difference of the bit line pair selected by the transistor turned on based on the column address signal is increased. It is characterized in that rewriting is carried out after being sent to the sense amplifier, and then a minute potential difference generated in other bit line pairs is successively sent to the sense amplifier to carry out rewriting.

[0011]

When an arbitrary word line is selected, the charge stored in the memory cell arranged at the intersection of this word line and the bit line pair is read out and crosses the selected word line. A minute potential difference is generated between a predetermined number of each bit line pair. On the other hand, based on the column address signal, a pair of transistor pairs for turning on / off the connection between one end of the bit line forming each bit line pair and one sense amplifier is turned on. Then, only the minute potential difference of the bit line pair selected by the "on" transistor pair is sent to the sense amplifier.

Thus, the minute potential difference of the selected bit line pair is input to the sense amplifier, and only the information read from the target memory cell is amplified. Then, after the rewriting is performed, the transistor pairs corresponding to the unselected bit line pairs are sequentially turned “on / off” to sense / rewrite the non-selected bit line pairs. Is repeated in sequence.

[0013]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a circuit configuration diagram of a DRAM in this embodiment. This DRAM has n word lines WLi (i =
1 to n), two dummy word lines DWLk (k = 1, 2), and m pairs of bit lines BLj, BLj # (j = 1 to m).

Each bit line pair BLj, BLj # (j = 1 to 1)
m), m sets of bus transistors CTj, CTj # (j =
1 to m), the same sense amplifier SA is connected. Then, as in the case of FIG. 4, the word lines WLi
The memory cell M is arranged at the intersection of the bit line pair BLj, BLj #, while the dummy cell DM is arranged at the intersection of the dummy word line DWLk and the bit line pair BLj, BLj #.

The memory cell M, as shown in FIG.
It is composed of a MOS (metal oxide semiconductor) transistor TR and a capacitor C. Then, the MOS transistor TR
The source terminal S is connected to the bit line BLj (BLj #), while the gate terminal G is connected to the word line WLi. The drain terminal D is connected to one electrode of the capacitor C. The other terminal of the capacitor C is connected to the common electrode PE. On the other hand, the dummy cell DM has the same structure as the memory cell M except that the gate terminal G of the MOS transistor is connected to the dummy word line DWLk.

A memory cell M in the DRAM having the above structure
When reading the information stored in, the bit line pair BLj, BLj # (j = 1 to m) is precharged to 1/2 of the power supply voltage in advance. Further, the precharge voltage is written in the dummy cell DM. Bus transistor control signal C
Sj is inactive in the initial state, and the bus transistors CTj and CTj # are "off". In this state, the DRAM is hereafter described according to the timing chart of FIG.
To operate.

First, a specific word line WLi and a dummy word line DWLk (k is "1" when i is an even number and k is "2" when i is an odd number) are activated, The MOS transistors TR of the memory cell M and the dummy cell DM are turned on. Thus, information on the m memory cells M connected to the word line WLi and the dummy word line D
Information of m dummy cells DM connected to WLk is read to the bit line pair BLj, BLj # (j = 1 to m), and a minute potential difference ΔVj is generated between the bit line BLj and the bit line BLj #. Occurs. In this state, a minute potential difference is generated in all the bit line pairs. Up to this point, the process is the same as that of the conventional DRAM shown in FIG.

Next, a specific bus transistor control signal CSj is activated based on the column address signal. Then, the bus transistor pair CTj, C to which the activated bus transistor control signal CSj is input.
Tj # is turned on, and only the minute potential difference ΔVj of the specific bit line pair BLj, BLj # selected based on the column address signal is input to the sense amplifier SA.

After that, the bus transistor pair CTj and CTj # which are "on" are turned off. And
The minute potential difference ΔVj is amplified by the sense amplifier SA so that the potential on the high potential side becomes the power source potential, while the potential on the low potential side becomes zero potential.

When the sensing operation is completed in this way, the output transistor control signal OT input to the gates of the output transistor pair I1, I2 connected to the output side of the sense amplifier SA is activated, and the output transistor pair I1, I2 is activated.
Turn on. Then, the information read from the target memory cell M is output to the I / O line formed of the input / output line pair IO, IO #.

At the same time, the specific bus transistor control signal CSj is activated again to turn on the bus transistor pair CTj, CTj #, and the specific memory cell M.
Rewrite to.

By the way, for the bit line pair BLo, BLo # (o = 1 to i, k to m) not selected at the time of reading information, after the rewriting of the selected bit line pair BLj, BLj # is completed. , The bus transistor control signal CSo is activated to turn on the bus transistor pair CTo, CTo #, and the minute potential difference ΔVo is transmitted to the sense amplifier SA. After that, the bus transistor control signal CSo is deactivated to turn off the bus transistors CTo and CTo # to perform the sensing operation. After the sensing operation is completed, the bus transistor control signal CSo is activated again to activate the bus transistor pair C.
To and CTo # are turned on and the memory cell M is rewritten.

In this way, the bus transistor control signal CSo (o = 1 to j, km) is sequentially activated / deactivated / activated regardless of the column address signal, and at the time of reading the information. Unselected bit line pair BLo, BLo #
Each minute potential difference ΔVo generated at 1 is serially sent to the sense amplifier SA to perform a sensing operation and rewriting is performed. Then, when the rewriting operation for all the memory cells M is completed, the word line and the dummy word line are deactivated.

As described above, in this embodiment, the minute potential difference ΔVj of the specific bit line pair BLj, BLj # is selected based on the column address signal and sent to one sense amplifier SA. Bit line pairs BLj,
One may be provided for BLj #. Therefore, the area occupied by the sense amplifier can be reduced and the chip can be downsized. Further, since the sense amplifier SA is serially operated based on the bus transistor control signal CSj, the operating time of the sense amplifier SA is dispersed, the peak current value is lowered, and the stability is increased. Furthermore, since the shoot-through current during the sensing operation is reduced, DR that can reduce power consumption
AM can be built.

In the above embodiment, one sense amplifier SA is provided for m bit line pairs BLj, BLj #. Regarding the bit line logarithm “m” at that time,
It is desirable to determine it in consideration of the response speed of the sense amplifier and the holding time of the minute potential difference ΔVj.

[0026]

As is apparent from the above, in the semiconductor memory device of the present invention, one end of a predetermined number of bit line pairs is connected to the same sense amplifier via a transistor pair, and the transistor of the above-mentioned transistors is connected based on a column address signal. Since the on / off is controlled, only the minute potential difference generated in a specific bit line pair is sent to the sense amplifier based on the column address signal, and the sensing operation can be selectively executed. Therefore, according to the present invention, it suffices that there is one sense amplifier for the predetermined number of bit line pairs, and the area occupied by the sense amplifier can be reduced to reduce the power consumption and the peak current value. A memory device can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a semiconductor memory device of the present invention D
It is a circuit block diagram in RAM.

FIG. 2 is a diagram showing a specific circuit example of a memory cell M in FIG.

FIG. 3 is a timing chart when reading information from the DRAM shown in FIG.

FIG. 4 is a circuit configuration diagram of a conventional DRAM.

[Explanation of symbols]

BLj, BLj # ... Bit line pair, CTj, CTj # ...
Bus transistor pair, CSj ... Bus transistor control signal, DM ... Dummy cell, DWL1, D
WL2 ... dummy word line, I1, I2 ... output transistor,
IO, IO # ... I / O lines, M ... Memory cells,
OT ... Output transistor control signal,
SA ... sense amplifier, WLi ... word line.

Claims (1)

[Claims] 1. A semiconductor memory device having a predetermined number of bit line pairs, word lines extending in a direction intersecting with the bit line pairs, and memory cells arranged at intersections of the bit lines and the word lines. In one differential type sense amplifier to which one end of each bit line pair is connected, and the bit line and the differential type sense amplifier, which are controlled based on a column address signal, to form each bit line pair. Of the minute potential difference generated in the predetermined number of bit line pairs read from the memory cell by selecting any word line, the column address signal is provided. A semiconductor memory characterized in that only the minute potential difference of the bit line pair selected by the transistor turned on based on the above is sent to the differential sense amplifier. Apparatus.