JPH0529858B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a photodetection circuit, and is used, for example, in a photoelectric smoke detector or a photoelectric intrusion sensor.

[Prior art] Figure 11 shows a conventional example of a photoelectric smoke detector
14398).
In the figure, l ₁ and l ₂ are sensor lines connected to the receiver. The receiver supplies DC power voltage between the sensor lines l ₁ and l ₂ , and when the sensor lines l ₁ and l ₂ are short-circuited, it detects an increase in line current and issues a fire alarm signal. report. 1 is a diode bridge whose AC input terminal is connected to the sensor lines l ₁ and l ₂ and whose DC output terminal is connected to the internal circuit of the sensor. This diode bridge 1 may be omitted, but during construction, workers can connect the sensor line l ₁ ,
This is provided to enable normal operation even if _l2 is wired with reverse polarity. Reference numeral 2 designates a switching circuit, which is composed of a self-holding circuit using a thyristor element or a transistor, and is turned on by a trigger signal from the counting circuit 12 to connect the sensor lines l ₁ and l _{2 .}
This short-circuits the terminals and sends a smoke detection signal to the receiver. 3 is a constant voltage circuit which converts the DC voltage obtained at the DC output terminal of the diode bridge 1 into a predetermined constant voltage and supplies it to the internal circuit. 4 is an oscillation circuit which generates a reference clock signal. 5 is a timing control circuit, and oscillation circuit 4
The frequency of the reference clock signal from the light emitting element 6 is divided.
A light emission control signal is generated to control the light emission timing of the light emitting device. 6 is a light emitting element made of an LED (light emitting diode). A drive circuit 7 drives the light emitting element 6 intermittently according to a light emission control signal output from the timing control circuit 5. Reference numeral 8 denotes a light receiving element, which receives weak pulsed light generated when the pulsed light from the light emitting element 6 hits smoke particles and is scattered. Reference numeral 9 denotes an amplifier, which amplifies the weak electrical signal from the light receiving element 8. 10 is a comparator, which compares the output signal from the amplifier 9 and the reference signal from the reference voltage source 11.
It determines the presence or absence of smoke, and generates an output signal when it is determined that smoke has entered. A reference voltage source 11 supplies a reference signal to the comparator 10 for determining the presence or absence of smoke. 12 is a count circuit, and comparator 1
A trigger signal is supplied to the switching circuit 2 when the output signal from 0 is obtained at least twice.

[Problems to be Solved by the Invention] As described above, the photoelectric smoke detector includes the light receiving element 8 for detecting light scattered by smoke. This light receiving element 8 is generally made of a silicon photodiode (SPD), and the temperature coefficient of its light receiving output current is positive. Furthermore, the amplifier 9 that converts the light-receiving output current of the light-receiving element 8 into a voltage signal includes a resistance element for current-voltage conversion, and assuming that the temperature coefficient of this resistance element is also positive, the light detection circuit The output voltage increases as the ambient temperature increases. For this reason, there is a problem in that the presence or absence of smoke cannot be accurately determined, leading to false alarms occurring at high temperatures and false alarms occurring at low temperatures.

The present invention has been made in view of these points, and its purpose is to offset the temperature coefficient of the light-emitting side circuit and the temperature coefficient of the light-receiving side circuit, thereby increasing the overall output according to the ambient temperature. An object of the present invention is to provide a photodetection circuit in which the voltage does not fluctuate.

[Means for Solving the Problems] In order to solve the above problems, the photodetection circuit according to the present invention emits light with a brightness corresponding to the drive current _I6 , as shown in FIG. light emitting element 6
, a drive circuit 7 that supplies a drive current _I6 to the light emitting element 6, a light receiving element 8 that receives a part of the light emitted from the light emitting element 6, and a voltage signal V that outputs the light receiving output current I8 of the light receiving element ₈ . ₀ , the temperature coefficient of the luminous efficiency of the light emitting element ₆ , the temperature coefficient of the drive current _I6 of the drive circuit 7, and the light receiving element 8.
The temperature coefficient of the received light output current _I8 for the received light amount is
This is characterized in that the sum of the temperature coefficients of the resistance values of the resistance element _R8 is approximately zero.

[Function] In the circuit shown in Fig. 1, the temperature coefficient of the received light output current _I8 with respect to the amount of light received by the light receiving element 8 is
Assuming that the temperature coefficient of the resistance value of the resistance element _R8 is 2000 ppm/°C, the temperature coefficient of the amount of light received by the light-receiving circuit is 5000 ppm/°C. Therefore, the temperature coefficient of the amount of light emitted in the light emitting circuit is -
5000ppm/℃, the output voltage of the photodetector circuit
V ₀ does not vary with ambient temperature. When a light emitting diode (LED) is used as the light emitting element 6,
Its luminous efficiency (the amount of light emitted with respect to the driving current _I6 ) decreases as the temperature rises, and its temperature coefficient, for example, -
If the temperature coefficient is 6250 ppm/°C, the temperature coefficient of the drive current I ₆ by the drive circuit 7 may be set to 1250 ppm/°C. Specifically, (n
-1) By adjusting the number of diode series arrays, the temperature coefficient of the output voltage of the photodetection circuit can be made zero.

For more detailed structure and operation of the present invention,
This will be explained in detail in the description of the embodiments below.

[Embodiment] FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention, and in the conventional block diagram shown in FIG. 11, the circuit configuration of the switching circuit 2, constant voltage circuit 3, and drive circuit 7 is This is a concrete example. First, the switching circuit 2 includes a PNP transistor Tr ₁ and an NPN transistor Tr ₂ , which are connected to form a self-holding circuit. The emitter of PNP transistor Tr ₁ is connected to the positive output terminal of diode bridge 1,
The emitter of the NPN transistor Tr ₂ is connected to the negative output terminal of the diode bridge 1 .
The base of the PNP transistor Tr ₁ is connected to the collector of the NPN transistor Tr ₂ , and the collector of the PNP transistor Tr ₁ is connected to the base of the NPN transistor Tr ₂ . Each transistor Tr ₁ ,
Resistors R ₁ and R ₂ are connected in parallel between the base and emitter of Tr ₂ . The base of the NPN transistor Tr ₂ serves as a trigger terminal and is connected to the output of the count circuit 12 via a diode D ₀ .

The output signal OUT of the count circuit 12 is “High”
When the level is reached, the base current flows to the NPN transistor Tr ₂ via the diode D ₀ , the base current flows to the PNP transistor Tr ₁ due to the collector current of the NPN transistor Tr 2, and from then on, the base current flows to the PNP transistor Tr ₁ due to the collector current of the PNP transistor Tr ₁ . The base current of Tr ₂ is supplied, and the switching circuit becomes a self-holding state (latched-up state), and the DC output terminals of the diode bridge 1 are short-circuited, so that the sensor lines l ₁ and l ₂ are short-circuited.
As a result, the line current flowing through the sensor lines l ₁ and l ₂ increases, and the receiver connected to the other end of the sensor lines l ₁ and l ₂ detects a smoke detection signal. Thereafter, the switching circuit 2 maintains its self-holding state until the reset switch is operated on the receiver side to cut off the line current flowing through the sensor lines l ₁ and l ₂ .

Next, the configuration of the constant voltage circuit 3 will be explained.
The constant voltage circuit 3 includes three NPN transistors Tr ₃ ,
Including Tr ₄ and Tr ₅ . The collector of transistor Tr ₃ is connected to the positive output terminal of diode bridge 1 . The base of the transistor Tr ₃ is connected through a first constant voltage element consisting of a series circuit of a Zener diode ZD ₁ and a diode D ₁ , and a second constant voltage element consisting of a series circuit of a Zener diode ZD ₂ and a diode D ₂ . , connected to the negative output terminal of diode bridge 1. The diodes D ₁ and D ₂ are provided to compensate for the temperature coefficient of the Zener voltage of the Zener diodes ZD ₁ and ZD ₂ . 1st and 2nd
A current flows through the constant voltage element from the positive output terminal of the diode bridge 1 via the bias resistor _R3 connected between the collector and base of the transistor _Tr3 . As a result, the Zener voltage V _ZD1 of the Zener diode ZD1 is applied across the first constant voltage element _.
A constant voltage (V _ZD1 + V _F ) is generated, which is the sum of the forward voltage drop V _F of the diode D ₁ and the forward drop voltage V F of the diode D 1 . Additionally, a Zener diode is connected across the second constant voltage element.
A constant voltage (V _ZD2 + V _F ) is generated that is the sum of the zener voltage V _ZD2 of ZD ₂ and the forward drop voltage V _F of the diode D ₂ . Therefore, a voltage (V _ZD1 +V _ZD2 +2×V _F ), which is the sum of the voltages across the first and second constant voltage elements, is generated at the base of the transistor Tr ₃ . Assuming that the base-emitter voltage of the transistor Tr ₃ is V _BE3 , the emitter voltage of the transistor Tr ₃ is constant at (V _ZD1 +V _ZD2 +2×V _F -V _BE3 ). This voltage is charged to the power supply capacitor _C1 via the low resistance _R4 , and the power supply lines V _CC , V _SS1
The power supply voltage will be between. Also, if the base-emitter voltage of transistor Tr ₅ is V _BE5 , the emitter voltage of transistor Tr ₅ is (V _ZD2 + V _F − V _BE5 )
becomes constant. This voltage is applied to the power supply capacitor
It is charged to _C2 and becomes the power supply voltage between the power supply lines _VDD and _VSS2 . Transistor Tr ₄ is provided to prevent overcurrent, and if the level is appropriate for the emitter current of transistor Tr ₃ , low resistance R ₄
Since the voltage developed across the transistor is small,
Tr ₄ does not operate, but when the emitter current of transistor Tr ₃ increases abnormally, the base current flows to transistor Tr ₄ due to the voltage generated across low resistance R ₄ , and the base current of transistor Tr ₃ flows between its collector and emitter. The base current is shunted and the emitter current of transistor Tr ₃ is limited.

Next, the configuration of the drive circuit 7 will be explained. Drive circuit 7 is two NPN transistors
Tr ₆ , Tr ₇ and three NMOS transistors Tr ₈ ,
Includes Tr ₉ , Tr ₁₀ and one PMOS transistor Tr ₁₁ , and receives a light emission control signal from the timing control circuit 5.
When LEDON is at the “High” level, the drive current _I6 is applied to the light emitting element 6, but the light emission control signal
When LEDON is at the "Low" level, not only is no current passed through the light emitting element 6, but the drive circuit 7 itself is in a high impedance state, consuming no current at all.

Light emission control signal from timing control circuit 5
LEDON is applied to the gate of NMOS transistor _Tr8 . The source of the NMOS transistor Tr ₈ is connected to the power supply line V _SS1 , and the drain is connected to the power supply line V _CC via a bias resistor R ₅ . The connection point between the resistor _R5 and the drain of the NMOS transistor _Tr8 is the NMOS transistor _Tr9 ,
Connected to the gates of Tr ₁₀ and PMOS transistor Tr ₁₁ . The sources of the NMOS transistors Tr ₉ and Tr ₁₀ are connected to the power supply line V _SS1 , and the source of the PMOS transistor Tr ₁₁ is connected to the power supply line V _CC . The drain of NMOS transistor Tr ₉ and
The drains of the PMOS transistors _Tr11 are commonly connected to the bases of the NPN transistors _Tr6 .
The collector of NPN transistor Tr ₆ is the power line
It is connected to V _CC , its emitter is connected to the cathode of the Zener diode ZD ₃ via the resistor R ₆ , and the anode of the Zener diode ZD ₃ is connected to the power supply line V _SS1 . The cathode of the Zener diode ZD ₃ is connected to the drain of the NMOS transistor Tr ₁₀ , and is also connected to the base of the NPN transistor Tr ₇ via a series array of (n-1) diodes. The emitter of the NPN transistor _Tr7 is connected to the power supply line _VSS1 via a resistor _R7 . Further, the collector of the NPN transistor Tr ₇ is connected to the cathode of the light emitting element 6,
The anode of the light emitting element 6 is connected to the power supply line V _CC .

The operation of the drive circuit 7 will be explained below. Light emission control signal from timing control circuit 5
When LEDON becomes "High" level, the NMOS transistor Tr ₈ turns on, and the gate potentials of the NMOS transistors Tr ₉ and Tr ₁₀ and the PMOS transistor Tr ₁₁ decrease, so the NMOS transistors Tr ₉ and Tr 10 turn off, and the PMOS transistor Tr ₈ turns on. transistor
Tr ₁₁ is turned on. Therefore, the base potential of the NPN transistor Tr ₆ rises, and a current flows through the series circuit of _{the resistor R 6 and} the Zener diode ZD ₃ through the collector and emitter of the NPN transistor Tr 6. As a result, a voltage equal to the Zener voltage V _ZD3 is generated at the cathode of the Zener diode _ZD3 . The voltage obtained by subtracting the forward voltage drop (n-1) x V _F of the series array of (n-1) diodes from this voltage is applied to the base of the NPN transistor Tr _{7 .} The light emitting element 6 is turned on, and a driving current _I6 flows through the light emitting element 6.

Next, when the light emission control signal LEDON from the timing control circuit 5 becomes “Low” level, the NMOS
Transistor Tr ₈ is turned off, and NMOS transistors Tr ₉ and Tr ₁₀ are turned off by bias resistor R ₅ .
Since the gate potential of the PMOS transistor Tr ₁₁ rises, the NMOS transistors Tr ₉ and Tr ₁₀ are turned on, and the PMOS transistor Tr ₁₁ is turned off. Therefore, the base potential of the NPN transistor Tr ₆ drops, and no current flows between the collector and emitter of the NPN transistor Tr ₆ . Also,
Since both ends of the Zener diode ZD ₃ are short-circuited by the NMOS transistor Tr ₁₀ , the cathode potential of the Zener diode ZD ₃ is lowered, the NPN transistor Tr ₇ is turned off, and the drive current I ₆ of the light emitting element 6 is stopped.

The power-on reset circuit 13 detects the voltage rise of the power supply capacitor C ₁ and supplies a power-on reset signal RESET to the oscillation circuit 4 , timing control circuit 5 , and count circuit 12 . The analog signal processing circuit 14 includes an amplifier 9, a comparator 10, and a reference voltage source 11 shown in FIG. The oscillation circuit 4 supplies a reference clock signal OSC to the timing control circuit 5. The timing control circuit 5 divides the reference clock signal OSC and supplies a light emission control signal LEDON to the drive circuit 7.
Timing control signal to analog signal processing circuit 14
PHI1 and PHI2 are supplied, and the reset signal RST and up clock signal are supplied to the count circuit 12.
Supply UPCLK. Analog signal processing circuit 14
A comparison output signal COMP is sent to the count circuit 12 from
is supplied. The oscillation circuit 4, timing control circuit 5, analog signal processing circuit 14, and count circuit 12 operate at low voltage and consume little current.
Powered by capacitor _C2 . On the other hand, since the drive circuit 7 of the light emitting element 6 instantaneously consumes a large amount of current, it is supplied with power from the capacitor _C1 .
In this way, the power line V _CC of the drive circuit 7
By separating the power supply line V _DD from the power supply line V DD of other circuits, there is no fear that the power supply voltage of other circuits will drop instantaneously when the light emitting element 6 emits light, and malfunctions of other circuits can be prevented.

FIG. 3 shows an oscillation circuit 4, a timing control circuit 5,
Analog signal processing circuit 14 and count circuit 12
FIG. 2 is a circuit diagram specifically showing the configuration of FIG.

First, the oscillation circuit 4 is a capacitor for setting a time constant.
It consists of C _T and resistor R _T , two inverters G ₁ and G ₂ , and a NAND gate G ₃ for oscillation control. NAND
One input of the gate G ₃ is connected to the output of the inverter G ₁ through a resistor R _T and also connected to the input of the inverter G ₁ and the inverter through a capacitor C _T.
Connected to the output of _G2 . The output of NAND gate G ₃ is connected to the input of inverter G ₂ , and the NAND
A power-on reset signal RESET is input to the other input of gate _G3 via inverter _G4 . When the power-on reset signal RESET goes to the "Low" level, the output of the inverter _G4 goes to the "High" level, the NAND gate _G3 becomes in a state where the signal can pass, and the output of the inverter _G2 is connected to the resistor _RT. A reference clock signal OSC with a period determined by the time constant of the capacitor C _T is obtained.

This reference clock signal OSC is input to a frequency dividing circuit 5a in the timing control circuit 5. The frequency dividing circuit 5a is composed of 15 stages of D flip-flops connected in cascade, and each stage's D flip-flop has its inverted output connected to its own data input D, and is also connected to the clock input CLK of the next stage. There is. The reference clock signal OSC is supplied to the clock input CLK of the D flip-flop in the first stage, and the output Q of the D flip-flop in the final stage is
A frequency-divided output B15 of the reference clock signal OSC is obtained.

This frequency-divided output B15 is input to the shift register circuit 5b in the timing control circuit 5. The shift register circuit 5b consists of seven stages of D flip-flops connected in cascade, and each stage's D flip-flop sends its output Q to the data input D of the next stage.
It is connected to the. The data input D of the first-stage D flip-flop is connected to the frequency division output B15 of the frequency division circuit 5a.
is supplied. The clock input CLK of the D flip-flop in each stage is connected to the output Q (divided output
_B2 ) is supplied.

Note that the frequency dividing circuit 5a and the shift register circuit 5
A power-on reset signal RESET is supplied to the reset input R of each D flip-flop in FIG.

Outputs Q ₃ , ₃ , Q ₄ , of the third to seventh stage D flip-flops in the shift register circuit 5b
Q ₅ , ₅ , ₆ , ₇ and frequency division output of frequency divider circuit 5a
_B14 is input to the AND gates _G5 to _G9 of the logic circuit 5c in the timing control circuit 5 as shown, and the control signals PHI1, PHI2, LEDON,
Generate RST and UPCLK respectively.

Next, the amplifier 9, the comparator 10 and the reference voltage source 1
The configuration of the analog signal processing circuit 14 including the analog signal processing circuit 1 will be described.

The amplifier 9 is a three-stage operational amplifier OP ₁ , OP ₂ ,
The non-inverting input of each operational _amplifier is connected to the reference voltage _Vr from the reference voltage circuit 15.
is applied. The cathode of a light receiving element 8 made of a silicon photodiode (SPD) is connected to the inverting input of the first stage operational amplifier _OP1 .
The anode of the light receiving element 8 is connected to the power supply line V _SS2 . Therefore, the PN junction of the light receiving element 8 is reverse biased, and the photocurrent flowing in the opposite direction through the PN junction due to light irradiation is detected as a voltage signal by the operational amplifier _OP1 . For this reason, a high resistance is used as the feedback resistor _R8 connected between the output and the inverting input of the operational amplifier _OP1 . The second stage operational amplifier OP ₂ constitutes a voltage amplification circuit, and its voltage amplification factor is determined by the input resistance R ₉
It is determined by the ratio of R and feedback resistor _R10 . The third stage operational amplifier _OP3 also constitutes a voltage amplification circuit, and its voltage amplification factor is determined by the ratio of the input resistance _R11 and the feedback resistance _R12 . The output of operational amplifier _OP3 is connected to one end of capacitor _C3 for DC cut, and the other end of capacitor _C3 is connected to the non-inverting input of operational amplifier _OP4 . The output of operational amplifier OP ₄ is fed back to its inverting input, so operational amplifier OP ₄ is a buffer amplifier that acts as an impedance converter. The output of operational amplifier OP ₄ is
It is connected to the non-inverting input of the comparator operational amplifier OP ₅ via a low-pass filter consisting of a resistor R ₁₃ and a capacitor C ₄ . Note that the other end of capacitor _C3 for DC cut is connected to the analog switch.
It is connected to the output of the reference voltage circuit 15 via _SW1 . The output of the reference voltage circuit 15 is an operational amplifier.
Applied to the non-inverting input of OP ₆ . operational amplifier
The output of OP ₆ is connected to the power supply line V _SS2 via resistors R ₁₄ and R ₁₅ . The connection point between resistor _R14 and resistor _R15 is fed back to the inverting input of operational amplifier _OP6 . The reference voltage V _REF obtained from the resistor R ₁₄ is applied to the inverting input of the operational amplifier OP ₅ for the comparator. The output of the operational amplifier OP ₅ is an RS flip-flop 12 consisting of NOR gates G ₁₀ and G ₁₁ .
This is the set input for a. A reset signal RST output from an AND gate _G8 is supplied to the reset input of this RS flip-flop 12a. Further, the output of the RS flip-flop 12a is an up-down selection signal UDS of the up-down counter 12b. The power-on reset signal RESET is supplied to the reset input R of the up-down counter 12b, and the up-clock signal UPCLK output from the AND gate _G9 is supplied to the up-clock input UPCLK.

FIG. 4 shows the circuit configuration of the count circuit 12. The count circuit 12 is the above-mentioned NOR gate.
RS flip-flop 12a consisting of G ₁₀ and G ₁₁ ;
It is equipped with an up-down counter 12b. The up-down counter 12b includes two D flip-flops. The reset input R of each D flip-flop has a power-on reset signal.
RESET is supplied, and the clock input CLK is supplied with an upclock signal UPCLK. Also, the outputs Q ₁₀ and Q ₂₀ of each D flip-flop are as follows:
The signal is input to the AND gate _G12 , and the output of the AND gate _G12 becomes the output signal OUT of the count circuit 12.
In addition, the data input D ₁₀ of each D flip-flop,
D ₂₀ is generated by the logic circuits G ₁₃ and G ₁₄ based on the up-down selection signal UDS and the outputs Q ₁₀ and Q ₂₀ of each D flip-flop, respectively, and the smoke scattered light detection signal COMP has been generated three times in a row in the past. When the output signal OUT reaches the "High" level, the output signal OUT becomes the "High" level, and the switching circuit 2 is triggered.

By the way, in the drive circuit 7 shown in FIG. 2 above, the Zener voltage of the Zener diode ZD ₃ is
Assuming V _ZD3 , the drive current of the light emitting element 6 is I ₆ ={V _ZD3 −(n−1)×V _F −V _BE7 }/R ₇ =(V _ZD3 −n×V _F )/R ₇ . However, it is assumed that the base-emitter voltage _VBE7 of the transistor _Tr7 is equal to the forward drop voltage _VF of each of the (n-1) diodes.
As is clear from the above, in the drive circuit 7 shown in FIG. 2, the temperature characteristic of the base-emitter voltage V _BE7 of the transistor Tr ₇ is
This will affect the temperature characteristics of the drive current _I6 .

FIG. 5 shows another example of the drive circuit 7. In FIG. Compared to _{the drive} circuit ₇ shown _{in FIG} . The difference is that the temperature characteristics of the drive current _I6 of the light emitting element 6 are determined only by the Zener diode _ZD3 and (n-1) diodes by canceling the voltage _VBE17 .

First, when the light emission control signal LEDON is at the "High" level, as described above, the NMOS transistor Tr ₈ is in the on state, the NMOS transistors Tr ₉ ,
Since Tr ₁₀ is in the off state and PMOS transistor Tr ₁₁ is in the on state, the PMOS transistor Tr ₁₂ and
The gate potential of NMOS transistor Tr ₁₃ rises,
The PMOS transistor Tr ₁₂ is turned off, and the NMOS transistor Tr ₁₃ is turned on. For this reason,
A constant current determined by a resistor _R16 flows through the PNP transistor _Tr14 , and the same current flows through the PNP transistor _Tr15 to the base of the transistor _Tr6 . At this time, since the gate potential of the NMOS transistor Tr ₁₆ is low, the NMOS transistor Tr ₁₆ is in an off state and the NPN transistor Tr ₁₇ is in an operable state. This NPN transistor Tr ₁₇ is
When the voltage across resistor R ₆ increases, the base current of NPN transistor Tr ₆ is shunted, the voltage across resistor R ₆ decreases, and negative feedback is generated so that it becomes equal to the base-emitter voltage V _BE17 of transistor Tr ₁₇ . It's under control. Therefore, in this drive circuit 7, the drive current I ₆ of the light emitting element 6 is I ₆ ={V _ZD3 −(n−1)×V _F }/R ₇ . This is the base-emitter voltage V _BE7 of transistor Tr ₇ and the base-emitter voltage V BE7 of transistor Tr ₁₇ .
This is because the emitter voltage V _BE17 cancels each other out.

Next, when the light emission control signal LEDON is at the “Low” level, as described above, the NMOS transistor Tr ₈ is in the off state, and the NMOS transistors Tr ₉ and
Since Tr ₁₀ is on and PMOS transistor Tr ₁₁ is off, PMOS transistor Tr ₁₂ and
The gate potential of NMOS transistor Tr ₁₃ drops,
The PMOS transistor Tr ₁₂ is turned on, and the NMOS transistor Tr ₁₃ is turned off. For this reason,
No current flows through PNP transistor Tr ₁₄ ,
Current no longer flows through PNP transistor _Tr15 as well.
Since the NMOS transistors Tr ₁₆ and Tr ₁₀ are turned on, the base potentials of the NPN transistors Tr ₆ and Tr ₇ are lowered, and the NPN transistors Tr ₆ and Tr ₇ are completely turned off. Therefore, the control signal PHI1
When is at the “Low” level, no current flows from the power supply line V _CC to the power supply line V _SS1 at all.

Here, the (n-1) diodes used in the drive circuit 7 are the temperature coefficient of the Zener voltage V _ZD3 of the Zener diode _ZD3 , the temperature coefficient of the luminous efficiency of the light emitting element 6, the light receiving efficiency of the light receiving element 8, and the current - Considering the temperature coefficient of the high resistance _R8 for voltage conversion, the number of resistors is selected so that the temperature coefficient on the light emitting side and the light receiving side as a whole becomes almost zero. The specific method will be described later.

Next, a specific circuit configuration of the operational amplifiers _OP1 to _OP6 is illustrated in FIG. This operational amplifier is
It includes MOS transistors Tr ₁₈ to Tr ₃₀ , a resistor R ₁₇ , and an inverter G ₁₅ , and when the control signal PHI1 is at "High" level, the output terminal outputs a voltage signal obtained by amplifying the difference between the voltages applied to the input terminals IN1 and IN2. Occurs at OUT1, control signal PHI1 is “Low”
level, the output terminal OUT1 becomes “Low” level and the power line V _DD and
It is characterized by operating so that no current flows during V _SS2 . The operation will be briefly explained below. First, the control signal PHI1 is “High”.
level, PMOS transistor Tr ₁₈ and
Since the gate potential of the NMOS transistor Tr ₂₀ rises, the PMOS transistor Tr ₁₈ is turned off and the NMOS transistor Tr ₂₀ is turned on. Therefore, PMOS transistor Tr ₁₉ ,
Tr ₂₁ , Tr ₂₆ , and Tr ₂₈ have their gate potentials reduced and act as resistance elements. Therefore, input terminal IN1,
The voltage corresponding to the difference in voltage applied to IN2 is
It is generated by a differential amplifier consisting of MOS transistors Tr ₂₂ to _{Tr 25} , and this voltage is amplified in two stages by MOS transistors Tr ₂₇ and Tr ₂₉ and sent to the output terminal OUT.
1 is output. At this time, the MOS transistor
Tr ₂₆ and Tr ₂₈ act as load resistances for the MOS transistors Tr ₂₇ and Tr ₂₉ . Next, when the control signal PHI1 becomes “Low” level, the PMOS transistor
Since the gate potentials of Tr ₁₈ and NMOS transistor Tr ₂₀ decrease, PMOS transistor Tr ₁₈ is turned on and NMOS transistor Tr ₂₀ is turned off. Therefore, PMOS transistor Tr ₁₉ ,
The gate potentials of Tr ₂₁ , Tr ₂₆ , and Tr ₂₈ rise, and they enter a cutoff state. Therefore, no current flows from the power supply line V _DD to the power supply line V _SS2 at all. Also,
Inverter G ₁₅ is powered by power supply lines V _DD and V _SS2 , but all inverters in this example
Since it consists of a CMOS inverter, no current flows after the state transitions. Therefore, the control signal PHI1
When is at “Low” level, the operational amplifier OP ₁ ~
OP ₆ will no longer consume any current.

Next, a specific circuit configuration of the reference voltage circuit 15 is shown in FIG. This circuit generates a reference voltage V _r at the output terminal OUT2 when the control signal PHI1 is at the “High” level, and when the control signal PHI1 is at the “Low” level.
It is characterized in that it operates so that the current from the power supply line V _DD to the power supply line V _SS2 is cut off when the power supply line is at a high level. Hereinafter, assuming that the inverted signal of the control signal PHI1 is 1, the principle by which the reference voltage V _r is generated as a constant voltage when 1 is at the "High" level will be explained.

_Let the base-emitter voltages of transistors Tr ₃₆ and Tr ₃₉ be V _BE36 and V _BE39 , and
If the current flowing through Tr ₃₆ is I, then V _BE36 = V _BE39 + I・R... The ratio of the emitter area of transistor Tr ₃₆ to the emitter area of transistor Tr ₃₉ is 1:S.
, the respective collector currents I _C36 and I _C39 are as follows.

I _C36 = I _s

Claims (1)

[Claims] 1. A light-emitting element that emits light with a brightness that corresponds to the drive current, a drive circuit that supplies the drive current to the light-emitting element, a light-receiving element that receives part of the light emitted from the light-emitting element, and a light-receiving output of the light-receiving element. The temperature coefficient of the luminous efficiency of the light emitting element, the temperature coefficient of the driving current of the drive circuit, the temperature coefficient of the light receiving output current with respect to the amount of light received by the light receiving element, and the temperature coefficient of the light receiving output current with respect to the amount of light received by the light receiving element, and the resistance element that converts current into a voltage signal. A photodetection circuit characterized in that the sum of temperature coefficients of resistance values is approximately zero.