JPH05298248A - Data transfer control method - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a data transfer control system of a CPU register, and an object thereof is to prevent contention between writing from a DSP and reading from a CPU. Constitution: When data is written from the digital signal processor 1 to the CPU read / write register 3, the digital signal processor 1 performs write permission access to the digital signal processor control unit 4, and receives the write permission access and receives the competition control unit 6 Generates a CPU access prohibited area using a control signal output from the digital signal processor control unit 4, and then, when reading from the CPU 2, reads the state of the access prohibited area generated by the conflict control unit 6 into the CPU control unit. 5, the read access to the CPU read / write register 3 is suspended when the prohibited area occurs, and the read access is restarted when the prohibited area ends. When the prohibited area does not occur, the normal operation is performed to read from the CPU 2. It is characterized by performing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control system between a digital signal processor (hereinafter referred to as a DSP) and a CPU, more specifically, a DSP and a CP.
The present invention relates to a data transfer control method between a DSP and a CPU, which uses a write procedure to a read / write register of a CPU when data is transferred between U.

The present invention is suitable for a voice CODEC for performing a voice decoding process in ATM transmission. In ATM transmission, DSP is generally used to process various transmission information contained in cell data, and the processing result, for example, transmission fluctuation and error rate are stored in a register of CPU, and the device side registers The method to read the contents of is adopted. However, DSP and CPU
Since the operation speed between the two is different and they operate asynchronously, D
When data is transferred between the SP and the CPU, the access may conflict with each other. When access conflicts, the data changes as a result, so the DSP and CPU
There has been a demand for the realization of a control method that prevents the contention of the access.

[0003]

2. Description of the Related Art FIG. 6 shows a conventional system configuration for transferring data between a DSP and a CPU. First, DSP to CPU
The data writing procedure from the DSP 1 to the read / write register section 3 of the CPU will be described by using the control signal output from the DSP 1 by the DSP control section 4.
Writing to the write register unit 3 is possible.

Next, the procedure of reading data from the CPU 2 to the read / write register section 3 of the CPU will be described. The CPU 2 reads / write register section 3 of the CPU.
When the data stored in the CPU is read, the control signal output from the CPU control unit 5 is used to enable reading from the read / write register unit 3 of the CPU.

As described above, the DSP controller 4 and the CP
Since the U control unit 5 independently controls the read / write register unit 3 of the CPU, writing from the DSP 1 and reading from the CPU 2 may conflict with each other, in which case the read data changes. Was. Therefore, in the conventional data transfer control method, the CPU 2 makes continuous accesses several times to compare read data,
By changing only the same data to normal data, changes in data due to competition were prevented. See the flowchart shown in FIG.

[0006]

However, in the conventional data transfer control method, as described above, in order to prevent the change of data due to the conflict between the data writing from the DSP and the data reading from the CPU, the data is read on the reading side. Since continuous access must be performed several times and data comparison work must also be performed, there is a problem that the processing procedure of the CPU becomes complicated and the processing speed also decreases. The present invention has been made in consideration of the above circumstances,
A data transfer control method capable of preventing a change in read data even when a write access from a DSP occurs during a read access from a CPU to a read / write register of the CPU.

[0007]

FIG. 1 is a block diagram showing the principle configuration of the present invention. In the figure, according to the present invention, when data is written from the digital signal processor 1 to the CPU read / write register 3, the digital signal processor 1 performs write permission access to the digital signal processor control unit 4 and receives the write permission access. The contention control unit 6 uses the control signal output from the digital signal processor control unit 4 to generate the CPU access prohibited area, and when reading from the CPU 2 next time, the state of the access prohibited area generated by the contention control unit 6 Is checked by the CPU control unit 5, and when the prohibited area occurs, the read access to the CPU read / write register 3 is suspended, and when the prohibited area ends, the read access is restarted,
The data transfer control method is characterized in that when no prohibited area is generated, the CPU 2 reads out data by a normal operation.

[0008]

According to the present invention, the C generated by the competition control unit 6
By controlling reading from the CPU 2 using the PU access prohibited area, writing from the DSP 1 and C
Contention of reading from the PU 2 is prevented, and the CPU 2 reading side can eliminate complicated processing including several continuous access operations and data comparison operations.

[0009]

The present invention will be described in detail below based on the embodiments shown in the drawings. The present invention is not limited to this. FIG. 2 is a block diagram of an apparatus for carrying out the data transfer control system of the present invention.
This is a configuration including SP87064. In such a configuration, the DSP 1 to the CPU read / write register 3
The procedure for writing data to the memory will be described below.

First, the DSP 1 makes write permission access to the DSP control section 4. The DSP control unit 4 detects the write permission access and transfers the write permission signal A to the access prohibited area generation unit 6.

Next, the access prohibition area generator 6 generates a prohibition area signal B using the write permission signal A, and further transfers the generated prohibition area signal B to the competition controller 7. Next, the DSP 1 performs write access to the DSP control unit 4 and writes data in the data holding unit 8. Further, the DSP control unit 4 simultaneously detects the completion of the write access, releases the write permission signal A, and transfers it to the access prohibited area generation unit 6. The access prohibited area generator 6 releases the prohibited area signal B and transfers it to the conflict controller 7.

Next, the procedure for reading data from the CPU 2 to the read / write register 3 of the CPU will be described. CP
U2 makes a read access to the CPU control unit 5, and the CPU control unit 5 detects the read access,
The read signal C is transferred to the competition control unit 7. The competition controller 7 controls the competition by using the prohibited area signal B and the read signal C described above. That is, while the prohibited area signal B and the read signal C overlap, the transfer of the data transfer end signal XACT to the CPU 2 is held, and when the overlap is released, the data transfer end signal XACT is transferred to the CPU 2, and the CPU 2 reads the data. Access is complete.

The CPU 2 sends a data transfer end signal XACT.
Confirm the data by receiving the “Low” pulse of. In addition,
When it is a "High" pulse, it stands by until it receives a "Low" pulse.

3 to 5 are time charts showing the above operation. FIG. 3 shows the case where there is no overlap between the CPU 2 and the DSP 1, the symbol “A” in the DSP write in the figure indicates the signal A output from the DSP control section in FIG. 2, and the symbol “B” in the figure. The signal B output from the access-prohibited area generation unit 6 in FIG. 2 is shown. 4 and 5 show a case where the accesses from the CPU 2 and the DSP 1 overlap.

[0015]

As described above, according to the present invention, C
Even if a write access from the DSP occurs during a read access to the read / write register of the CPU from the PU, until the write access from the DSP ends.
By keeping the read access of the CPU, it is possible to prevent the read data from changing.
Further, the operations of continuous read access and data comparison can be deleted, respectively, and the processing procedure of the CPU can be simplified.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment.

FIG. 4 is a time chart showing the operation of the embodiment.

FIG. 5 is a time chart showing the operation of the embodiment.

FIG. 6 is a conventional system configuration diagram.

FIG. 7 is a flowchart showing a conventional CPU read access.

[Explanation of symbols]

 1 DSP 2 CPU 3 CPU read / write register 4 DSP control unit 5 CPU control unit 6 Competition control unit

Claims (1)

[Claims] 1. Digital signal processor (1) to C
When writing data to the PU read / write register (3), the digital signal processor (1) performs write permission access to the digital signal processor control unit (4), and upon receiving the write permission access, the contention control unit (6)
Generates a CPU access prohibited area by using the control signal output from the digital signal processor control unit (4), and then, when reading from the CPU (2), the conflict control unit
The state of the access prohibited area generated in (6) is checked by the CPU control unit (5), when the prohibited area occurs, the read access to the CPU read / write register (3) is suspended, and when the prohibited area ends, the read access is suspended. And a read operation from the CPU (2) is performed by normal operation when the prohibited area is not generated.