JPH05297834A - Data input circuit of lcd driver - Google Patents

Abstract

PURPOSE:To eliminate the need for designing the delay time of an internal clock as an absolute value and to facilitate the designing by inputting an external data signal in synchronism with the rising of an external clock. CONSTITUTION:When the external clock raises, the external data signal is inputted to a flip-flop FF0 and data are supplied to shift registers SR1-SRN in synchronism with half-clock delay behind the external clock. The shift registers SR1-SRN fetches the data signal that the FF0 output the moment the cascade input trigger signal from the flip-flops FF1-FFN goes up to 'high'. Consequently, the internal data are synchronized with the clock. Therefore, only the delay time of an internal clock buffer circuit CB-N needs to be considered and the delay time need not be designed as an absolute value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD driver, and more particularly to a data input circuit.

[0002]

2. Description of the Related Art As shown in FIG. 3, a data input circuit of a conventional LCD driver is a flip-flop circuit FF _{1 to} FFN (hereinafter abbreviated as FF or FF ₁ , FF ₂ ... FFN) driven by an internal clock signal. Shift register SR ₁ SR ₂ for storing and transferring data from the FF
... SRN and an internal clock buffer (positive) CB-P that changes the external clock signal into the internal clock signal, and an input delay circuit DR-I that delays the external data signal into the internal data signal.

When the cascade input signal is "high", it becomes a trigger signal for fetching external data, and the trigger signal is sequentially transferred in the order of FF ₁ → FF ₂ → ... And delayed by the output display circuit DR-O. It is output to the outside. This output signal is a cascade output to the next stage. When the number of data output terminals 1, 2, ... Is insufficient, it is used by cascade connection in multiple stages. It becomes the data acquisition trigger signal of the circuit. External data is input delay circuit DR-I
After being delayed by the shift register the rise of the signal from FF ₁ to ff _N as a trigger SR ₁ to SR _N
Is taken into. At this time, the external data must be designed so that the rising edge of the external clock signal is used as a trigger, so the internal clock buffer CB
The delay times of the -P delay circuits DR-I must be the same.

The specific operation will be described below with reference to FIG.

Since the cascade input signal is "high" at the rising time point 1 of the external clock signal, the output of FF ₁ becomes "high", and the shift register receives the external data "high" at the time point 1 and the data output terminal. "High" to 1
Is output. Next FF ₂ outputs the cascade input signal is transferred to FF ₂ at the rising time point 2 of the external clock signal is captured "high" external data signal next shift register SR ₂ at time 2 "low", the data output terminal “Low” is output to 2. Thereafter, the cascade input signal is similarly transferred from FF _{3 to} FF ₄ , "high" is taken into the shift register SR ₃ at the rising time point 3 of the external clock signal, and "high" is output to the data output terminal 3. To be done.

[0006]

The conventional data input circuit described above, however, has a drawback in that it is difficult to design because the delay time of the internal clock buffer and the delay time of the input delay circuit must be the same.

[0007]

A data input circuit of the present invention is a flip-flop (FF) which is driven by an external clock signal to take in external data, and a logical inversion of the external clock signal to obtain an internal block signal. And an internal clock buffer circuit.

[0008]

According to the above configuration, the external data signal is taken in at the rising edge of the external clock signal.
Internal data is synchronized with the clock. Therefore, it suffices to consider only the delay time of the internal clock buffer circuit, and the delay time does not have to be designed as an absolute value, and the delay time may be designed to be as small as possible, which facilitates the design.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. FF _{0 to} FF ₄ are flip-flops, and CB-N is an internal clock buffer which is a logic inversion buffer.

Next, the above block diagram will be described.

When the cascade input signal is "high", it becomes a trigger signal for fetching external data, and the trigger signal is sequentially transferred as FF ₁ → FF ₂ → FF ₃ ... FF _N , and the output display circuit DR-O Is delayed and output to the outside. The output signal is a cascade output to the next stage and serves as a data capture trigger signal for the next circuit. The external data signal is taken in by the flip-flop FF ₀ at the rising edge of the external clock signal and is synchronized with the external clock by a half clock delay and the shift register SR ₁
And supplies the data to ~SR _N. Shift register SR
And supplies the data to the ₁ to SR _N. Shift register S
R ₁ to SR _N at the time the cascade input trigger signal from the FF ₁ to ff _N becomes "high", takes in the data signal output from the FF _0.

The specific operation will be described below with reference to FIG.

Since the cascade input signal is "high" at the rising time E of the internal clock signal, the output of FF ₁ becomes "high", and the internal data signal [high] taken into the shift register SR ₁ at the rising time A of the external clock. Is taken in and “high” is output to the data output terminal 1.

Next, the cascade signal is transferred to FF _2, the internal clock signal rises at time F the output of the FF ₂ is "high", and the internal captured into the shift register SR ₂ at the rising time point B of the external clock signal data The “low” is taken into the shift register SR ₂ , and the “low” is output to the data output terminal 2.

Similarly, the cascade signal is FF ₃ → F
It is transferred as F ₄ and when external clock rises C
The internal data “high” captured by the shift register SR
_It is taken into 3 and "high" is output to the data output terminal 3.

[0017]

As described above, according to the present invention, since the external data signal is synchronized and taken in at the rising edge of the external clock, it is not necessary to design the delay time of the internal clock as an absolute value, and the design is easy. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram of a data circuit of the present invention.

FIG. 2 is a timing chart of the data input circuit according to the present invention.

FIG. 3 is a block diagram of a conventional data input circuit.

FIG. 4 is a timing chart of a conventional data input circuit.

[Explanation of symbols]

FF ₀ to ff _N flip-flop CB-P internal clock logic forward rotation of the internal clock buffer CB-W logic inverting buffer SR ₁ to SR _N shift register

Claims (2)

[Claims] 1. An LCD driver, comprising: a flip-flop driven by an external clock signal to take in external data internally; and an internal clock buffer circuit that logically inverts the external clock signal to produce an internal clock signal. Data input circuit. 2. A flip-flop that is driven by the internal clock signal and transfers a trigger signal, and a shift register that outputs the data taken in by the transferred trigger signal. The data input circuit of the LCD driver described in 1.