JPH0529529A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH0529529A JPH0529529A JP3184493A JP18449391A JPH0529529A JP H0529529 A JPH0529529 A JP H0529529A JP 3184493 A JP3184493 A JP 3184493A JP 18449391 A JP18449391 A JP 18449391A JP H0529529 A JPH0529529 A JP H0529529A
- Authority
- JP
- Japan
- Prior art keywords
- island
- resin
- package
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 239000011347 resin Substances 0.000 claims abstract description 26
- 229920005989 resin Polymers 0.000 claims abstract description 26
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 238000005476 soldering Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は樹脂封止型半導体装置に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】近年、樹脂封止型半導体装置が実装され
る、電子機器の小型軽量化に伴い半導体パッケージもよ
り小型・薄型のものが要望されている。以下に小型・薄
型の樹脂封止型半導体装置の従来例については図３〜図
７を参照しながら説明する。この図において、１はリー
ドフレームのアイランド部でこの上に半導体チップ２が
ダイボンドされる。このダイボンドされた半導体チップ
２の上面の電極は、リードフレームの外部導出リード３
に金属線４により配線される。そしてこの配線部及び前
記半導体チップ部はモールド樹脂５により封止される。
以上のように構成された樹脂封止型半導体装置をプリン
ト基板に搭載する際の様子を図４，図５に示す。プリン
ト基板６に半田ペースト７あるいは接着剤８を塗布して
おき、これに樹脂封止型半導体装置を位置決めして載
せ、半田ペーストを用いた場合にはその後、熱風あるい
は赤外線等により加熱し半田付けする。一方接着剤を使
用した場合は、半田浴に浸漬して半田付けする。2. Description of the Related Art In recent years, with the reduction in size and weight of electronic equipment in which a resin-sealed semiconductor device is mounted, there has been a demand for smaller and thinner semiconductor packages. A conventional example of a compact and thin resin-encapsulated semiconductor device will be described below with reference to FIGS. In this figure, reference numeral 1 denotes an island portion of a lead frame on which a semiconductor chip 2 is die-bonded. The electrodes on the upper surface of the die-bonded semiconductor chip 2 are connected to the external leads 3 of the lead frame.
Is wired by a metal wire 4. The wiring portion and the semiconductor chip portion are sealed with the mold resin 5.
4 and 5 show how the resin-sealed semiconductor device configured as described above is mounted on a printed circuit board. A solder paste 7 or an adhesive 8 is applied to the printed circuit board 6, a resin-sealed semiconductor device is positioned and placed on the printed substrate 6, and when the solder paste is used, it is thereafter heated by hot air or infrared rays to be soldered. To do. On the other hand, when an adhesive is used, it is dipped in a solder bath for soldering.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
樹脂封止型半導体装置においては、プリント基板への半
田付けの際、モールド樹脂（パッケージ）全体を加熱し
てしまうので、次のような欠点を有する。即ちパッケー
ジ全体が高温（２００℃〜２５０℃）となり、材料の熱
膨張係数の差により樹脂とリードフレーム間、樹脂とチ
ップ表面間の密着性劣化が発生し、図６に示すように半
田付け以前に吸湿した内部の水分９が加熱により急激に
気化膨張するため、パッケージ内部より外部へ大きな力
が発生し、その力によりモールド樹脂にクラックを生
じ、図７に示すようにパッケージを破壊してしまう。こ
の状態で樹脂封止型半導体の使用を続けると、半導体チ
ップ表面に容易に空気中の水分が達するため、チップ表
面のアルミニウム配線の腐食・断線を発生し、半導体装
置としての機能を果たさなくなる。However, in the conventional resin-encapsulated semiconductor device, since the entire mold resin (package) is heated during soldering to the printed circuit board, the following drawbacks are encountered. Have. That is, the temperature of the entire package becomes high (200 ° C to 250 ° C), and the adhesion between the resin and the lead frame and between the resin and the chip surface deteriorates due to the difference in the coefficient of thermal expansion of the materials. Since the moisture 9 inside which has been absorbed by the inside of the package abruptly vaporizes and expands due to heating, a large force is generated from the inside of the package to the outside, and the force causes a crack in the mold resin, which destroys the package as shown in FIG. . If the resin-encapsulated semiconductor is continuously used in this state, moisture in the air easily reaches the surface of the semiconductor chip, so that the aluminum wiring on the surface of the chip is corroded and disconnected, and the semiconductor device does not function as a semiconductor device.
【０００４】本発明は上記従来の課題を解決するもの
で、半田付けにおいてもパッケージ破損を発生させない
樹脂封止型半導体装置を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a resin-encapsulated semiconductor device which does not cause package damage even during soldering.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
に本発明の樹脂封止型半導体装置はリードフレームのア
イランドが平坦なアイランド部とそのアイランド部の全
外周部に半導体チップをとり囲むような側壁部を有する
深皿形状をなし、その側壁部，半導体チップおよび配線
部にはモールド樹脂が封止されているが、アイランドの
裏面側にはモールド樹脂が形成されていない構成によ
る。In order to achieve the above object, in a resin-sealed semiconductor device of the present invention, a semiconductor chip is surrounded by an island portion of a lead frame having a flat island and the entire outer peripheral portion of the island portion. It has a deep dish shape having various side wall portions, and the side wall portion, the semiconductor chip and the wiring portion are sealed with the mold resin, but the mold resin is not formed on the back surface side of the island.
【０００６】[0006]
【作用】本発明は上記した構成により、アイランド裏面
側には樹脂層が無く、またアイランドの上面および半導
体チップ表面と、モールド樹脂部との界面にて加熱時急
膨張する水分はダイアイランド外周の側壁部とモールド
樹脂の隙間より外部へ逃げ、パッケージの破損を防止す
ることができるものである。According to the present invention, due to the above-mentioned structure, there is no resin layer on the back surface of the island, and the moisture that rapidly expands at the interface between the upper surface of the island and the surface of the semiconductor chip and the mold resin portion is the outer surface of the die island. It is possible to prevent the package from being damaged by allowing the package to escape to the outside through the gap between the side wall and the molding resin.
【０００７】[0007]
【実施例】以下本発明の一実施例について図１及び図２
を参照しながら説明する。図１は本発明の一実施例の樹
脂封止型半導体装置の断面図、図２は図１のリードフレ
ームのアイランド部の斜視図である。これらの図におい
て１０はリードフレームのアイランド、１１はそのアイ
ランドの側壁である。すなわちリードフレームのアイラ
ンド１０が平坦なアイランド部とそのアイランド部の全
外周部に半導体チップをとり囲むような側壁部１１を有
する深皿形状をなし、その側壁部１１，半導体チップ１
２および配線部にはモールド樹脂１５が封止されている
が、上記アイランド１０の裏面側にはモールド樹脂１５
が形成されていない構成である。アイランド１０上面に
は半導体チップ１２がダイスボンドされる。このダイス
ボンドされた半導体チップ１２の表面の電極はリードフ
レームの外部導出リード１３に金属線１４により配線さ
れる。そして、この半導体チップ部及び上記配線部の全
体が急速に加熱されると、半導体チップ１２を搭載した
アイランド１０と、モールド樹脂との界面においては各
々の材料の熱膨張係数の違い及び高温における樹脂の強
度の低下により、密着性が低下し気化膨張した水分は、
アイランド１０の側壁部１１とモールド樹脂１５の隙間
より外部へ逃げる。また半田付け前後の保管状態・使用
状態においては、半導体チップ１２の上面を除く全周囲
をアイランド１０の側壁部１１で包囲する構成のため、
従来技術の構成と比較して、半導体チップ１２部の吸湿
は少ない。パッケージ表面の露出したアイランド１０と
モールド樹脂１５との境界からの水分の進入について
は、側壁部１１がその進入経路となるため、進入経路が
長く、かつ屈曲しており水分が半導体チップ１２表面ま
で達するおそれは少ない。またアイランド１０の裏面に
モールド樹脂１５が無いため、その樹脂層の厚みの分、
従来技術の構成と比較しパッケージの厚みを薄くするこ
とができる。またアイランド１０の裏面が外部に露出し
ているため、放熱性も従来技術の構成に比べ良好とな
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
Will be described with reference to. 1 is a sectional view of a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 2 is a perspective view of an island portion of the lead frame shown in FIG. In these figures, 10 is an island of the lead frame, and 11 is a side wall of the island. That is, the island 10 of the lead frame has a flat plate shape having a flat island portion and a side wall portion 11 surrounding the semiconductor chip on the entire outer peripheral portion of the island portion.
The mold resin 15 is sealed on the wiring 2 and the wiring portion, but the mold resin 15 is formed on the back surface side of the island 10.
Is not formed. The semiconductor chip 12 is die-bonded to the upper surface of the island 10. The electrodes on the surface of the die-bonded semiconductor chip 12 are wired by the metal wires 14 to the external leads 13 of the lead frame. Then, when the entire semiconductor chip portion and the wiring portion are rapidly heated, at the interface between the island 10 on which the semiconductor chip 12 is mounted and the mold resin, the difference in the coefficient of thermal expansion of each material and the resin at high temperature. Due to the decrease in the strength of the
It escapes from the gap between the side wall 11 of the island 10 and the mold resin 15 to the outside. Further, in the storage state and the use state before and after soldering, since the entire periphery of the semiconductor chip 12 except the upper surface is surrounded by the side wall portion 11 of the island 10,
As compared with the configuration of the conventional technique, the semiconductor chip 12 portion absorbs less moisture. Regarding the entry of moisture from the boundary between the island 10 and the molding resin 15 which are exposed on the package surface, the sidewall 11 serves as the entry route, so that the entry route is long and bent, and the moisture reaches the surface of the semiconductor chip 12. Less likely to reach. Since the back surface of the island 10 does not have the mold resin 15, the thickness of the resin layer
The thickness of the package can be reduced as compared with the configuration of the related art. Further, since the back surface of the island 10 is exposed to the outside, the heat dissipation property is also better than that of the conventional structure.
【０００８】[0008]
【発明の効果】以上の実施例から明らかなように本発明
によれば、リードフレームのアイランドが平坦なアイラ
ンド部とそのアイランド部の全外周部に半導体チップを
とり囲むような側壁部を有する深皿形状をなし、その側
壁部，半導体チップおよび配線部にはモールド樹脂が封
止されているが、アイランドの裏面側にはモールド樹脂
が形成されていない構成によるので、プリント基板への
半田付け時のパッケージ破損の発生を防止でき、より薄
型で、より放熱性の良い樹脂封止型半導体装置を提供で
きる。As is apparent from the above embodiments, according to the present invention, the lead frame island has a flat island portion and a deep side wall portion surrounding the semiconductor chip on the entire outer peripheral portion of the island portion. Although it has a dish shape and the side wall, semiconductor chip and wiring are sealed with mold resin, the back surface of the island is not covered with mold resin. It is possible to provide a resin-sealed semiconductor device which can prevent the package from being damaged and is thinner and has better heat dissipation.
【図１】本発明の一実施例の樹脂封止型半導体装置の要
部断面図FIG. 1 is a sectional view of an essential part of a resin-sealed semiconductor device according to an embodiment of the present invention.
【図２】図１の樹脂封止型半導体装置のリードフレーム
アイランド部の斜視図FIG. 2 is a perspective view of a lead frame island portion of the resin-sealed semiconductor device of FIG.
【図３】従来の樹脂封止型半導体装置の要部断面図FIG. 3 is a sectional view of a main part of a conventional resin-encapsulated semiconductor device.
【図４】図３の樹脂封止型半導体装置の実装方法を示す
断面図FIG. 4 is a sectional view showing a mounting method of the resin-sealed semiconductor device of FIG.
【図５】図３の樹脂封止型半導体装置の他の実装方法を
示す断面図5 is a sectional view showing another mounting method of the resin-sealed semiconductor device of FIG.
【図６】従来の樹脂封止型半導体装置の実装時における
パッケージ破損の原因を説明するための図FIG. 6 is a diagram for explaining a cause of package damage at the time of mounting a conventional resin-sealed semiconductor device.
【図７】図６の破損原因により樹脂封止型半導体装置が
破損した状態を示す断面図7 is a cross-sectional view showing a state in which the resin-encapsulated semiconductor device is damaged due to the cause of damage in FIG.
１０ アイランド １１ アイランドの側壁部 １２ 半導体チップ １３ 外部導出リード １４ 金属線 １５ モールド樹脂 10 Island 11 Sidewall of Island 12 Semiconductor Chip 13 Externally Derived Lead 14 Metal Wire 15 Mold Resin
Claims (1)
ップを搭載し、その半導体チップ上面の電極をリードフ
レームの外部導出リードに配線し、その配線部及び前記
半導体チップをモールド樹脂で封止してなる樹脂封止型
半導体装置において、前記リードフレームのアイランド
が平坦なアイランド部とそのアイランド部の全外周縁部
に前記半導体チップをとり囲むような側壁部を有する深
皿形状をなし、その側壁部，前記半導体チップおよび配
線部にはモールド樹脂が封止されているが、前記アイラ
ンドの裏面側には前記モールド樹脂が形成されていない
ことを特徴とする樹脂封止型半導体装置。Claim: What is claimed is: 1. A semiconductor chip is mounted on an island of a lead frame, electrodes on the upper surface of the semiconductor chip are wired to external leads of the lead frame, and the wiring part and the semiconductor chip are made of a molding resin. In a resin-sealed semiconductor device formed by encapsulation, the island of the lead frame has a flat plate shape, and a deep plate shape having a side wall part surrounding the semiconductor chip at the entire outer peripheral edge part of the island part. A resin-encapsulated semiconductor device, wherein a mold resin is sealed on the side wall portion, the semiconductor chip, and the wiring portion, but the mold resin is not formed on the back surface side of the island.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3184493A JPH0529529A (en) | 1991-07-24 | 1991-07-24 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3184493A JPH0529529A (en) | 1991-07-24 | 1991-07-24 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0529529A true JPH0529529A (en) | 1993-02-05 |
Family
ID=16154146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3184493A Pending JPH0529529A (en) | 1991-07-24 | 1991-07-24 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0529529A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0964243A (en) * | 1995-08-30 | 1997-03-07 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH09199639A (en) * | 1996-01-16 | 1997-07-31 | Matsushita Electron Corp | Semiconductor device and its formation |
| EP0712160A3 (en) * | 1994-11-14 | 1998-04-01 | Texas Instruments Incorporated | Improvements in or relating to semiconductor devices |
| JPH11103003A (en) * | 1997-07-31 | 1999-04-13 | Matsushita Electron Corp | Semiconductor device and lead frame |
| JP2000036558A (en) * | 1998-07-17 | 2000-02-02 | Shinko Electric Ind Co Ltd | Lead frame and manufacture thereof |
| US6208023B1 (en) | 1997-07-31 | 2001-03-27 | Matsushita Electronics Corporation | Lead frame for use with an RF powered semiconductor |
| US7821116B2 (en) | 2007-02-05 | 2010-10-26 | Fairchild Semiconductor Corporation | Semiconductor die package including leadframe with die attach pad with folded edge |
| JP2014232811A (en) * | 2013-05-29 | 2014-12-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method for manufacturing the same |
| JP2018056309A (en) * | 2016-09-28 | 2018-04-05 | エイブリック株式会社 | Semiconductor device |
-
1991
- 1991-07-24 JP JP3184493A patent/JPH0529529A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0712160A3 (en) * | 1994-11-14 | 1998-04-01 | Texas Instruments Incorporated | Improvements in or relating to semiconductor devices |
| JPH0964243A (en) * | 1995-08-30 | 1997-03-07 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH09199639A (en) * | 1996-01-16 | 1997-07-31 | Matsushita Electron Corp | Semiconductor device and its formation |
| JPH11103003A (en) * | 1997-07-31 | 1999-04-13 | Matsushita Electron Corp | Semiconductor device and lead frame |
| US6208023B1 (en) | 1997-07-31 | 2001-03-27 | Matsushita Electronics Corporation | Lead frame for use with an RF powered semiconductor |
| EP0895287A3 (en) * | 1997-07-31 | 2006-04-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and lead frame for the same |
| JP2000036558A (en) * | 1998-07-17 | 2000-02-02 | Shinko Electric Ind Co Ltd | Lead frame and manufacture thereof |
| US7821116B2 (en) | 2007-02-05 | 2010-10-26 | Fairchild Semiconductor Corporation | Semiconductor die package including leadframe with die attach pad with folded edge |
| JP2014232811A (en) * | 2013-05-29 | 2014-12-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method for manufacturing the same |
| JP2018056309A (en) * | 2016-09-28 | 2018-04-05 | エイブリック株式会社 | Semiconductor device |
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