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JPH0529455A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPH0529455A
JPH0529455A JP18148491A JP18148491A JPH0529455A JP H0529455 A JPH0529455 A JP H0529455A JP 18148491 A JP18148491 A JP 18148491A JP 18148491 A JP18148491 A JP 18148491A JP H0529455 A JPH0529455 A JP H0529455A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
sheet
wafer
electrical characteristics
rear surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18148491A
Other languages
Japanese (ja)
Inventor
Hideaki Takano
英明 高野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18148491A priority Critical patent/JPH0529455A/en
Publication of JPH0529455A publication Critical patent/JPH0529455A/en
Pending legal-status Critical Current

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  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To avoid the wafer cracking during the handling steps of thin wafer from the polishing step of semiconductor wafer to the electrical characteristics checking step and the dicing step in consideration of the diminished thickness of semiconductor wafer in the polishing step resultant from the miniaturization of packaged semiconductor wafer. CONSTITUTION:After sticking a surface protective sheet 2 on a semiconductor wafer 1, a rear surface sheet 3 is sticked on the rear surface of the same. Next, the surface protective sheet 2 is released to be handled leaving such a state intact from the electrical characteristics checking step to the dicing step. Through these procedures, the thin semiconductor wafer can be reinforced by the rear surface sheet 3 while eliminating the handling step of the unit wafer itself for avoiding the wafer cracking phenomenon thereby enabling the yield in the manufacturing steps to be increased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に裏面研削工程からダイシング工程までに関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a back grinding process to a dicing process.

【0002】[0002]

【従来の技術】従来の製造方法について、図2(a)〜
(e)を参照して説明する。
2. Description of the Related Art A conventional manufacturing method is shown in FIG.
This will be described with reference to (e).

【0003】はじめに図2(a)に示すように、半導体
ウェーハ1の表面に表面保護シート2を貼って半導体ウ
ェーハ1と同形状に表面保護シート2を裁断する。
First, as shown in FIG. 2A, a surface protection sheet 2 is attached to the surface of a semiconductor wafer 1 and the surface protection sheet 2 is cut into the same shape as the semiconductor wafer 1.

【0004】つぎに図2(b)に示すように、研削機に
より半導体ウェーハ1の裏面を所定の厚さになるまで研
削する。
Next, as shown in FIG. 2B, the back surface of the semiconductor wafer 1 is ground by a grinder to a predetermined thickness.

【0005】つぎに図2(c)に示すように、表面保護
シート2をはがし、半導体ウェーハ1のみとする。この
状態で個々のチップの電気的特性チェックを行ない、良
・不良の判定を行なう。
Next, as shown in FIG. 2C, the surface protection sheet 2 is peeled off to leave only the semiconductor wafer 1. In this state, the electrical characteristics of each chip are checked to determine whether they are good or bad.

【0006】つぎに図2(d)に示すように、半導体ウ
ェーハ1の裏面に裏面シート3を貼り、同時に裏面シー
ト3の外周部をフレーム4に貼り付ける。
Next, as shown in FIG. 2D, the back sheet 3 is attached to the back surface of the semiconductor wafer 1, and at the same time, the outer peripheral portion of the back sheet 3 is attached to the frame 4.

【0007】つぎに図2(e)に示すように、ダイシン
グ装置により、半導体ウェーハ1を個々のチップ5に分
割する。この状態で次工程のダイボンディング工程に送
られる。
Next, as shown in FIG. 2E, the semiconductor wafer 1 is divided into individual chips 5 by a dicing device. In this state, it is sent to the die bonding step of the next step.

【0008】[0008]

【発明が解決しようとする課題】実装パッケージの小型
化にともない、半導体ウェーハの研削仕上げ厚さも35
0μmあるいは300μmと薄くなっている。また、半
導体ウェーハの外径もφ6インチ、φ8インチと大型化
して来た。
With the miniaturization of the mounting package, the ground finish thickness of the semiconductor wafer is also 35.
It is as thin as 0 μm or 300 μm. In addition, the outer diameter of semiconductor wafers has been increased to φ6 inches and φ8 inches.

【0009】従来の方法では、研削後に表面保護シート
をはがし、半導体ウェーハ単体でハンドリングを行なう
ので、ハンドリング時の半導体ウェーハ割れが多く、半
導体集積回路の製造歩留りを低下させるという問題があ
った。
In the conventional method, since the surface protective sheet is removed after grinding and the semiconductor wafer is handled as a single body, the semiconductor wafer is often cracked at the time of handling, and there is a problem that the manufacturing yield of semiconductor integrated circuits is reduced.

【0010】[0010]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、研削後の半導体ウェーハの表面保護シートを
残したまま半導体ウェーハの裏面に裏面シートを貼り付
け、同時に裏面シートの外周部にフレームを貼り付けて
から半導体ウェーハの表面保護シートをはがし、電気特
性チェックおよびダイシング工程のハンドリングを行な
うものである。
According to a method of manufacturing a semiconductor device of the present invention, a backside sheet is attached to a backside of a semiconductor wafer while leaving a surface protection sheet of the semiconductor wafer after grinding, and at the same time, an outer peripheral portion of the backside sheet is attached to the backside sheet. After the frame is attached, the surface protection sheet of the semiconductor wafer is peeled off to check the electrical characteristics and handle the dicing process.

【0011】[0011]

【実施例】本発明の一実施例について、図1(a)〜
(e)を参照して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to (e).

【0012】はじめに図1(a)に示すように、半導体
ウェーハ1の表面に表面保護シート2を貼りつけて、表
面保護シート2を半導体ウェーハ1と同形状に切断した
ものである。
First, as shown in FIG. 1A, a surface protective sheet 2 is attached to the surface of a semiconductor wafer 1 and the surface protective sheet 2 is cut into the same shape as the semiconductor wafer 1.

【0013】つぎに図1(b)に示すように、研削機に
より半導体ウェーハ1の裏面を所定の厚さになるまで研
削する。
Next, as shown in FIG. 1 (b), the back surface of the semiconductor wafer 1 is ground by a grinder to a predetermined thickness.

【0014】つぎに図1(c)に示すように、表面保護
シート2が貼られた半導体ウェーハ1の裏面にダイシン
グ用の裏面シート3を貼り付ける。同時に裏面シート3
の外周部にフレーム4を貼り付ける。
Next, as shown in FIG. 1C, a back sheet 3 for dicing is attached to the back surface of the semiconductor wafer 1 to which the surface protection sheet 2 is attached. Back sheet 3 at the same time
The frame 4 is attached to the outer peripheral portion of.

【0015】つぎに図1(d)に示すように、表面保護
シート2をはがす。この状態で半導体ウェーハ1内の個
々のチップの電気的特性チェックを行なう。
Next, as shown in FIG. 1 (d), the surface protection sheet 2 is peeled off. In this state, the electrical characteristics of individual chips in the semiconductor wafer 1 are checked.

【0016】つぎに図1(e)に示すように、ダイシン
グ装置により、個々のチップ5に切断して、次工程であ
るダイボンディング工程に送られる。
Next, as shown in FIG. 1E, the individual chips 5 are cut by a dicing device and sent to a die bonding step which is the next step.

【0017】[0017]

【発明の効果】表面保護シートを残したまま裏面研削後
の半導体ウェーハの裏面にダイシング用の裏面シートを
貼り付ける。そのあと表面保護シートをはがして電気的
特性を測定する。
EFFECTS OF THE INVENTION A backside sheet for dicing is attached to the backside of a semiconductor wafer after backside grinding with the surface protection sheet left. After that, the surface protection sheet is peeled off and the electrical characteristics are measured.

【0018】半導体ウェーハ単体でのハンドリングがな
くなり、表面保護シートはがすときや電気特性を測定す
る工程でのハンドリングによる半導体ウェーハ割れがな
くなり、製造工程での歩留り向上の効果がある。また、
φ8インチの大口径でも厚さ250μm程度の半導体ウ
ェハーの製造も可能となる。
Handling of the semiconductor wafer alone is eliminated, and cracking of the semiconductor wafer due to handling during peeling of the surface protective sheet or in the process of measuring electrical characteristics is eliminated, which has the effect of improving the yield in the manufacturing process. Also,
Even with a large diameter of φ8 inch, it is possible to manufacture a semiconductor wafer having a thickness of about 250 μm.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を工程順に示す断面図であ
る。
FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.

【図2】従来の裏面研削・測定・ダイシング工程を示す
断面図である。
FIG. 2 is a cross-sectional view showing a conventional back surface grinding / measurement / dicing process.

【符号の説明】[Explanation of symbols]

1 半導体ウェーハ 2 表面保護シート 3 裏面シート 4 フレーム 5 チップ 1 semiconductor wafer 2 surface protection sheet 3 back sheet 4 frame 5 chips

Claims (1)

【特許請求の範囲】 【請求項1】 半導体ウェーハの表面に表面保護シート
を貼って前記半導体ウェーハの裏面を研削する工程と、
前記半導体ウェーハの裏面に裏面シートを貼ると同時に
前記裏面シート外周にフレームを貼る工程と、前記表面
保護シートをはがして前記半導体ウェーハの電気的特性
を測定する工程と、前記半導体ウェーハを個々のチップ
に分割するダイシング工程とを含む半導体装置の製造方
法。
Claim: What is claimed is: 1. A step of adhering a surface protection sheet to the front surface of a semiconductor wafer and grinding the back surface of the semiconductor wafer,
A step of attaching a backside sheet to the backside of the semiconductor wafer and a frame at the same time on the outer periphery of the backside sheet, a step of peeling off the surface protection sheet to measure the electrical characteristics of the semiconductor wafer, and the semiconductor wafer into individual chips. And a dicing step of dividing into
JP18148491A 1991-07-23 1991-07-23 Manufacturing method of semiconductor device Pending JPH0529455A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18148491A JPH0529455A (en) 1991-07-23 1991-07-23 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18148491A JPH0529455A (en) 1991-07-23 1991-07-23 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0529455A true JPH0529455A (en) 1993-02-05

Family

ID=16101569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18148491A Pending JPH0529455A (en) 1991-07-23 1991-07-23 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0529455A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430937A4 (en) * 1987-03-16 1990-10-18 Nat Biomedical Res Foundation Interactive microscopic image display system and method.
WO1997008745A1 (en) * 1995-08-31 1997-03-06 Nitto Denko Corporation Method and apparatus for peeling protective adhesive tape from semiconductor wafer
US6426275B1 (en) 1999-08-03 2002-07-30 Tokyo Seimitsu Co., Ltd. Method for manufacturing semiconductor chips using protecting pricing and separating sheets
WO2003049164A1 (en) * 2001-11-30 2003-06-12 Disco Corporation Production method for semiconductor chip
US6869830B2 (en) * 2001-12-03 2005-03-22 Disco Corporation Method of processing a semiconductor wafer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430937A4 (en) * 1987-03-16 1990-10-18 Nat Biomedical Res Foundation Interactive microscopic image display system and method.
WO1997008745A1 (en) * 1995-08-31 1997-03-06 Nitto Denko Corporation Method and apparatus for peeling protective adhesive tape from semiconductor wafer
US6426275B1 (en) 1999-08-03 2002-07-30 Tokyo Seimitsu Co., Ltd. Method for manufacturing semiconductor chips using protecting pricing and separating sheets
WO2003049164A1 (en) * 2001-11-30 2003-06-12 Disco Corporation Production method for semiconductor chip
US6852608B2 (en) 2001-11-30 2005-02-08 Disco Corporation Production method for semiconductor chip
US6869830B2 (en) * 2001-12-03 2005-03-22 Disco Corporation Method of processing a semiconductor wafer

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