JPH05292343A - Frame pulse detector - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a circuit capable of accurately detecting a frame pulse without increasing the circuit scale. [Structure] A change amount of an input video signal is taken out by a latch circuit 33 and a subtractor 34. The comparator 36 determines whether or not the change amount is equal to or more than a certain amount, and the sign determination circuit 35 determines whether the change direction is positive or negative. According to this direction determination, if there is a certain amount of change in the positive direction (condition 1), a positive signal is taken out from the AND circuit 38, and if there is a certain amount of change in the negative direction (condition 2). , AND circuit 39 and inverting circuit 42 take out a negative signal. These signals are input to the frame pulse detection circuit 46 via the OR circuit 41 and the selector 44. Under the conditions other than the above conditions 1 and 2, the NOR circuit 43 continues to derive the output of the latch circuit 45 to eliminate the change of the input signal of the frame pulse detection circuit 46.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame pulse detector used in a television receiver for receiving satellite broadcasting, and more particularly to a MUSE (MULTIPLE SUB-NYQUI).
ST SAMPLINGENCODING) is an effective device for circuits that process television signals transmitted by the system.

[0002]

2. Description of the Related Art In recent years, in addition to conventional terrestrial broadcasting, cable broadcasting such as CATV broadcasting and satellite broadcasting using satellites has diversified. Also IDTV and EDTV
It is expected that the quality of the image will be improved due to such reasons. Above all, high-definition broadcasting using satellites is the conventional broadcasting signal NTS.
It has more than twice the number of scanning lines as the C signal, and is attracting attention from various fields such as the broadcasting industry and the printing industry as a major change in television broadcasting in the future.

However, this MUSE system is not compatible with the NTSC signals that have been conventionally broadcast, and cannot be received by a commonly used television receiver. Therefore, a new high-definition receiver must be prepared to receive high-definition broadcasting. But the LS to use
Since I is expensive and there are many types, it is thought that it still takes a lot of time to spread to general households.
Therefore, it becomes necessary to further integrate this LSI,
Development for commercialization is underway.

In the MUSE system, one image is sampled at different sampling points and divided into a plurality of image data having narrow frequency bands. In the MUSE system, a signal of one image is sampled and divided into four images for transmission, so that the signals can be accommodated in the transmission band of the satellite. In the MUSE type receiving device, the operation of returning the original image to one original image is performed by superimposing the four divided images. However, this operation can be completely restored only when the original image is a still image, but in the case of a moving image, this operation causes four images to move, so the images overlap and the screen collapses. I will end up.
Therefore, the moving image portion is not subjected to the superimposing processing, and the pixel data between the sampling points is created using the pixels around it. Actually, data for restoring the video such as motion information is included in the MUSE signal, and these processes are performed by digital signal processing.

As described above, in the MUSE system, there is one set of four fields, but in an actual signal, two fields are defined as one frame. Then, a signal called a frame pulse is horizontally 2 every two fields.
It is inserted across the line and this pulse can be detected to obtain system synchronization.

FIG. 3 shows the waveform of the frame pulse. Line No. 1 and NO. 2 has a frame pulse period, which is inserted as a signal whose polarity switches every 4 clocks. In the MUSE receiver, this frame pulse is detected and used as a time reference for signal processing.
If this frame pulse is not detected, video cannot be received, which is an important signal.

To detect frame pulses, MUSE
The signal is digitized and detected using the MSB bit. This utilizes the characteristic of the MUSE signal that the peak of the frame pulse always crosses the center of the maximum and minimum digital values representing the video signal in the normal state, and this state is shown in FIG. Shown in a). However, when trying to detect a frame pulse when the power is turned on or when the video signal is at all low level or high level,
A phenomenon may occur in which the video signal does not cross the center of the digital value and is fixed as it is. This situation is shown in Figure 2.
It shows in (b) and (c) of (A). (B) of FIG. 2 (A)
Shows the case where the level is too low, and FIG. 2 (c) shows the case where the level is too high. Therefore, it is not complete just to use 1 bit of MSB, and some measures are required. Therefore, the levels (LA) and (L
B) is detected and ORed with the MSB bit to take countermeasures.

However, the circuit for realizing this is as shown in FIG. 2B, and the frame pulse detecting device becomes large in scale. The circuit of FIG. 2B will be described.
The MUSE signal is supplied to the input terminal 11, is converted into a digital signal by the analog-digital (A / D) converter 12, and is introduced into the frame pulse detection device 14 via the low-pass filter 13. Frame pulse detector 14
Has a first frame pulse detector 15, a first comparator 16, and a second comparator 17 to which the output of the A / D converter 12 is supplied. The frame pulse detection circuit 15 captures the upper 1 bit and detects the frame pulse pattern. The comparator 16 takes out the upper 1 bit of bits exceeding the level (LA) as a reference and supplies it to the frame pulse detection circuit 18. Frame pulse detection circuit 1
8 detects the pattern of the frame pulse similarly to the above detection circuit 15. The comparator 17 takes out the upper 1 bit exceeding the level (LB) as a reference and supplies it to the frame pulse detection circuit 19. The frame pulse detection circuit 19 detects the pattern of the frame pulse similarly to the detection circuit 15 described above. The detection pulse of each frame pulse detection circuit 15, 18, 19 is led to the output terminal 21 via the OR circuit 20.

[0009]

According to the above-mentioned conventional frame pulse detecting device, the frame pulse detecting circuit 1 is provided.
Three of 5, 18, and 19 are required, and the circuit scale becomes large, which is not suitable for integration. Therefore, it is an object of the present invention to provide a frame pulse detection device capable of accurately detecting a frame pulse while suppressing an increase in circuit scale.

[0010]

SUMMARY OF THE INVENTION According to the present invention, a level change of an input video signal is monitored, a signal level is determined according to the amount of change and a direction of change, and a signal for frame pulse determination that follows the signal level is obtained. It is provided with a means for taking it out.

[0011]

According to the above means, even if the video signal level is deviated to some extent and the MSB bit does not change, the signal for frame pulse detection can be taken out if the level change of the video signal exceeds a certain level.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The MUSE signal introduced to the input terminal 30 is sent to the A / D converter 31.
Is input to and digitized. The digital MUSE signal is noise-removed by the low-pass filter 32, and then is input to the latch circuit 33 and the subtractor 34 which constitute the calculating means. The latch pulse of the latch circuit 33 is, for example, MU.
This is 16.2 MHz which is the clock rate of the SE signal. In the subtractor 34, the latch circuit 3 is fed from the current input signal.
The output of 3 is subtracted. The difference signal from the subtractor 34 is
It is input to a code determination circuit 35 as a code determination means and a comparator 36 as a level comparison means. The comparator 36 is supplied with comparison data of a certain level from the level setting circuit 37. The comparator 36 outputs a high level (H) when the difference signal is larger than the comparison level, and outputs a low level (L) when the difference signal is smaller than the comparison level. The output of the comparator 36 is supplied to one input terminal of each of the AND circuits 38 and 39.

The sign determination circuit 35 outputs (H) in the positive direction and outputs (L) in the negative direction. The output of the sign determination circuit 35 is directly input to the other input terminal of the AND circuit 38 that constitutes the output level setting means, and is also input to the other input terminal of the AND circuit 39 via the inverting circuit 40.

As a result, when the input video signal changes in the positive direction and the amount of change exceeds the comparison level, (H) is obtained from the AND circuit 38. On the contrary, when the value changes in the negative direction and the amount of change exceeds the comparison level, (H) is obtained from the AND circuit 39. The output of the AND circuit 38 is supplied to one input end of the OR circuit 41, and the output of the AND circuit 39 is supplied to the other input end of the OR circuit 41 via the inverting circuit 42. Therefore,
The output level of the OR circuit 41 is such that the data of the input video signal is past (previously one clock) the data of the video signal.
It outputs (H) when it changes in the positive direction above the comparison level and outputs (L) when it changes in the negative direction.

The outputs of the AND circuits 38 and 39 are input to the NOR circuit 43. The output of the NOR circuit outputs (L) when the data of the input video signal is higher than the comparison level with respect to the data of the video signal of the past (before one clock). (H) when it is within the comparison level. That is, when the output of the NAND circuit 43 changes from (H) to (L) and continues (L), the selector 44 selectively derives the output of the OR circuit 41. The output of the selector 44 is
It is input to the latch circuit 45 and the frame pulse detection circuit 46. The past signal output from the selector 44 is always repeatedly latched in the latch circuit 45.

As a result, the selector 44 outputs (H) when the data of the current video signal changes in the positive direction above the comparison level with respect to the data of the past video signal, and goes above the comparison level. When changing in the negative direction, (L)
Is output. When the change in the video data is less than the comparison level, the output of the latch circuit 45 is selected from the selector 44, and the same signal, that is, the unchanged signal is output.

Now, let us consider a case in which video data as shown in FIG. 2A, (a), is input. Since the level changes across the level (200H) which is the change point of the MSB bit, the frame pulse can be easily detected with only the MSB bit. Therefore, let us consider a comparison between the case where the level is detected by the MSB bit and the case where the level is detected in FIG. When the level setting value (comparison level) of the comparator in FIG. 1 is set to (0FFH), the level becomes (0FFH
When the value exceeds H), the level in the changed direction is obtained, so that the same result as the detection with the MSB bit is obtained. Next, consider the case of (b) of FIG. When detected with the MSB bit, the signal is always at the level (200H) or less, so it is at the (L) level, but if the level set value of the comparator 36 is (0FFH), the same result as in the case of (a) is obtained, and the frame pulse Can be detected. Also, considering the case of FIG. 2C, the signal is always (200H) or more when detected with the MSB bit, and therefore becomes (H), but the comparator 36
When the level setting value of is 0FFH, the same result as in the case of FIG.

As described above, according to this system, when the level of the video signal changes by a certain amount or more with respect to the level of the video signal one cycle before at the reference clock of 16.2 MHz, the signal changes depending on the direction of the level change. A positive change and a negative change are detected, and the frame pulse is detected using this detection signal. As a result, it is not necessary to provide a plurality of frame pulse detection circuits, and the reliability of frame pulse detection can be obtained without increasing the circuit scale.
It is also possible to increase the detection speed of the frame pulse.

[0020]

As described above, according to the present invention, it is possible to detect a frame pulse accurately while suppressing an increase in circuit scale.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of the level of an input frame pulse and a diagram showing a conventional frame pulse detection circuit.

FIG. 3 is an explanatory diagram of a waveform of a frame pulse.

[Explanation of symbols]

31 ... A / D converter, 32 ... Low-pass filter, 33 ...
Latch circuit, 34 ... Subtractor, 35 ... Sign determination circuit, 36
Comparator, 37 ... Level setting circuit, 28, 39 ... AND circuit, 40, 42 ... Inversion circuit, 41 ... OR circuit, 43 ...
NOR circuit, 44 ... Selector, 45 ... Latch circuit, 46 ...
Frame pulse detection circuit.

Claims (1)

[Claims] 1. A low-pass filter means for receiving a MUSE signal to reduce transmission noise, and a level difference signal between the video data output from the low-pass filter means, the level difference between the temporally preceding and following data being calculated, Level calculating means for outputting, level change direction detecting means for judging the sign of the level difference signal output from the level calculating means, and detecting an increasing / decreasing direction of the level, and the level difference signal output by the level calculating means According to the output of the level change direction detecting means, when the level difference of the video data in the level comparing means is larger than the set level, the output level is changed according to the output of the level changing direction detecting means. When the level difference of the video data in the level comparison means is below the set level The output level and an output level setting means for the non-changing state, the frame pulse detection device is characterized in that a structure to detect the frame pulse of the MUSE signal by the output level.