JPH05292116A - Input buffer type ATM switch control circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding an input buffer type ATM switch control circuit that avoids cell contention at the output port, it can easily handle high-speed input ports and the processing time of each circuit and The purpose is to be able to flexibly deal with variations in signal propagation delay time. A structure for reading the destinations of a plurality of cells from the beginning of the FIFO memory, a table for managing cell transmission from the FIFO memory for each cell time, and a cell transmission request signal including destination information of each cell, A control means for receiving a response signal including a cell transmission time for the cell, further reserving the cell transmission from the FIFO memory at the designated cell transmission time by referring to the table, and transmitting the cell from the FIFO memory at that time. After transmitting the transmission request signal of each cell, before transmitting the cell transmission, the transmission request signal of the next cell is transmitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM switch that accommodates a plurality of input / output ports in which cells are ATM-multiplexed and routes input cells to their destination output ports. Input buffer type ATM switch with a buffer for use in input buffer type that checks whether or not the cell can be sent to the destination output port before sending the cell from the buffer and avoids cell contention at the output port The present invention relates to an ATM switch control circuit.

[0002]

2. Description of the Related Art In an input buffer type ATM switch, a cell transmission request may be issued from a plurality of input ports to one output port at the same time (cell contention at the output port). Therefore, contention occurs before cell transmission. Control is needed.
Of the conventionally known contention control methods, the scheduling control method will be described first.

FIG. 6 is a block diagram showing a configuration example of an input buffer type ATM switch to which conventional scheduling control is applied. In the figure, input ports 61 _{1 to} 61
Cells with different destinations arrive at ₃ by time division multiplexing. Cells arriving at each input port are sequentially input FIFO (Firs
t-In First-Out) 62 _{1 to} 62 ₃ are accumulated and waiting is performed. The input control units 63 _{1 to} 63 ₃ are controlled by the common control unit 65 connected via the control links 64 ₁ to 64 ₃ , and control cell transmission from each input FIFO. Cell sent from each input FIFO are respectively input to the cell transmission memory 66 _{1-66 3,} common control unit 6
It is written in the address corresponding to the cell transmission time designated by the contention control in 5, and the waiting is performed until that time. Space switch circuit 67 takes in the cells read out at a predetermined time from the cell output memory and sent to the output port 68 ₁ to 68 ₃ corresponding to the destination information. The cells corresponding to the respective destinations are time-division multiplexed and taken out from the respective output ports.

The competition control operation in the input buffer type ATM switch having such a configuration will be described below. The cell arriving at the input port 61 is the input FIFO 62.
When the data is stored in the input port, the input control unit 63 first checks the output port number of the destination of the first cell before sending the cell to the output port of the destination, and outputs the cell transmission request signal including the destination number to the control link 64. To the common control unit 65 via. The common control unit 65 calculates the time that can be sent to the output port that is the destination of the cell and assigns it to each cell. When the input control unit 63 receives from the common control unit 65 the designation of the transmission time of the cell that issued the transmission request, the input control unit 63 checks whether or not the cell can be transmitted at the designated transmission time. At this time, if the cell transmission is possible, the cell is written to the corresponding address of the cell transmission memory 66 so that the cell can be read at that time. In the cell transmission memory 66, the data (cell) at each address is sequentially read, so that each cell is read at a designated time, and the space switch circuit 67 is read.
To the corresponding output port 68 of the corresponding destination to avoid the conflict.

FIG. 7 is a block diagram showing a configuration example of an input control unit 63 used in a conventional input buffer type ATM switch. In the figure, the input control unit 63 indicates the input FI
Common control unit 65 via FO 62 and control link 64
Is connected to the input control circuit 71, and a cell transmission table 72 that is connected to the input control circuit 71 and manages the cell transmission state from the cell transmission memory 66.

The input control circuit 71 takes in the destination of the leading cell of the input FIFO 62, generates a cell transmission request signal including the destination number, and transmits it to the common control section 65 via the control link 64. When the cell transmission time is notified from the common control unit 65 via the control link 64, the cell transmission table 72 is checked to see whether or not the cell can be transmitted at the designated transmission time. At this time, if cell transmission is possible, the cell transmission table 72 is changed to the reserved state, and the input FIFO 6 is changed by the shift-out control signal.
2 is shifted and the output head cell is written in the corresponding address of the cell transmission memory 66.

Next, a three-phase algorithm will be described as another competition control method. In the input buffer type ATM switch to which this three-phase algorithm is applied,
In the configuration shown in FIG. 6, the cell transmission memories 66 _{1 to} 66 ₃ waiting for the cell transmission time designated by the contention control in the common control unit 65 are unnecessary. Hereinafter, the competition control operation of the three-phase algorithm will be described with reference to FIG. 6 for convenience.

The cell arriving at the input port 61 is the input FI.
When stored in the FO 62, the input control unit 63 checks the output port number of the destination of the first cell and sends a cell transmission request signal including the destination number to the common control unit 65 via the control link 64. When one output port receives a cell transmission request from a plurality of input ports, the common control unit 65 gives transmission permission to only one input port in order to prevent cell collision at the output port. When the input control unit 63 receives the transmission permission from the common control unit 65, the input FIFO unit 62 causes the input FIFO 62 to transmit the cell to the slot. If the transmission permission is not obtained, the input control unit 63 requests the transmission again in the subsequent slots. With such a processing sequence, the same contention control as in the scheduling control method is possible.

The input control unit 63 naturally does not need the cell sending table 72 for managing the cell sending status from the cell sending memory 66, and the processing time therefor is also unnecessary.

[0010]

By the way, a series of operations of the input control unit 63 in the conventional input buffer type ATM switch must be completed within one cell time. Therefore, it is necessary to increase the operating speed of each circuit for a high-speed input port. That is, a high-speed circuit element is required to cope with a high-speed signal, and an increase in power consumption cannot be avoided.

Further, in high speed processing, the signal propagation delay time between the circuits may be a problem. In that case, it becomes necessary to shorten the signal propagation delay time by shortening the wiring length between the circuits as much as possible. However, considering the signal propagation delay time due to such a wiring length, the circuit design becomes significantly complicated.

The present invention controls an input buffer type ATM switch which can easily cope with a high-speed input port and can flexibly cope with variations in processing time of each circuit and signal propagation delay time between each circuit. The purpose is to provide a circuit.

[0013]

According to a first aspect of the present invention, an input cell in which ATM cells having different destinations are time-division multiplexed is stored in a FIFO memory, and a routing process of the cell between the input and output ports is performed by scheduling control. In the input buffer type ATM switch for performing the operation, a means for reading the destinations of a plurality of cells from the head of the FIFO memory, and a FIFO
A table that manages cell transmission from the O memory for each cell time, a cell transmission request signal including the destination information of each cell, and a response signal including the cell transmission time corresponding thereto are received, and the table is further referred to. The cell transmission from the FIFO memory is reserved at the cell transmission time specified by the above, and a control means for transmitting the cell from the FIFO memory at that time is provided, until the cell transmission is performed after the transmission request signal of each cell is transmitted. The configuration is such that the transmission request signal of the next cell is transmitted before the completion of the series of processes.

According to the second aspect of the present invention, A having different destinations is used.
An input buffer type AT which stores an input cell in which TM cells are time-division-multiplexed in a FIFO memory and performs cell routing processing between input / output ports by a three-phase algorithm
In the M switch, a means for reading the destinations of a plurality of cells from the head of the FIFO memory and a cell transmission request signal including the destination information of each cell are transmitted, and a response signal including a transmission permission for the cell is received, and the transmission permission is used. A control means for sending the corresponding cell from the FIFO memory,
After the transmission request signal of each cell is transmitted, the transmission request signal of the next cell is transmitted before the series of processing until the cell transmission is completed.

[0015]

The present invention advances the transmission control processing for each cell in parallel by starting the transmission control for the next cell before the transmission control processing for each cell is completed. This eliminates the need to end the transmission control processing of each cell within one cell period, and allows independent control systems to be used, so that high-speed input ports can be easily dealt with. Further, by performing the transmission control processing for a plurality of cells in parallel, it is possible to make room for the overall processing time, and it is possible to sufficiently absorb even a slight variation in each processing time or signal propagation time.

[0016]

First, an embodiment of the control circuit of the present invention used in an input buffer type ATM switch to which scheduling control is applied will be described.

FIG. 1 is a block diagram showing the configuration of the first embodiment. In the figure, in the control circuit of the present embodiment, as a means for reading the destinations of a plurality of cells, an input FIFO with a tap capable of reading one or both of the first cell and the next cell.
O10 is used. The input control circuit 11 and the selector 12 that selects one of the first two cells are connected to the two taps of the input FIFO 10, and the cell output memory 66 is connected to the output of the selector 12. Input control circuit 11
In addition, the common control unit 65 is further connected via the control link 64.
Is connected to the cell transmission table 13 for managing the cell transmission status from the cell transmission memory 66, and the input FIFO 10 is connected.
In this configuration, a control signal for controlling the reading is sent to.

That is, the feature of this embodiment is that the input F
The IFO 10 has a structure in which one or both of the first cell and the next cell can be read, and the input control circuit 11 can simultaneously access the common control unit 65 for the destinations of a plurality of cells.

An example of the control operation of the conventional circuit and the first example of the control operation of the circuit of the present invention will be described below with reference to FIG. The upper stage is an example of control operation of the conventional circuit, and the lower stage is an example of control operation of the circuit of the present invention.

In the conventional cell transmission control, the input control circuit 71 reads the cell destination and generates a cell transmission request signal, the processing time a ₁₁ , the input control section 63 to the common control section 65.
Propagation time b ₁₁ of the cell transmission request signal to the common control unit 65
Processing time a ₂₁ for calculating the cell transmission time, the propagation time b ₂₁ of the response signal from the common control unit 65 to the input control unit 63, and the processing time a ₂₁ for the input control circuit 71 to refer to and change the cell transmission table 72. ₃₁ , input F from the input control unit 63
Propagation time b ₃₁ of control signal to IFO 62, input FIFO
The processing time a ₄₁ for reading the cell from 62 was required.
The same applies to the next cell. Thus, in the conventional scheduling control, for each cell,
Decoding of the cell destination, transmission of a cell transmission request signal, reception of a response signal (cell transmission time), checking of the cell transmission table, and cell transmission processing from the input FIFO were performed in order. Therefore, a signal propagation time is required between each processing, and furthermore, it is necessary to end the series of processing for each cell period.

On the other hand, in the first control operation example, each processing is simultaneously performed on two cells. Therefore, the propagation time b ₁ of the cell transmission request signal from the input control circuit 11 to the common control unit 65, the common control unit 65 to the input control circuit 11
The propagation time b ₂ of the response signal to the input FIFO 10 and the propagation time b ₃ of the control signal from the input control circuit 11 to the input FIFO 10 are approximately halved because two cells can be combined. That is, for two cells, the input control circuit 11 reads their destinations and generates the cell transmission request signals, the processing times a ₁₁ and a ₁₂ , and the processing time for calculating the cell transmission time in the common control unit 65. Even when a ₂₁ , a ₂₂ , processing times a ₃₁ , a _{32 for} the input control circuit 11 to refer to and change the cell transmission table 13 and processing times a ₄₁ , a ₄₂ for reading two cells from the input FIFO 10 are summed up, respectively. The overall time can be shortened by reducing the signal propagation time.

Moreover, since the processing for two cells only has to be completed within the two-cell period, even if there is some variation in each processing time or each signal propagation time, it is possible to flexibly cope with it compared with the conventional method. it can.

FIG. 3 is a block diagram showing the configuration of the second embodiment. Although the control circuit of the present embodiment is functionally equivalent to that of the first embodiment, in contrast to the configuration in which the input FIFO 10 with a tap is used in the first embodiment, in the present embodiment, a normal FIFO is used. It is a configuration example that enables use.

In the figure, the output of the input FIFO 62 is supplied to the buffer 32 ₁ for one cell via the selector 31,
32 ₂ is connected. The destination of the cell output from each buffer is input to the input control circuit 33, and the cell is output to the cell output memory 66 via the selector 34. The input control circuit 33 is further connected via a control link 64 to a common control unit 65 and a cell transmission table 35 that manages the cell transmission status from the cell transmission memory 66, and controls the input FIFO 62 to control reading. And a control signal for controlling the selection operation is sent to each selector 31, 34.

Also in this embodiment, the first control operation example shown in the lower part of FIG. 2 can be applied as it is. That is, first, two cells of the input FIFO 62 are connected to the selector 31.
Are sequentially written to the buffers 32 ₁ and 32 ₂ via
The destination of each cell is read by the input control circuit 33 and sent to the common control unit 65 via the control link 64. Also,
The input control circuit 33 receives the cell transmission time of each cell as a response signal, and refers to / changes the cell transmission table 35. As a result, the selector 32 is controlled to select the buffer 32 that can be transmitted, and the cell is transmitted to the cell transmission memory 6
6 and sends the selector 3 to the buffer 32.
1 is controlled to fetch a new cell from the input FIFO 62. After that, the same processing is repeated. Thus, in this embodiment, a normal FIFO with one output can be used,
The structure of the input FIFO can be simplified.

In the above description, an example in which the processing for a plurality of cells (two cells in the first control operation example shown in FIG. 2) is continuously performed has been shown. However, the processing is separated cell by cell and the previous cell is processed. The same is true even if the processes are started in parallel (in a pipeline) before the end of the process. It should be noted that the circuit for realizing this control operation is basically the same as the other embodiments shown in FIGS. 1 and 3, except that the control algorithm of the input control circuits 11 and 33 is changed. You can An example of the second control operation is shown in FIG.

Processing time a ₁₁ for reading the cell destination and generating a cell transmission request signal, propagation time b ₁₁ for the cell transmission request signal from the input control circuits ₁₁ and 33 to the common control unit 65, and the cell in the common control unit 65 Processing time a ₂₁ for calculating the sending time, from the common control unit 65 to the input control circuit 1
Propagation time b ₂₁ of the response signal to 1, 33, input control circuit 1
1 processing time a ₃₁ for referencing / changing the cell transmission tables 13 and 35, input FIFO 1 from the input control circuits 11 and 33
Propagation time b ₃₁ of control signal to 0, 62, input FIFO1
The processing time a ₄₁ for reading cells from 0 and 62 is the same as the control operation example of the conventional circuit, and is the same for the cells.

The feature of the second control operation example is that the processing for the next cell is started before the processing for the cell is completed, which is the control operation example of the conventional circuit and the first circuit of the circuit of the present invention. Different from the control operation example.

By the way, in the control operation based on the scheduling control method, the cell transmission information is managed independently for each output port, and if the destinations of consecutive cells are different, before the transmission control of the preceding cell is completed. There is no problem even if the transmission control of the next cell is started. However, when the destinations of consecutive cells are the same, the input control circuit (11, 33) needs the following control.

If the cell can be sent at the specified time, there is no change in the operation of the input control circuit. When the cell cannot be transmitted at the specified time, the transmission control is performed again during the cell period of the cell, for example. At this time, the fact that cells of the same destination can be transmitted means that the cell transmission table check processing time a ₃₂
If it is found in the above, the transfer from the input FIFO to the cell sending memory is performed so that the cell is sent at the designated time.
In addition, transmission control (a _13-
a ₄₃ ) is diverted to the control operation relating to the cell. Thus, for cells destined for the same destination output port,
In order to preserve the time order of cells, it is necessary to control transmission in the order in which they arrive at the input port. Note that the transmission control for cells is shifted during the cell period of the cell. The same applies between cells.

Although the example in which the cell transmission control is performed in parallel for two cells has been described above, the parallel control for three cells or more can be similarly described. Next, an embodiment of the control circuit of the present invention used in the input buffer type ATM switch to which the competitive control method of the three-phase algorithm is applied will be described. The circuit configuration is basically the same as that of the embodiment shown in FIGS. 1 and 3, except that the cell transmission tables 66 are removed as the cell transmission memory 66 becomes unnecessary. realizable.

An example of the control operation of the circuit of the present invention to which the 3-phase algorithm is applied will be described below with reference to FIG. In this control operation example, the processing time c ₁₁ for reading the cell destination and generating the cell transmission request signal, the input control circuit 1
1, 33, a propagation time d ₁₁ of a cell transmission request signal from the common control unit 65 to the common control unit 65, a processing time c ₂₁ for selecting an input port to which the common control unit 65 permits transmission, and the common control unit 65 to the input control circuits 11 and 33. In parallel with the propagation time d ₂₁ of the response signal to the cell and the processing time c ₃₁ for reading cells from the input FIFOs 10 and 62, the processing for cells is started. In the three-phase algorithm, the input control circuit 1
1,33 eliminates time corresponding to the processing time a _31, a ₃₂ to reference-cell emission table 13 and 35, but the control operation can be explained in the same manner as the above-described example.
The same applies to control when the destinations of consecutive cells are the same.

[0033]

As described above, according to the present invention, a control circuit applicable to a high-speed input port can be easily realized, and in terms of speed, even if processing can be performed within one cell period, there is a margin in the overall processing time. Therefore, the design of the operation timing of the circuit can be simplified. That is, even if there is some variation in each processing time or signal propagation time, it is possible to flexibly deal with it.

When the transmission control cannot be processed within one cell period in order to apply to a high speed input port,
In the past, a high-speed circuit was used to deal with the problem, but by using the circuit of the present invention, a low-speed and highly integrated element can be used, and power consumption and the number of chips can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment.

FIG. 2 is a diagram showing a control operation example of a conventional circuit to which scheduling control is applied and a first control operation example of the circuit of the present invention.

FIG. 3 is a block diagram showing the configuration of a second embodiment.

FIG. 4 is a diagram showing a second control operation example of the circuit of the present invention to which scheduling control is applied.

FIG. 5 is a diagram showing an example of control operation of a circuit of the present invention to which a 3-phase algorithm is applied.

FIG. 6 is a block diagram showing a configuration example of a conventional input buffer type ATM switch to which scheduling control is applied.

FIG. 7 is a diagram showing a configuration example of an input control unit 63.

[Explanation of symbols]

 10 Input FIFO 11 Input Control Circuit 12 Selector 13 Cell Transmission Table 31, 34 Selector 32 Buffer 33 Input Control Circuit 35 Cell Transmission Table 61 Input Port 62 Input FIFO 63 Input Control Unit 64 Control Link 65 Common Control Unit 66 Cell Transmission Memory 67 Space Switch circuit 68 Output port 71 Input control circuit 72 Cell transmission table

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9076-5K H04Q 11/04 R

Claims (2)

[Claims] 1. An input buffer type ATM switch which stores an input cell in which ATM cells having different destinations are time-division-multiplexed in a FIFO memory, and performs a routing process of the cell between the input and output ports by scheduling control. A means for reading the destinations of a plurality of cells from the head, a table for managing the cell transmission from the FIFO memory for each cell time, a cell transmission request signal including destination information of each cell, and a cell transmission time for the cell Receiving a response signal including, and further, the cell transmission from the FIFO memory is reserved at the cell transmission time designated by referring to the table,
A control means for transmitting a cell from the FIFO memory at that time is provided, and after transmitting a transmission request signal for each cell, before transmitting a cell, a transmission request signal for the next cell is transmitted. A control circuit for an input buffer type ATM switch having a structure for transmitting. 2. An input buffer type ATM switch for accumulating an input cell in which ATM cells having different destinations are time-division-multiplexed in a FIFO memory and performing a routing process of the cell between the input and output ports by a three-phase algorithm. Means for reading the destinations of a plurality of cells from the head of the cell, and a cell transmission request signal including the destination information of each cell is transmitted, and a response signal including a transmission permission for the cell is received, and the transmission permission responds from the FIFO memory. A control means for transmitting a cell is provided, and after the transmission request signal of each cell is transmitted, the transmission request signal of the next cell is transmitted before the series of processing until cell transmission is completed. A control circuit of a characteristic input buffer type ATM switch.