JPH05291586A - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] The element isolation region is miniaturized, a large cell current flows during reading, the access speed is fast, and
A device with good cutoff characteristics is obtained. In a nonvolatile semiconductor memory device, in particular, a NAND type nonvolatile semiconductor memory device, a groove 2 formed in an element isolation region of a semiconductor substrate 7 and an element isolation film provided in the groove except the upper portion thereof. 9 and a charge storage layer 5 formed at least from the upper surface of the element region 1 of the semiconductor substrate 7 to the upper sidewalls of the trenches on both sides with a gate insulating film 6 interposed therebetween.
And a control gate electrode 3 formed on the charge storage layer via an insulating film 4, a charge storage layer 5 in the element region 1, and source and drain regions provided with the control gate electrode 3 interposed therebetween. Is configured. According to the present invention, the access speed is high,
In addition, a nonvolatile semiconductor memory device having good cutoff characteristics can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a charge storage layer and a control gate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a conventional nonvolatile semiconductor memory device having a charge storage layer and a control gate, an element isolation region is formed by a thick insulating film. This conventional memory cell has the following three problems. First of all, in order to perform element isolation between memory cells, in particular, in order to secure a sufficient inversion breakdown voltage, under the field oxide film,
Impurities for preventing inversion are injected. The PN junction breakdown voltage is lowered due to the impurities for preventing inversion, which hinders miniaturization of the element isolation region. Second, in order to reduce the write / erase voltage of the memory cell, the charge storage layer is formed on the field oxide film in order to make the capacitance between the charge storage layer and the substrate equal to the capacitance between the charge storage layer and the control gate electrode. It has been postponed. Therefore, a charge storage layer region on the element isolation region,
Since the charge storage layer isolation region is required, miniaturization of the element isolation region is hindered. Thirdly, the electrical element region width is reduced by implanting the inversion preventing impurity under the field oxide film as pointed out in the first. Therefore, the cell current at the time of reading is reduced due to the narrow channel effect, and the access speed is reduced. Fourthly, in particular, a NAND type EEPROM in which memory cells are connected in series
In the case of, the substrate potential fluctuates due to noise, the source potential fluctuates due to charging / discharging of additional capacitance, etc., and as a result, the threshold voltage of the memory cell fluctuates, and the back bias effect due to the floating source potential fluctuates reading. The cell current at that time is reduced, and the access speed is significantly reduced. As described above, there are three major problems in the conventional memory cell structure. Further, there is a demand for a device having a good cutoff characteristic, and therefore a drain current rising sharply with respect to a change in gate voltage.

[0003]

As described above, according to the conventional technique, the miniaturization of the element isolation region is hindered, and the cell current at the time of reading is reduced, so that the access speed is lowered. There was a problem that it would end up.

An object of the present invention is to provide a non-volatile semiconductor memory device having a fine element isolation region, a large cell current during reading, a high access speed and a good cutoff characteristic. Another object of the present invention is to provide a method for manufacturing such a nonvolatile semiconductor memory device.

[0005]

The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a NAND type nonvolatile semiconductor memory device, in which a groove formed in an element isolation region of a semiconductor substrate and an upper portion of the groove are removed. And a charge storage layer formed through the gate insulating film at least from the upper surface of the element region of the semiconductor substrate to the upper sidewalls of the trenches on both sides, and the charge storage layer on the charge storage layer. A control gate electrode formed via an insulating film, a charge storage layer in the element region, and source and drain regions provided with the control gate electrode sandwiched therebetween.

In the nonvolatile semiconductor memory device having the above structure, the distance between the sidewalls of the groove in the channel width direction is
The depth of the depletion layer in the central portion of the channel is set to be deeper than when the gate electrode is provided only on the upper surface of the element region, or the depth of the depletion layer in the central portion of the channel is set to the gate electrode only on the upper surface of the element region. It is characterized in that it is set to be deeper than the case where is provided, and to be closer than the depletion layers extending from the side walls are in contact with each other.

In addition, in the nonvolatile semiconductor memory device having the above structure, the distance between the sidewalls of the groove in the channel width direction is widened from the source region to the drain region. Further, the groove formed in the element isolation region of the semiconductor substrate is formed so as to extend over a plurality of control gate electrodes in the NAND memory cell.

Further, the element isolation film is formed of a conductor wrapped with an insulator, and the potential of the conductor is the potential of the source or the potential of the source and the substrate, or if the memory cell is formed in the WELL. Then sauce and its W
The conductor is electrically connected to the source so as to have the same potential as the ELL.

[0009]

The charge storage layer and the control gate electrode formed from the upper surface of the element region to the side wall of the groove exert a comparatively large electric field on the edge of the groove. As a result, a depletion layer having a larger radius than the flat portion, that is, a larger extension is generated around the corner. When the depletion layers extending from the respective corners in the channel width direction overlap to each other, the depth of the depletion layer in the central portion of the channel in the gate width direction becomes deeper than when the gate electrode is provided only on the upper surface of the element region. In such a state, the corner transistor dominates the transistor characteristics. Since the corner transistor has a larger gate control force and a stronger electric field in the channel portion than a transistor formed in a flat portion, the back bias effect is less likely to appear. When the depletion progresses and the distance between the side walls becomes closer than the contact between the depletion layers extending from the side walls, the influence of the back bias effect disappears. Further, under the above-mentioned control of the corner transistor, a device having excellent cutoff characteristics can be obtained because the change in the gate electrode is large.

As described above, in a non-volatile semiconductor memory device, particularly a NAND type non-volatile semiconductor memory device, a groove formed in an element isolation region of a semiconductor substrate and an element provided in the groove excluding the upper portion. An interlayer isolation film, a charge storage layer formed through a gate insulating film at least from the upper surface of the element region of the semiconductor substrate to the upper sidewalls of the trenches on both sides, and an insulating film over the charge storage layer. A control gate electrode formed, and a charge storage layer in the element region, and a structure provided with a source and drain regions provided with the control gate electrode sandwiched, a large cell current at the time of reading can be obtained, and It is possible to provide cells with fast access speed.

Further, by adopting such a structure that there is a step between the element portion and the element isolation portion as described above, the capacitance between the charge storage layer and the substrate and the charge accumulation in the side wall portion in the groove of the element isolation region. Since it is possible to form a region that extends the charge storage layer over the field oxide film for making the capacitance between the layer and the control gate electrode the same, it is not necessary to form this region in the device isolation region, and therefore the device isolation region It becomes possible to miniaturize.

Further, the element isolation film is formed of a conductor wrapped with an insulator, and the potential of the conductor is the potential of the source, the potential of the source and the substrate, or if the memory cell is formed in the WELL. Then sauce and its W
By electrically connecting the conductor to the source so as to have the same potential as the ELL, the electrical element region width is reduced, and the impurity concentration for inversion prevention under the field oxide film is reduced. Therefore, the narrow channel effect can be suppressed, the cell current at the time of reading increases, and the access speed improves.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view showing the structure. 2 is a plan view of a single memory cell, and FIG. 3 is a NAN.
It is a top view of a D-type memory cell. Further, as shown in FIG. 3, in the NAND type memory cell, the groove formed in the element isolation region of the semiconductor substrate is formed over a plurality of control gate electrodes in the NAND type memory cell.

The nonvolatile semiconductor memory device of the present invention shown in FIG. 1 has a groove (2) formed in an element isolation region of a semiconductor substrate (7) and an element isolation film (excluding an upper portion) provided in the groove. 9) A charge storage layer (5) formed at least from the upper surface of the isolation region (2) of the semiconductor substrate (7) to the upper sidewalls of the trench on both sides with a gate insulating film (6) interposed therebetween.
And a control gate electrode (3) formed on the charge storage layer (5) via an insulating film (4), and the charge storage layer (5) and the control gate electrode (3) in the element region (1). It is mainly composed of a source region and a drain region which are provided so as to sandwich.

In the nonvolatile semiconductor memory device of the present invention having such a structure, the charge storage layer (5) and the control gate electrode formed from the upper surface of the element region (1) to the sidewall of the groove (2). (3) can apply a relatively large electric field to the groove edge. As a result, a depletion layer having a larger diameter than the flat portion, that is, a larger elongation is generated around the corner, and the influence of the back bias effect is less likely to appear, and a device having excellent cut-off characteristics can be obtained. A device with a high access speed can be used.
4A to 4G are process cross-sectional views taken along the line AA ′ in FIG. 1. For convenience, the description will be given along the first manufacturing method thereof to facilitate understanding. 5A and 5B are process cross-sectional views according to the second manufacturing method. 6 (a) and 6 (b)
[Fig. 4] is a perspective view showing another embodiment and a cross-sectional view taken along the line AA '.

The element isolation film is formed of a conductor wrapped with an insulator, and the conductor is electrically connected or the element ionization film is insulated so that the potential of the conductor is the same as the potential of the source. It is made of a conductor wrapped around the body, and the potential of the conductor is the potential of the source and substrate, or if the memory cell is W
Source and its WEL if formed in ELL
The conductor is electrically connected or the element isolation film is formed of a conductor wrapped with an insulator so that the potential becomes the same as the potential of L, and the potential of the conductor becomes the same as the potential of the source. , The conductor may be electrically connected. FIG. 7 is a plan view of a single memory cell in which the distance between the sidewalls of the groove in the channel width direction increases from the source region to the drain region.

[0018]

According to the present invention, by miniaturizing the element isolation region, a cell current at the time of reading can be increased, an access speed can be increased, and a nonvolatile semiconductor memory device having a good cutoff characteristic can be obtained.

[Brief description of drawings]

FIG. 1 is a perspective view showing an apparatus according to an embodiment of the present invention.

FIG. 2 is a plan view of a single memory cell.

FIG. 3 is a plan view of a NAND memory cell.

FIG. 4 is a cross-sectional view showing the manufacturing process of the device of the present invention.

FIG. 5 is a process sectional view according to a second manufacturing method of the device of the present invention.

FIG. 6 is a structural explanatory view showing another embodiment of the present invention.

FIG. 7 is a plan view of a single memory showing another embodiment of the present invention.

[Explanation of symbols]

1 n ⁺ Region (device region) 2 Groove (device isolation region: polysilicon) 3 Control gate electrode 4 Insulating film (SiO ₂ ) 5 Floating gate (charge storage layer) 6 Gate insulating film 7 Semiconductor substrate 8 Silicon oxide film (SiO ₂ ) 9 Silicon oxide film (SiO ₂ ) 10 Silicon oxide film (SiO ₂ )

Front page continuation (72) Inventor Seiichi Aridome 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Research Institute

Claims (8)

[Claims] 1. A groove formed in an element isolation region of a semiconductor substrate, an element isolation film provided in the groove excluding an upper portion, and at least an upper portion of the groove on both sides from an upper surface of the element region of the semiconductor substrate. A charge storage layer formed over the side wall via a gate insulating film, a control gate electrode formed over the charge storage layer via an insulating film, a charge storage layer in the element region, and a control gate electrode A non-volatile semiconductor memory device comprising a source and a drain region which are provided so as to sandwich it. 2. An NA in which a plurality of memory cells each having a charge storage layer and a control gate stacked on a semiconductor substrate are connected in series.
In the ND type cell, the memory cell includes a groove formed in an element isolation region of a semiconductor substrate, an element isolation film provided in the groove excluding an upper portion, and at least both sides from an upper surface of the element region of the semiconductor substrate. A charge storage layer formed on the upper side wall of the groove via a gate insulating film, a control gate electrode formed on the charge storage layer via an insulating film, and a charge storage layer on the element region. And a source and drain region provided with a control gate electrode sandwiched therebetween, a non-volatile semiconductor memory device. 3. The non-volatile semiconductor according to claim 2, wherein the groove formed in the element isolation region of the semiconductor substrate is formed over a plurality of control gate electrodes in the NAND memory cell. Storage device. 4. The element isolation film is formed of a conductor wrapped with an insulator, and the potential of the conductor is the potential of the source or the potential of the source and the substrate, or if the memory cell is WE.
Source and its WELL if formed in LL
2. The non-volatile semiconductor memory device according to claim 1, wherein the conductor is electrically connected to the source so as to have the same potential as that of the above. 5. The distance between the sidewalls of the groove in the channel width direction is set so that the depth of the depletion layer in the central portion of the channel is deeper than that when the gate electrode is provided only on the upper surface of the element region. 3. The non-volatile semiconductor memory device according to claim 1 or 2. 6. The distance between the sidewalls of the groove in the channel width direction is set so that the depth of the depletion layer in the central portion of the channel becomes deeper than that when the gate electrode is provided only on the upper surface of the element region, and the sidewalls. 3. The non-volatile semiconductor memory device according to claim 1, wherein the depletion layers extending from the non-volatile semiconductor memory device are set closer to each other than to be in contact with each other. 7. The nonvolatile semiconductor memory device according to claim 1, wherein the distance between the sidewalls of the groove in the channel width direction is widened from the source region toward the drain region. 8. A step of forming a groove in an element isolation region of a semiconductor substrate, a step of embedding an element isolation film in the groove except for an upper portion, and upper sidewalls of the groove on both sides from an upper surface of the element region of the semiconductor substrate. Forming a charge storage layer across a gate insulating film, forming a control gate electrode on the charge storage layer via an insulating film, a charge storage layer in the element region, and a control gate A method of manufacturing a non-volatile semiconductor memory device, comprising the step of forming source and drain regions in the element region by self-aligning with electrodes.