JPH05291503A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] While suppressing the increase of input / output capacitance of each signal terminal,
In other words, while shortening the signal transmission delay time and reducing the chip area, the electrostatic breakdown withstand voltage of a dynamic RAM having a plurality of power supply systems is improved. [Structure] An electrostatic protection circuit is provided corresponding to each signal terminal, that is, a first semiconductor layer DA10 provided corresponding to a bonding pad PA1 and the like, and power supply voltages VCC1 and VCC2 and ground potentials VSS1 and VSS2. A plurality of second semiconductor layers DA that are formed so as to face each other in different combinations, including those that surround the corresponding first semiconductor layer DA10 and constitute an adjacent electrostatic protection circuit.
11 to DA14 and the like. As a result, an electrostatic protection circuit that can deal with electrostatic breakdown between each signal terminal and each power supply system and between different power supply systems can be formed with a relatively small required layout area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
For example, a dynamic RAM having a plurality of power supply systems
The present invention relates to a large-scale integrated circuit such as (random access memory) and a technique particularly effective for use in electrostatic protection thereof.

[0002]

2. Description of the Related Art A dynamic type R having an electrostatic protection circuit
I have AM. Further, there are a logic integrated circuit having a plurality of power supply systems and a static RAM.

Dynamic RA with electrostatic protection circuit
M is described in, for example, Japanese Patent Application No. 1-65838.

[0004]

In a conventional logic integrated circuit or static RAM having a plurality of power supply systems, the standard for electrostatic breakdown voltage is relatively lenient, and the electrostatic protection circuit is representative of each signal terminal. It is provided only between the power supply system. On the other hand, in the conventional dynamic RAM, the standard for electrostatic breakdown voltage is relatively strict, but its power supply system is unified, and an electrostatic protection circuit capable of supporting a plurality of power supply systems has not been put into practical use.

With the progress of integrated circuit technology in recent years,
Byte widening and ECL for dynamic RAM
Demand for (Emitter Coupled Logic) interface support is increasing, and it is expected that multiple power supply systems will be used even in dynamic RAMs that have strict standards for electrostatic breakdown voltage. For this reason, it is necessary to take electrostatic protection measures to cope with this, but the conventional dynamic type R
When the electrostatic protection circuit used in AM is provided between each signal terminal and a plurality of power supply systems, the input / output capacitance of the signal terminal increases, the signal transmission delay time increases, and electrostatic protection The required layout area of the circuit becomes large,
The chip area of the dynamic RAM increases. Also,
In particular, when the use area of each power supply system is limited, the layout area of the power supply wiring that connects each power supply and the electrostatic protection circuit becomes large, which also results in an increase in the chip area of the dynamic RAM.

An object of the present invention is to suppress the increase of the input / output capacitance of each signal terminal and the increase of the layout area of the power supply wiring, in other words, to reduce the signal transmission delay time and the chip area, and at the same time It is to improve the electrostatic breakdown withstand voltage of a large-scale integrated circuit having a power supply system.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, an electrostatic protection circuit of a large-scale integrated circuit such as a dynamic RAM having a plurality of power supply systems, a first semiconductor layer provided corresponding to each signal terminal, a power supply voltage supply terminal of each power supply system, and a ground. It basically comprises a plurality of second semiconductor layers which are provided corresponding to the potential supply terminals and surround the first semiconductor layer and are formed so as to face each other. In addition, when the use area of each power supply system is limited, the electrostatic protection circuit is provided with the first semiconductor layer and the second protection layer provided corresponding to the power supply voltage supply terminal and the ground potential supply terminal of the corresponding use area. A semiconductor layer is basically formed, and second semiconductor layers provided corresponding to the power supply voltage supply terminal or the ground potential supply terminal having the same potential and formed in different use areas are bidirectionally coupled via a diode pair.

[0009]

According to the above means, it is possible to form an electrostatic protection circuit having a relatively small required layout area to cope with electrostatic breakdown between the signal terminal and each power supply system and between different power supply systems. Also, when the use area of each power supply system is limited, without providing many power supply wiring,
The power supply voltage supply terminals or the ground potential supply terminals having the same potential can be bidirectionally coupled to enhance the electrostatic breakdown voltage between the power supply systems. This suppresses an increase in the input / output capacitance of each signal terminal and an increase in the layout area of the power supply wiring,
In other words, it is possible to improve the electrostatic breakdown voltage of a large-scale integrated circuit such as a dynamic RAM having a plurality of power supply systems, while shortening the signal transmission delay time and reducing the chip area.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a board layout diagram of an embodiment of a large scale integrated circuit LSI to which the present invention is applied. Based on the figure, first, an outline of the substrate arrangement of the large-scale integrated circuit LSI of this embodiment will be described. The large scale integrated circuit LSI of this embodiment constitutes a relatively large capacity dynamic RAM. Further, in the following description, the vertical and horizontal directions of the semiconductor substrate SUB will be expressed with the positional relationship of FIG.

In FIG. 1, the large-scale integrated circuit LSI of this embodiment is not particularly limited, but internal logic circuits LC1 and LC arranged so as to occupy most of the surface of the semiconductor substrate SUB.
2 is provided. In this embodiment, the semiconductor substrate SUB
Is formed by using P-channel type single crystal silicon as a substrate, and the internal logic circuits LC1 and LC2 are P-channel and N-channel MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are used as insulated gates. Type field-effect transistor)
Are combined to form a large number of CMOS (complementary MOS) logic circuits composed of extremely fine elements.

Above the internal logic circuit LC1, m bonding pads PA are provided along the upper side of the semiconductor substrate SUB.
1 to PAm are arranged, and 2 on each of the upper left and right.
Individual bonding pads PVC1A and PVC1B and PVS1A and PVS1B are arranged. Of these, the bonding pads PA1 to PAm are respectively coupled to signal terminals for inputting or outputting predetermined signals via bonding wires (not shown). Further, the bonding pads PVC1A and PVC1B are commonly coupled to a power supply voltage supply terminal to which the power supply voltage VCC1 is supplied, and the bonding pads PVS1A and PVS1B are connected.
Are commonly coupled to a ground potential supply terminal to which the ground potential VSS1 is supplied.

Similarly, in the lower part of the internal logic circuit LC2,
The n bonding pads PB1 to PBn are arranged along the lower side of the semiconductor substrate SUB, and two bonding pads PVC2A and PVC are provided on the lower left and right sides thereof, respectively.
2B and PVS2A and PVS2B are placed.
Of these, the bonding pads PB1 to PBn are respectively coupled to signal terminals for inputting or outputting predetermined signals via bonding wires (not shown). Further, the bonding pads PVC2A and PVC2B are
Both are commonly coupled to the power supply voltage supply terminal to which the power supply voltage VCC2 is supplied, and are bonded to the bonding pads PVS2A and P
Both VS2B are commonly coupled to the ground potential supply terminal to which the ground potential VSS2 is supplied.

Power supply voltage VCC1 and ground potential VSS1
Is supplied as the operating power supply for the internal logic circuit LC1, and the power supply voltage VCC2 and the ground potential VSS2 are supplied as the operating power supply for the internal logic circuit LC2. As a result, the large scale integrated circuit LSI of this embodiment has two power supply systems, and the use area of each power supply system is limited by the internal logic circuits LC1 and LC2. The two power supply voltage supply terminals to which the power supply voltages VCC1 and VCC2 are supplied and the two ground potential supply terminals to which the ground potentials VSS1 and VSS2 are supplied are commonly coupled to each other outside the package of the large scale integrated circuit LSI, Power supply voltages VCC1 and VCC2 and ground potential V
Both SS1 and VSS2 have the same potential.

FIG. 2 shows a partially enlarged layout view of one embodiment of the large scale integrated circuit LSI shown in FIG. The outline and features of the electrostatic protection circuit of the large-scale integrated circuit LSI of this embodiment will be described with reference to FIG. Although FIG. 2 exemplifies a portion relating to the four bonding pads PA1 to PA4 arranged on the upper left portion of the semiconductor substrate SUB and the corresponding electrostatic protection circuit, other portions corresponding to the signal terminals are shown. A similar electrostatic protection circuit is also provided for the bonding pad. Further, in the figure, a portion shown by a thick solid line is a so-called metal wiring layer made of an aluminum wiring layer, and a portion shown by a thin solid line is a so-called semiconductor layer made of an N channel type diffusion layer or a buried layer. Is. Hereinafter, the bonding pads PA1 to PA4 and corresponding electrostatic protection circuits will be described as examples.

In FIG. 2, the bonding pad PA1 made of an aluminum wiring layer is directly coupled to the semiconductor layer DA10 (second semiconductor layer) via the aluminum wiring layer, and is further coupled to one electrode of the well resistance WR1. .. The other electrode of the well resistance WR1 is coupled to the drain region D1 of the N-channel MOSFET M1 via another aluminum wiring layer, and the internal logic circuit LC is further connected.
1 is coupled to the input terminal of the input buffer IAB1. The gate layer G1 and the source region S1 of the MOSFET M1 are commonly coupled via an aluminum wiring layer,
Further, it is coupled to the ground potential VSS1. This makes M
The OSFET M1 has a diode shape in which its cathode electrode is directed to the bonding pad PA1 and acts as a so-called clamp MOSFET of an electrostatic protection circuit.

Similarly, the bonding pads PA2 to PA
4 are coupled to corresponding semiconductor layers DA20 to DA40 (second semiconductor layers) via aluminum wiring layers, respectively, and further coupled to corresponding one electrodes of well resistors WR2 to WR4. The other electrodes of the well resistors WR2 to WR4 are connected to the drain regions D2 to D2 of the corresponding N-channel MOSFETs M2 to M4 via other aluminum wiring layers.
Coupled to D4 and further corresponding input buffer IAB2
~ Coupled to the input terminal of IAB4. MOSFET M2
-M4 gate layers G2-G4 and source regions S2-
S4 is commonly coupled through the aluminum wiring layer and further coupled to the ground potential VSS1. As a result, the MOSFETs M2 to M4 are diode-shaped with their cathode electrodes facing the corresponding bonding pads PA2 to PA4, and both function as clamp MOSFETs.

In this embodiment, the periphery of the semiconductor layer DA10 is surrounded by the semiconductor layer DA10 and is opposed to each other.
Individual semiconductor layers DA11 to DA14 (first semiconductor layers) are formed. Of these, the semiconductor layers DA11 and DA12
Are coupled to the power supply voltage VCC1 and the ground potential VSS1, respectively, and the semiconductor layers DA13 and DA14 are coupled to the power supply voltages VCC2 and VSS2, respectively. As a result, the N-channel semiconductor layer DA10 forms a PN junction diode with the P-channel semiconductor substrate SUB, and the N-channel semiconductor layers DA11 to DA14.
Also, the PN junction diodes are formed between the semiconductor substrate SUB and the semiconductor substrate SUB. As a result, the bonding pad PA1 is supplied with the power supply voltages VCC1 and VC1 via the semiconductor substrate SUB, in other words, via two diodes which are connected in series so that their anodes are commonly coupled.
C2 and the ground potentials VSS1 and VSS2, respectively, and the power supply voltage VCC1 and the ground potentials VSS1 and VSS2, and the power supply voltage VCC2 and the ground potentials VSS1 and VSS2, respectively, are coupled via two similar diodes. To be done. Each of these diodes has a predetermined breakdown voltage, and a high voltage applied between the bonding pad PA1 and each power supply voltage supply terminal or ground potential supply terminal or between each power supply voltage supply terminal and ground potential supply terminal. Acts to absorb.

Similarly, in the periphery of the semiconductor layers DA20 to DA40, 4 are provided so as to surround them and face each other.
Semiconductor layers DA21 to DA24 to DA41 to DA
44 (first semiconductor layer) are respectively formed. Of these, the semiconductor layers DA21 and DA22 are not particularly limited, but are coupled to the power supply voltages VCC1 and VCC2, respectively, and the semiconductor layers DA23 and DA24 are connected to the ground potential VSS.
1 and VSS2 respectively. The semiconductor layers DA31 and DA32 are coupled to the power supply voltage VCC1 and the ground potential VSS2, respectively, and the semiconductor layers DA33 and DA34 are coupled to the ground potential VSS1 and the power supply voltage VCC2, respectively. Further, the semiconductor layers DA41 and D
A42 is coupled to the power supply voltage VCC1 and the ground potential VSS1, respectively, and the semiconductor layers DA43 and DA44 are coupled to the power supply voltage VCC2 and the ground potential VSS2, respectively.

As a result of these, the bonding pad PA3
~ PA4 is connected to the power supply voltage VCC via two diodes which are connected in series and whose anodes are commonly coupled.
1 and VCC2 and ground potentials VSS1 and VSS2
Via the same two diodes, respectively, between the power supply voltage VCC1 and the power supply voltage VCC2 and the ground potential VSS2, the ground potential VSS1 and the power supply voltage VCC2.
And the ground potential VSS2, between the power supply voltage VCC1 and the ground potential VSS2 and the power supply voltage VCC2, and the ground potential V
Between SS1 and ground potential VSS2 and power supply voltage VCC2, between power supply voltage VCC1 and ground potentials VSS1 and VSS2
And the power supply voltage VCC2 and the ground potentials VSS1 and VSS2, respectively. Similarly, these diodes each have a predetermined breakdown voltage, and between the corresponding bonding pads PA2 to PA4 and each power supply voltage supply terminal or ground potential supply terminal or between each power supply voltage supply terminal and ground potential supply terminal. To absorb the high voltage applied in a predetermined combination.

By the way, in this embodiment, as is apparent from FIG. 2, the semiconductor layers DA11 to DA14 to DA41 to DA44 included in four adjacent electrostatic protection circuits are intentionally arranged so as to face each other in different combinations. It is formed by changing the order. That is, for example, between the two electrostatic protection circuits corresponding to the bonding pads PA1 and PA2, the semiconductor layer DA coupled to the ground potential VSS1 is provided.
12 and semiconductor layer DA21 coupled to power supply voltage VCC1
Have a facing portion, and the semiconductor layer DA13 coupled to the power supply voltage VCC2 and the semiconductor layer DA24 coupled to the ground potential VSS2 have a facing portion. Further, between the two electrostatic protection circuits corresponding to the bonding pads PA2 and PA3, the semiconductor layer DA2 coupled to the power supply voltage VCC2 is provided.
2 and semiconductor layer DA31 coupled to power supply voltage VCC1 have opposing portions, and semiconductor layer DA23 coupled to ground potential VSS1 and semiconductor layer DA34 coupled to power supply voltage VCC2 have opposing portions. Further, between the two electrostatic protection circuits corresponding to the bonding pads PA3 and PA4, the semiconductor layer DA3 coupled to the ground potential VSS2 is provided.
2 and semiconductor layer DA41 coupled to power supply voltage VCC1 have opposing portions, and semiconductor layer DA33 coupled to ground potential VSS1 and semiconductor layer DA44 coupled to ground potential VSS2 have opposing portions.

As a result, by the combination of the facing portions, between the power supply voltage VCC1 and the ground potential VSS1,
Between power supply voltage VCC1 and power supply voltage VCC2, between power supply voltage VCC1 and ground potential VSS2, ground potential VSS1
And the power supply voltage VCC2, the ground potential VSS1 and the ground potential VSS2, and the power supply voltage VCC2 and the ground potential VSS2 are further coupled through an electrostatic protection element having a relatively small breakdown voltage, The electrostatic breakdown voltage between the corresponding power supply voltage supply terminal and ground potential supply terminal is increased. The combination of the facing portions is repeated in units of four adjacent electrostatic protection circuits, whereby approximately the same number of electrostatic protection elements are provided between each power supply voltage supply terminal and the ground potential supply terminal. ..

Needless to say, the electrostatic protection circuit is formed with a sufficiently small layout area as compared with the case where the electrostatic protection circuit used in the conventional dynamic RAM or the like is combined. Further, by forming these electrostatic protection circuits with a sufficiently small required layout area, an increase in input / output capacitance coupled to each signal terminal is suppressed. As a result, the chip area of the large scale integrated circuit is reduced and the signal transmission delay time is reduced.

3 to 7 are cross-sectional views of the electrostatic protection circuit included in the large-scale integrated circuit LSI of FIG. 2 taken along the line AB of the first to fifth embodiments, respectively. The cross-sectional structure and characteristics of the electrostatic protection circuit of the large-scale integrated circuit will be described with reference to these drawings. Since the embodiment of FIGS. 4 to 7 basically follows the embodiment of FIG. 3, only the parts different from this will be described.

In FIG. 3, the bonding pad PA1
The semiconductor layer DA10 provided corresponding to is formed of an N-channel type diffusion layer formed on the surface of the P-channel type semiconductor substrate SUB. As described above, this diffusion layer is coupled to the corresponding bonding pad PA1 via the aluminum wiring layer, and further the corresponding well resistance W.
It is coupled to one electrode of R1.

On the other hand, the semiconductor layer DA13 is the semiconductor substrate S.
It is composed of an N-channel type buried layer formed in advance on the UB surface and an N-channel type diffusion layer formed on the buried layer. The buried layer forming the semiconductor layer DA13 is formed so as to be buried under the diffusion layer corresponding to the semiconductor layer DA10. The diffusion layer forming the semiconductor layer DA13 is connected to the power supply voltage VC via the aluminum wiring layer.
A predetermined insulating layer, that is, Locos L, is coupled between C2 and the diffusion layer corresponding to the semiconductor layer DA10.
OCOS is provided. Thereby, the semiconductor layer DA10
And DA13, a planar facing portion that separates the locos LOCOS is formed, and an facing portion in the interlayer direction with a buried layer is formed.

Similarly, the semiconductor layer DA14 includes an N-channel type buried layer formed in advance on the semiconductor substrate SUB surface,
It is composed of an N channel type diffusion layer formed on the buried layer. The buried layer forming the semiconductor layer DA14 is formed so as to be buried under the diffusion layer corresponding to the semiconductor layer DA10. The diffusion layer forming the semiconductor layer DA14 is connected to the ground potential V via the aluminum wiring layer.
Another locos LOCOS, which is coupled to SS2, is provided between this diffusion layer and the diffusion layer corresponding to the semiconductor layer DA10.
Is provided. Thereby, the semiconductor layers DA10 and DA
Between 14 is formed a planar facing portion that separates the locos LOCOS, and at the same time an interlayer facing portion is formed via the buried layer.

By the way, in the electrostatic protection circuit of this embodiment, the buried layer and the semiconductor layer DA corresponding to the semiconductor layer DA13 are formed.
The buried layer corresponding to 14 is opposed to the buried layer of P-channel type formed in advance on the semiconductor substrate SUB. Therefore, the breakdown voltage between the semiconductor layers DA13 and DA14 is made relatively small, which causes the power supply voltage VC.
The electrostatic protection characteristic between C2 and the ground potential VSS2 is enhanced.

In the embodiment shown in FIG. 4, the semiconductor layer DA1 is used.
The buried layer corresponding to 3 faces the buried layer corresponding to the semiconductor layer DA14 via the semiconductor substrate SUB having a relatively low conductivity. Therefore, the breakdown voltage between the semiconductor layers DA13 and DA14 becomes larger than that in the embodiment of FIG.

Next, in the embodiment of FIG. 5, the semiconductor layer DA1
The N-channel type diffusion layer corresponding to 0 is coupled to the buried layer formed thereunder, and further faces the buried layers corresponding to the semiconductor layers DA13 and DA14 via the P-channel type buried layer, respectively. .. Therefore, the semiconductor layer DA10
Also, the breakdown voltage between DA13 and DA14 is made smaller than that in the embodiment of FIG. 2, which further enhances the electrostatic protection characteristics between the bonding pad PA1 and the power supply voltage VCC2 and the ground potential VSS2.

On the other hand, in the embodiment of FIG. 6, the semiconductor layer DA1
The buried layer corresponding to 0 faces the buried layers corresponding to the semiconductor layers DA13 and DA14 via the semiconductor substrate SUB having a relatively low conductivity. Therefore, the breakdown voltage between the bonding pad PA1 and the semiconductor layers DA13 and DA14 is larger than that in the embodiment shown in FIG. 5, but is smaller than that in the embodiment shown in FIGS.

Further, in the embodiment of FIG. 7, the portion corresponding to the semiconductor layer DA10 of FIG. 2 is divided into three parts with the Locos LOCOS being separated, and a contact is provided corresponding to each of these semiconductor layers. As a result, in the electrostatic protection circuit of this embodiment, the three semiconductor layers obtained by dividing the semiconductor layer DA10 can be coupled to the bonding pad PA1 or other power supply voltage or ground potential in any combination, and the static electricity can be reduced. It is possible to realize various variations of the electric protection circuit.

FIG. 8 shows an equivalent circuit diagram of an embodiment of the electrostatic protection circuit included in the large scale integrated circuit LSI of FIG. The equivalent circuit of the electrostatic protection circuit of the large-scale integrated circuit of this embodiment and its characteristics will be described with reference to FIG.
The following description will proceed with the bonding pad PA1 and the corresponding electrostatic protection circuit as an example.

In FIG. 8, the bonding pad PA1
Are coupled to the semiconductor layer DA10 via the aluminum wiring layer and further coupled to one electrode of the well resistance WR1 as described above. The other electrode of the well resistance WR1 is coupled to the drain of the N-channel MOSFET M1 and further coupled to the input terminal of the input buffer IAB1. The gate and source of MOSFET M1 are commonly coupled and further coupled to ground potential VSS1. As a result, the MOSFET M1 is in the diode form with its cathode electrode facing the bonding pad PA1.
It acts to absorb the negative high voltage applied to the bonding pad PA1.

The bonding pad PA1 further has a semiconductor substrate SUB, that is, a substrate potential V, via a parasitic diode D0 having the N-channel type semiconductor layer DA10 as a cathode and the P-channel type semiconductor substrate SUB as an anode.
The power supply voltage VCC1, the ground potential VSS1, and the power supply voltage V1 are coupled via four parasitic diodes D1 to D4 that are coupled to the BB and have the semiconductor substrate SUB as an anode and the N-channel semiconductor layers DA11 to DA14 as a cathode.
CC2 and ground potential VSS2, respectively. The power supply voltage VCC1 is coupled to the ground potential VSS1 via two parasitic diodes D12 that are connected in series so that their anodes are commonly coupled, and the ground potential VSS1.
Is further coupled to the power supply voltage VCC2 via a similar parasitic diode D23. The power supply voltage VCC2 is
It is coupled to the ground potential VSS2 via the parasitic diode D34, and this ground potential VSS2 is connected to the parasitic diode D14.
To the power supply voltage VCC1.

The parasitic diodes D0 and D1 to D4 and D12, D14, D23 and D34 each have a predetermined breakdown voltage, and the bonding pad PA1 is provided.
And power supply voltage VCC1 or VCC2 or ground potential VS
It acts to absorb a high voltage applied between S1 or VSS2 and between the power supply voltage supply terminal and the ground potential supply terminal. As a result, in the large-scale integrated circuit LSI of this embodiment, the electrostatic power between each bonding pad, that is, each signal terminal and each power supply voltage supply terminal or ground potential supply terminal is increased even though the power supply system is made plural. The breakdown voltage is improved, and the electrostatic breakdown voltage between the power supply voltage supply terminal and the ground potential supply terminal is also improved.

FIG. 9 is a connection diagram of an embodiment of the electrostatic protection circuit included in the large scale integrated circuit LSI of FIG. With reference to the figure, the connection form and characteristics of the electrostatic protection circuit of the large scale integrated circuit of this embodiment will be described. In addition,
In the following description, the bonding pad PA1 of the internal logic circuit LC1 and the bonding pad P of the internal logic circuit LC2 will be described.
Two electrostatic protection circuits provided corresponding to B1 will be taken as an example.

In FIG. 9, the large-scale integrated circuit LSI of this embodiment has the internal logic circuit LC1 which uses the power supply voltage VCC1 and the ground potential VSS1 as the operating power supply, as described above.
An internal logic circuit LC2 using the power supply voltage VCC2 and the ground potential VSS2 as operating power supplies. The bonding pad PA1 is included in the internal logic circuit LC1, and the corresponding semiconductor layers DA10 to DA14 of the electrostatic protection circuit are formed in the region of the internal logic circuit LC1. Therefore, the semiconductor layer D
A11 and DA12 are supplied with a power supply voltage V from a power supply voltage bus or a ground potential bus in the area through a relatively short power supply wiring.
CC1 and ground potential VSS1 are supplied, but different internal logic circuits LC2 are provided to the semiconductor layers DA13 and DA14.
The power supply voltage VCC2 and the ground potential VSS2 are supplied from the power supply voltage bus or the ground potential bus in the region of (1) through a relatively long power supply wiring.

On the other hand, the bonding pad PB1 is included in the internal logic circuit LC2, and the corresponding semiconductor layers DB10 to DB14 of the electrostatic protection circuit are formed in the region of the internal logic circuit LC2. Therefore, the semiconductor layers DB13 and DB
14 is supplied with the power supply voltage VCC2 and the ground potential VSS2 from the power supply voltage bus or the ground potential bus in the region through a relatively short power supply wiring.
B12 is supplied with a power supply voltage VCC1 and a ground potential VSS1 from a power supply voltage bus or a ground potential bus in different regions of the internal logic circuit LC1 through a relatively long power supply wiring.

As a result, in this embodiment, the required layout area of the power supply wiring for coupling the power supply voltage bus or the ground potential bus formed in the region of the internal logic circuit different from each semiconductor layer is increased, There is a drawback that the chip area of a large scale integrated circuit is rather large.

FIG. 10 is a connection diagram of the second embodiment of the electrostatic protection circuit included in the large scale integrated circuit LSI to which the present invention is applied. Since the large-scale integrated circuit of this embodiment supplements the drawback while basically following the embodiment of FIG. 9, description will be added only to parts different from this.

In FIG. 10, the large-scale integrated circuit LSI of this embodiment has an internal logic circuit LC1 having power supply voltages VCC1 and VSS1 as operating power supplies, and an internal logic circuit LC2 having power supply voltages VCC2 and VSS2 as operating power supplies. An internal logic circuit LC3 having power supply voltages VCC3 and VSS3 as operating power supplies. In this embodiment, the power supply voltage V
CC1 to VCC3 and power supply voltage supply terminals and ground potential supply terminals for supplying the ground potentials VSS1 to VSS3 are commonly coupled to each other outside the package of the large-scale integrated circuit LSI to supply power supply voltages VCC1 to VCC3 and ground potentials VSS1 to VSS1. VSS3
Are set to the same potential.

The internal logic circuit LC1 includes a semiconductor layer DA1.
0 (second semiconductor layer) and semiconductor layers DA11 and DA12
A plurality of electrostatic protection circuits including three semiconductor layers represented by (first semiconductor layer) are provided. Of these, the semiconductor layer DA10 is the bonding pad PA1 not shown.
Be combined with. Further, the semiconductor layer DA11 is supplied with the power supply voltage VCC1 from the power supply voltage bus provided in the region through the relatively short power supply wiring, and the semiconductor layer DA12 is relatively short from the ground potential bus provided in the region. The ground potential VSS1 is supplied through the power supply wiring.

On the other hand, in the internal logic circuit LC2, the semiconductor layer DB10 (second semiconductor layer) and the semiconductor layers DB11 and D are provided.
A plurality of electrostatic protection circuits including three semiconductor layers represented by B12 (first semiconductor layer) are provided. this house,
The semiconductor layer DB10 is coupled to a bonding pad PB1 (not shown), and the semiconductor layers DB11 and DB12 have power supply voltage VCC2 and ground potential VSS2 from the power supply voltage bus or the ground potential bus provided in the region through a relatively short power supply wiring. Is supplied. Similarly, the internal logic circuit LC3 includes a plurality of electrostatic protection layers including three semiconductor layers represented by a semiconductor layer DC10 (second semiconductor layer) and semiconductor layers DC11 and DC12 (first semiconductor layer). A circuit is provided. Of these, the semiconductor layer DC10 is coupled to a bonding pad PC1 (not shown),
11 and DC12 are respectively supplied with a power supply voltage VCC3 and a ground potential VSS3 from a power supply voltage bus or a ground potential bus provided in the region through a relatively short power supply wiring.

The internal logic circuits LC1 to LC3
Has a number of similar electrostatic protection circuits, as described above,
The first semiconductor layers forming these electrostatic protection circuits are formed so as to face each other in different combinations including the adjacent electrostatic protection circuits. However, in the large-scale integrated circuit LSI of this embodiment, the electrostatic protection circuit provided in each region causes the bonding pad, that is, the signal terminal provided in each region, between the corresponding power supply voltage or ground potential and the power supply voltage. The electrostatic breakdown voltage between the ground potential and the ground potential is increased.

In this embodiment, the internal logic circuit LC1
Power supply voltage VCC1 and the power supply voltage V2 of the internal logic circuit LC2
A diode pair DS2 in which two diodes are connected in parallel in opposite directions is provided between CC2 and CC2, and a similar diode pair DS1 is provided between ground potential VSS1 and ground potential VSS4. .. Similarly, the power supply voltage VCC1 of the internal logic circuit LC1 and the internal logic circuit LC3
A diode pair DS5 is provided between the ground potential VSS1 and the ground potential VSS3, and a diode pair DS6 is provided between the ground potential VSS1 and the ground potential VSS3. Further, the power supply voltage VCC2 of the internal logic circuit LC2 and the internal logic circuit LC
The diode pair DS3 is connected between the power supply voltage VCC3 of 3 and
And a diode pair DS4 is provided between the ground potential VSS2 and the ground potential VSS3. The diode pairs DS1 to DS6 have a predetermined breakdown voltage and act to absorb a high voltage applied between the power supply voltage supply terminals of the same potential or between the ground potential supply terminals.

By the way, the diode pairs DS1 to DS6 are coupled to a corresponding pair of power supply voltage buses or ground potential buses via a relatively thick power supply wiring. Therefore, in the large-scale integrated circuit of this embodiment, the required layout area of the power supply wiring can be reduced and the chip area thereof can be reduced, and at the same time, the electrostatic breakdown voltage between the power supply voltage or the ground potential of different power supply systems can be improved. Become.

As shown in the above embodiments, the present invention is applied to a dynamic RAM having a plurality of power supply systems.
When it is applied to a large-scale integrated circuit such as, the following effects can be obtained. That is, (1) the electrostatic protection circuit of a large-scale integrated circuit such as a dynamic RAM having a plurality of power supply systems, the first semiconductor layer provided corresponding to each signal terminal, and the power supply voltage supply of each power supply system. Between the signal terminal and each power supply system by basically configuring a plurality of second semiconductor layers that are provided so as to correspond to the terminals and the ground potential supply terminal and surround the first semiconductor layer and are formed so as to face each other. In addition, it is possible to form an electrostatic protection circuit that can cope with electrostatic breakdown between different power supply systems with a relatively small required layout area.

(2) In the above item (1), when the use area of each power supply system is limited, the electrostatic protection circuit is provided with the first semiconductor layer, the power supply voltage supply terminal and the ground potential of the corresponding use area. A second semiconductor layer, which is basically configured with a second semiconductor layer provided corresponding to the supply terminal and is provided corresponding to the power supply voltage supply terminal or the ground potential supply terminal having the same potential and formed in different use regions. By connecting the two via a diode pair, both power supply voltage supply terminals or ground potential supply terminals of the same potential in different usage areas can be bidirectionally connected without providing many power supply wirings, and electrostatic discharge between each power supply system can be achieved. The effect that the breakdown voltage can be increased can be obtained. (3) According to the above items (1) and (2), the increase of the input / output capacitance of each signal terminal is suppressed and the increase of the layout area of the power supply wiring is suppressed. In other words, the signal transmission delay time is shortened to reduce the chip area. It is possible to obtain an effect that the electrostatic breakdown voltage of a large-scale integrated circuit having a plurality of power supply systems can be improved while reducing the voltage.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, power supply voltages VCC1 and VCC2 supplied as operation power supplies to the internal logic circuits LC1 and LC2.
May be at different potentials. In this embodiment, the bonding pads arranged along the upper side or the lower side of the semiconductor substrate SUB are, for example, LOC (Lead On Ch).
ip) As in the case of adopting the package method, they can be arranged in a line at the center of the semiconductor substrate SUB. In FIG. 2, semiconductor layers DA10 to DA14 to DA40 to
The shape of the DA 44 or the like is not restricted by this embodiment, and the combination of the facing portions is arbitrary. Second
The number of first semiconductor layers provided around the semiconductor layer of
It changes according to the number of power supply systems of large-scale integrated circuit LSI,
The layout form of each semiconductor layer also changes accordingly.
The constituent elements of the electrostatic protection circuit and the connection form thereof can take various embodiments. The specific cross-sectional structure of the electrostatic protection circuit shown in FIGS. 3 to 7 is not restricted by these embodiments. In FIG. 10, a plurality of diode pairs in a serial form or a parallel form may be provided between each power supply voltage bus and between the ground potential buses.

In the above description, the case where the invention made by the present inventor is mainly applied to a large-scale integrated circuit such as a dynamic RAM which is a field of application which is the background of the invention has been described, but the invention is not limited thereto. Instead, it can be widely applied to various semiconductor devices having at least a plurality of power supply systems.

[0052]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an electrostatic protection circuit of a large-scale integrated circuit such as a dynamic RAM having a plurality of power supply systems, a first semiconductor layer provided corresponding to each signal terminal, a power supply voltage supply terminal of each power supply system, and a ground. It basically comprises a plurality of second semiconductor layers which are provided corresponding to the potential supply terminals and surround the first semiconductor layer and are formed so as to face each other. In addition, when the use area of each power supply system is limited, the electrostatic protection circuit is provided with the first semiconductor layer and the second protection layer provided corresponding to the power supply voltage supply terminal and the ground potential supply terminal of the corresponding use area. A semiconductor layer is basically formed, and second semiconductor layers provided corresponding to a power supply voltage supply terminal or a ground potential supply terminal having the same potential and formed in different use regions are bidirectionally coupled through a diode pair. This makes it possible to form an electrostatic protection circuit that can cope with electrostatic breakdown between the signal terminal and each power supply system and between different power supply systems with a relatively small layout area.
In addition, when the use area of each power supply system is limited, the power supply voltage supply terminals or the ground potential supply terminals of the same potential are bidirectionally coupled without providing many power supply wirings, and electrostatic discharge between each power supply system is performed. The breakdown voltage can be increased. As a result, a plurality of power supply systems are provided while suppressing an increase in the input / output capacitance of each signal terminal and suppressing an increase in the layout area of the power supply wiring, in other words, reducing the signal transmission delay time and the chip area. It is possible to improve the electrostatic breakdown voltage of a large-scale integrated circuit such as a dynamic RAM.

[Brief description of drawings]

FIG. 1 is a board layout diagram showing an embodiment of a large scale integrated circuit to which the present invention is applied.

FIG. 2 is a partial enlarged layout view showing an embodiment of the large scale integrated circuit of FIG.

3 is a cross-sectional structural view taken along line AB of the first embodiment of the electrostatic protection circuit included in the large scale integrated circuit of FIG.

FIG. 4 is a cross-sectional structural view taken along line AB of a second embodiment of the electrostatic protection circuit included in the large scale integrated circuit of FIG.

5 is a cross-sectional structural view taken along line AB of a third embodiment of the electrostatic protection circuit included in the large scale integrated circuit of FIG.

6 is a cross-sectional structural view taken along the line AB of a fourth embodiment of the electrostatic protection circuit included in the large scale integrated circuit of FIG.

7 is a cross-sectional structural view taken along line AB of the fifth example of the electrostatic protection circuit included in the large-scale integrated circuit of FIG.

8 is an equivalent circuit diagram showing an embodiment of an electrostatic protection circuit included in the large scale integrated circuit of FIG.

9 is a connection diagram showing a first embodiment of an electrostatic protection circuit included in the large-scale integrated circuit of FIG.

FIG. 10 is a connection diagram showing a second embodiment of an electrostatic protection circuit included in a large scale integrated circuit to which the present invention is applied.

[Explanation of symbols]

LSI ... Large-scale integrated circuit, SUB ... Semiconductor substrate, LC1 to LC3 ... Internal logic circuit, PA1 to PA
m, PB1 to PBm, PVC1A to PVC1B, PVS
1A to PVS1B, PVC2A to PVC2B, PVS2
A to PVS2B ... Bonding pad. DA10
DA14 to DA40 to DA44, DB10 to DB1
4, DC10 to DC12 ... Semiconductor layer, WR1 to WR
4 ... Well resistance, M1 to M4 ... N channel M
OSFET, S1 to S4 ... Source region, D1 to D4
... Drain region, G1 to G4 ... Gate layer. D0
~ D4, D12, D14, D23, D34 ... Diodes. DS1 to DS6 ... Diode pairs.

Claims (5)

[Claims] 1. A plurality of power supply voltage supply terminals and a ground potential supply terminal which are provided corresponding to each of the power supply systems, and each of the power supply voltage supply terminal and the ground potential supply terminal. And a static electricity protection circuit including a plurality of first semiconductor layers that are formed so as to face each other. 2. The semiconductor device comprises a plurality of signal terminals for inputting or outputting a predetermined signal, and a plurality of second semiconductor layers provided corresponding to each of the signal terminals. The electrostatic protection circuit is provided corresponding to each of the second semiconductor layers, and the plurality of first semiconductor layers are adjacent to each other so as to surround the corresponding second semiconductor layer. 2. The semiconductor device according to claim 1, wherein the semiconductor devices are formed so as to face each other in different combinations, including those constituting the electrostatic protection circuit. 3. The semiconductor device comprises a plurality of internal logic circuits using each of the power supply systems as operating power supplies, and the electrostatic protection circuit has internal logic using the corresponding power supply systems as operating power supplies. Wirings formed in the circuit region for connecting each of the power supply voltage supply terminal and the ground potential supply terminal to the corresponding first semiconductor layer are provided between the plurality of internal logic circuits. Claim 1 or Claim 2 characterized in that they are routed to each other.
Semiconductor device. 4. A plurality of internal logic circuits having a plurality of power supply systems, each of which uses the power supply system as an operating power supply,
A plurality of power supply voltage supply terminals and ground potential supply terminals provided corresponding to each of the power supply systems, and a corresponding power supply system provided corresponding to each of the power supply voltage supply terminals and the ground potential supply terminals as an operating power supply. A plurality of first semiconductor layers formed so as to face each other in the region of the internal logic circuit, and a plurality of first semiconductor layers formed corresponding to the power supply voltage supply terminals, respectively, formed in the regions of different internal logic circuits. A plurality of diode pairs provided corresponding to each of the first semiconductor layers or to each of the ground potential supply terminals and provided between a plurality of first semiconductor layers formed in different regions of the internal logic circuit. A semiconductor device characterized by. 5. The semiconductor device according to claim 4, wherein the plurality of power supply voltage supply terminals are supplied with the same power supply voltage.