JPH05291500A - Compound semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce an area occupied by a large capacitance capacitor without lowering the yield of devices. CONSTITUTION:A first insulating layer 2. a compound semiconductor layer 3, a second insulating layer 4, and an operation layer 5 are successively laminated on a compound semiconductor substrate 1, and a hole 7 is formed in the operation layer 5 and the second insulating layer for exposing the compound semiconductor layer 3. An ohmic electrode 9a is formed on the exposed compound semiconductor layer 3, and at least one or more FETs are formed on the operation layer 5. Further, a wiring metal 10 is formed on the ohmic electrode 9a and on an FET source electrode 9b to interconnect the ohmic electrode 9a and the FET source electrode 9b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an analog IC for ultra high frequency.
The present invention relates to a compound semiconductor integrated circuit used for the above.

[0002]

2. Description of the Related Art Generally, a GaAs analog IC (MMI
The self-bias method is often used as the bias circuit of C). As a bypass condenser used for this,
A large capacity capacitor of about 1000 pF is required.

Conventionally, as such a large-capacity capacitor, an external chip capacitor has been used, or an MIM capacitor has been used for integration. MIM
The capacitor means the first metal (Ti, Pt and Au).
Etc.) CVD of p-type SiN film with a dielectric constant of about 7
This is a capacitor in which a film is grown to a thickness of 2000 Å and a second metal is deposited on the film. FIG. 4 shows a circuit diagram of a GaAs analog IC using this MIM capacitor. In the figure, 33 is a GaAsFET, the gate electrode of the GaAsFET 33 is connected to the input terminal 34, the drain electrode is connected to the output terminal 35, and the source electrode is grounded via the resistor 31. There is. The source electrode of the GaAsFET 33 is connected to the other end of the capacitor 32, one end of which is connected to the ground. Furthermore, the input terminal 34 and the GaAsFET 3
The other end of the resistor 31, one end of which was connected to the ground, was connected to the gate electrode of No. 3.

[0004]

However, in the above-mentioned conventional bypass capacitor using the MIM capacitor, although the accuracy of the capacitance is not particularly required,
Since a large capacitance is required, there is a problem that the element area must be large.

Of course, in order to reduce the element area, p-type S
Although the iN film may be thinned to increase the dielectric constant to increase the capacitance, this causes a problem that the first and second metals are short-circuited and the device yield is reduced.

The object of the present invention is to solve the above problems.
The present invention provides a compound semiconductor integrated circuit in which the area occupied by a large-capacity capacitor can be reduced without lowering the device yield.

[0007]

In order to achieve the above-mentioned object, the present invention comprises a compound semiconductor substrate on which a first insulating layer, a compound semiconductor layer, a second insulating layer, and an operating layer are sequentially laminated. A hole exposing the compound semiconductor layer is formed in the operating layer and the second insulating layer, an ohmic electrode is formed on the exposed compound semiconductor layer, and at least one or more holes are formed on the operating layer. FET is formed, and a wiring metal is formed on the ohmic electrode and the source electrode of the FET to connect the ohmic electrode and the source electrode of the FET.

[0008]

In the present invention, since the capacitor composed of the compound semiconductor substrate, the first insulating layer and the compound semiconductor layer is formed below the operating layer, a large capacity capacitor can be obtained without increasing the element area. Moreover, since the upper layer of the capacitor and the source electrodes of the plurality of FETs are connected,
The capacitor is shared by a plurality of FETs, reducing the device area. In addition, since the FET can be grounded at a high frequency in the immediate vicinity through the capacitor, the high frequency characteristics are improved.

[0009]

Embodiments of the compound semiconductor integrated circuit according to the present invention will be described below with reference to FIGS.

That is, referring to FIG. 1, the compound semiconductor integrated circuit has 2000 angstroms on an n + GaAs substrate 1.
Undoped GaAs layer (insulating layer) 2, 2000 angstroms n + GaAs layer 3, 5,000 angstrom undoped GaAs layer (insulating layer) 4, 2,000 angstroms thick n serving as an operating layer Type GaAs
Layers 5 are sequentially laminated. And n-type GaAs
A hole 7 reaching the surface of the n + GaAs layer 3 which is the upper layer of the capacitor is formed in a predetermined portion of the layer 5 and the undoped GaAs layer 4, and a groove 6 is also formed in the predetermined portion of the n-type GaAs layer 5 by recess etching. Are formed.
Further, an ohmic electrode 9a formed by alloying an ohmic metal on the bottom surface of the hole 7 and an source / drain electrode on both sides of the groove 6 on the n-type GaAs layer 5 are formed.
Mick electrode 9b is formed. A gate electrode 8 is formed on the bottom surface of the groove 6, and a wiring metal 10 is formed on the surface of the hole 7 including the ohmic electrode 9a and on the ohmic electrode 9b.

In the compound semiconductor integrated circuit shown in FIG. 2, an undoped GaAs layer 5a and an n-type GaAlAs layer 5 are used as an operation layer.
Hemto (H
The EMT structure is used, and this can dramatically improve the operation speed.

FIG. 3 is a circuit diagram of such a compound semiconductor integrated circuit. In the figure, the gate electrode of the GaAs FET 23a is connected to the input terminal 24, and the drain electrode is the capacitor-
22a. GaAs FET 23a source
The capacitor electrode has one end connected to the ground.
a and the other end of the resistor 21a are connected to each other. The input terminal 24 is connected to the ground via the resistor 21a, and the resistor 21a is also connected between the input terminal 24 and the capacitor 22a. Furthermore, GaAsFET2
The drain electrode of 3a and the gate electrode of GaAs FET 23b are connected via a capacitor 22a,
The drain electrode of the FET 23b is connected to the capacitor-22b, and the capacitor-22b is connected to the output terminal 25. The source electrode of the GaAsFET 23b is connected to the ground, the capacitor 22b connected to the capacitor 22a and the resistor 21a, and the resistor 21b. A resistor 21b is connected between the capacitor 22a and the output terminal 25.

In this way, according to this embodiment, since the capacitor composed of the n + GaAs substrate 1, the undoped GaAs layer 2 and the n + GaAs layer 3 is three-dimensionally formed below the operating layer, a large capacity capacitor is formed. Can be obtained without increasing the area it occupies. Moreover, since the upper layer of the capacitor is connected to the source electrodes of the two FETs, the capacitor is shared by the two FETs and the element area is 2
Reduce by 0%. Further, since the FET can be grounded in the high frequency in the immediate vicinity through the capacitor, the high frequency characteristics are improved.

[0014]

As described above, according to the present invention, a large-capacity capacitor can be obtained without increasing the element area, and since the capacitor is shared by a plurality of FETs, the device yield is reduced. The element area can be significantly reduced without any need. Further, since the FET can be grounded in the high frequency in the immediate vicinity through the capacitor, the high frequency characteristics can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a compound semiconductor integrated circuit of the present invention.

FIG. 2 is a cross-sectional view of another compound semiconductor integrated circuit of the present invention.

FIG. 3 is a circuit diagram of a compound semiconductor integrated circuit of the present invention.

FIG. 4 is a circuit diagram of a conventional compound semiconductor integrated circuit.

[Explanation of symbols]

 1 n + GaAs substrate 2, 4 undoped GaAs layer 3 n + GaAs layer 5 n-type GaAs layer (operating layer) 6 groove 7 hole 8 gate electrode 9a, 9b ohmic electrode 10 wiring metal

Claims (1)

[Claims] 1. A first insulating layer, a compound semiconductor layer, a second insulating layer, and an operating layer are sequentially stacked on a compound semiconductor substrate, and the compound semiconductor layer is formed on the operating layer and the second insulating layer. An exposed hole is formed, an ohmic electrode is formed on the exposed compound semiconductor layer, and at least one FET is formed on the operation layer. The ohmic electrode and the FET are formed. 2. A compound semiconductor integrated circuit characterized in that a wiring metal is formed on the source electrode of said FET to connect said ohmic electrode and the source electrode of said FET.