JPH05284003A - Output circuit - Google Patents

Abstract

PURPOSE:To satisfy the output level standard even when a device parameter or a power supply voltage is fluctuated. CONSTITUTION:Respective sources are set so as to make equal the output currents of current mirror circuits 8 and 10 in a standard state and to make the output current of the current mirror circuit 8 larger than that of the current mirror circuit 10 in the case of enlarging the driving ability of a transistor. Thus, when the driving ability of the transistor is large, only while an output terminal 2 is set at an H level, a transistor 12 for control drives a transistor 11 for current leakage is driven currents flow between the input and output of an inverter 4, the logical amplitude of the inverter 4 is decreased, and the driving ability of an output transistor 5 is limited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit manufactured by a CMOS process.

[0002]

2. Description of the Related Art Conventionally, for example, one shown in FIG. 2 has been used to realize an ECL level (logic level of an ECL logic circuit) output signal by an output circuit having a CMOS structure.
Since the output transistor 5 needs a very large driving capability to output the ECL level, the driving power thereof also needs a large value. Therefore, the inverters 3 and 4 are connected in series between the input terminal 1 and the output transistor 5 to increase the driving capability of the inverters 3 and 4 step by step.

[0003]

However, in such a conventional output circuit, since the drain of the output transistor is connected to the output terminal, when the device parameter or the power supply voltage fluctuates, the H level of the output is generated. (High level) When the fluctuation range becomes large and the device parameters and power supply voltage fluctuate in the direction that the driving capability of the device decreases,
If the drive capability of the output transistor is increased in order to maintain the H level standard of the output terminal, and the device parameters and the power supply voltage change in the direction of increasing the drive capability of the device, the H level standard of the output terminal will be exceeded. Had.

The present invention has been made in view of such circumstances, and is to satisfy the output level standard even if the device parameter or the power supply voltage changes.

[0005]

In order to solve such a problem, the present invention provides a current leakage transistor (11).
And a control transistor (12) and a current source (13)
A first current mirror circuit (8), a second current mirror circuit having the same polarity as the first current mirror circuit (9), and a third current mirror circuit having a reverse polarity to the first current mirror circuit. (10), the first diode array (6), and the second diode array (7) having a smaller number of components than the first diode array, and the current leakage transistor is a P-channel, and the source-drain is connected between the source and the drain. The control transistor is connected between the input / output terminals on the rear side of the cascaded CMOS inverters, and the control transistor controls ON / OFF between the gate and drain of the current leakage transistor, and the current source is the gate of the current leakage transistor 11. To supply a current to the first current mirror circuit and the first diode array are connected in series,
The second current mirror circuit and the second diode array are connected in series, the output of the second current mirror circuit is input to the third current mirror circuit, and the output of the first current mirror circuit and the third current The output of the mirror circuit is input to the gate of the control transistor.

[0006]

The variable element is detected by the characteristic imbalance of the diode arrays having different numbers of constituents, and the detected variable element is supplied to the current leakage transistor to control the gate voltage of the output transistor.

[0007]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In FIG. 1, the inverters 3 and 4 are connected in cascade, the input terminal 1 is connected to the input of the inverter 3, and the output of the inverter 4 is connected to the gate of the output transistor 5 and the source of the control transistor 12. Also,
The source of the output transistor 5 is grounded, and the drain is connected to the output terminal 2.

The diode array 6 having (n-1) diodes and the current mirror 8, and the diode array 7 having (m-1) diodes (m> n) and the current mirror 9 are the negative power source 15 respectively. And ground. The output of the current mirror 9 is connected to the input of the current mirror 10, and the output of the current mirror 8 and the output of the current mirror 10 are the control transistor 12
, The drain of the control transistor 12 is connected to the gate of the current leak transistor 11, the source and drain of the current leak transistor 11 are connected to the input and output of the inverter 4, respectively, and the current source 13 is It is connected between the drain of the control transistor 12 and the ground.

In the device constructed as described above, the output currents of the current mirror circuits 8 and 10 are equal in the standard state, and when the driving capability of the transistors is increased, the output current of the current mirror circuit 8 is the output current of the current mirror circuit 10. Set each parameter to be larger. As a result, when the driving capability of the transistor is large, the current leak transistor 11 is driven by the control transistor 12 only when the output terminal 2 is at the H level, and a current flows between the input and output of the inverter 4, so that the logical amplitude of the inverter 4 changes. Decreased,
The drive capability of the output transistor 5 is limited. The diode array 6 and the current mirror 8 have the same transistor size, and the diode array 7 and the current mirror 9 have the same transistor size.
When the number of diode stages and the transistor size of the diode arrays 6 and 7 are determined so that the output currents I _Da and I _Db of the current mirrors 8 and 10 have the same value I _D when the power supply voltage is standard, equation (1) (2) ) It becomes like a formula.

I _Da = aA (V _GSa −V _T ) ² = aA {(V _S / n _a ) −V _T ) ² ... (1) I _Db = bA (V _GSb −V _T ) ² = _{bA {(V S / n b} ) -V T) 2 ···· (2) where each parameter is as follows. V _T : threshold voltage A: constant V _S : absolute value of voltage of negative power supply a, b: coefficient of transistor size

[0011] Current [Delta] I _D of the current mirror 8 and 10 is as following equation (3). ΔI _D = ΔI _Da −ΔI _Db = aA {(V _S / n _a ) −V _T } ^2- bA {(V _S / n _b ) −V _T } ² (3)

Here, the partial differentiation of ΔI _D with respect to V _S and V _T is as follows. (∂ΔI _D / ∂V _S ) = 2A [(a / n _a ) {(V _S / n _a ) −V _T } − (b / n _b ) {(V _S / n _b ) −V _T }] = 2 (AI _D) ^{1/2 _{[{(a) 1/2 / n a}} } - {(b) 1/2 / n b}} ] _{··· (4) (∂ΔI D /} ∂V T) = 2A _{[-a {(V S / n a} ) -V T} + b {(V S / n b) -V T} = 2 (AI D) 1/2 {- (a) 1/2 + (b ) ^1/2 } (5)

Here, n _a , n _b , a, and b are set as follows. n _a > n _b (a / b)> n _a ² / n _b ²

For example, if n _a = 4 and n _b = 2 are set, the following is obtained. (A / b) = 8.54> (4/2) ² = 4 In this case, (∂ΔI _D / ∂V _S )> 0, (∂ΔI _D / ∂
V _T ) <0.

Since the power supply voltage is increased and the threshold voltage is decreased to increase the drive capability of the device, when the device parameter and the power supply voltage change are changed to increase the drive capability of the device, ΔI _D The sign is positive. Therefore, the control transistor 12 whose outputs are connected to the gates of the current mirrors 8 and 10 is turned on because the gate voltage becomes H level.

When the control transistor 12 is turned on by setting the current value of the current source 13 to a minute value, the gate-drain voltage of the current leakage transistor 11 becomes almost 0, and the current leakage transistor 11 is an inverter. 4 functions as a diode in which the anode is connected to the input side and the cathode is connected to the output side.

If ΔI _D is negative, the control transistor 1
Since 2 is turned off, the gate voltage of the current leakage transistor 11 becomes H level by the current source 13, and the current leakage transistor 11 is also turned off. Therefore, when the device parameters and the power supply voltage fluctuate in the direction of increasing the driving capability of the device, and when the output terminal becomes the H level, the current leakage transistor 11 is diode-connected and is connected between the input and output of the inverter 4. Since the leak current flows, the logical amplitude of the inverter becomes small, and the inverter 4
The driving ability of is reduced.

Therefore, each element may be adjusted so that the H level of the output terminal 2 falls within the standard.

[0019]

As described above, according to the present invention, the variable element is detected by the imbalance of the diode arrays having different diode connections, and the transistor connected between the input and the output of the inverter is detected based on the detected variable element. Since it is controlled so that the gate voltage of the output transistor is controlled, there is an effect that the H level of the output transistor does not exceed the standard value.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional device.

[Explanation of symbols]

 3, 4 Inverter 5 Output transistor 6, 7 Diode array 8, 9, 10 Current mirror circuit 11 Current leakage transistor 12 Control transistor

Claims (1)

[Claims] 1. An inverter comprising CMOSs is cascaded in at least two stages, and a P channel MOS is provided at the output thereof.
In a transistor-connected output circuit, a current leakage transistor (11), a control transistor (12), a current source (13), a first current mirror circuit (8), and a first current mirror circuit are provided. The second current mirror circuit having the same polarity (9), and the third current mirror circuit (1 having the opposite polarity to the first current mirror circuit (1)
0), a first diode array (6), and a second diode array (7) having a smaller number of components than the first diode array, and the current leakage transistor is a P-channel and has a source-drain region. The control transistor is connected between the input / output terminals on the subsequent stage side of the cascaded CMOS inverters, the control transistor controls on / off between the gate and the drain of the current leakage transistor, and the current source is the current leakage. A current is supplied to the gate of the transistor 11 for use, the first current mirror circuit and the first diode array are connected in series, and the second current mirror circuit and the second diode array are connected in series. And the output of the second current mirror circuit is input to the third current mirror circuit, An output circuit, wherein the output of the first current mirror circuit and the output of the third current mirror circuit are input to the gate of the control transistor.