JPH05282212A - Information processing equipment - Google Patents

Abstract

(57) [Summary] [Object] To provide an information processing apparatus capable of performing a test of an arbitrary buffer access pattern in a buffer used for pipeline processing by a test program without causing disturbance of the pipeline. .. [Structure] RAM section 20b and buffer control circuit 20
buffer device 20 including a and request generation circuit 10
a, a read control logic unit 10 including an order generation circuit 10b for issuing a test discard request, an address generation circuit 10c, a reaping wait state circuit 30, a positive logic input from the request generation circuit 10a, and the order generation circuit 10b. The AND circuit 30s that uses the logical product of the inverted logical inputs as the set input to the cut-off waiting state circuit 30, and the logical product of the positive logical input from the buffer control circuit 20a and the inverted logical input of the order generation circuit 10b, the cut-off waiting state circuit 30. AND circuit 20s which is used as a reset input to the.

Description

Detailed Description of the Invention

[0001]

The present invention relates to information processing technology,
In particular, the present invention relates to a technique suitable for an operation test or the like of a hardware configuring a buffer in an actual operating environment in an information processing apparatus of a pipeline control system having a buffer.

[0002]

2. Description of the Related Art LSI (Large Scale Integrated circui)
t), semiconductor parts such as RAM (Random Access Memory)
Various inspections such as a wafer inspection, a package (LSI or RAM alone) inspection, a package (board mounted) inspection, etc. are carried out for each production process until it is incorporated into an information processing apparatus. As a result, it is possible to suppress the carry-in of defective parts after the assembly of the device, which is the final step, as much as possible, and ensure the productivity of the device. Bringing the defects that occurred in the previous process to the subsequent process causes the production line to be confused, such as replacing the unit including the defective part in the process, replacing the defective part by returning to the previous process or discarding the unit including the defective part. Eventually, the assembly period of the device will increase and the cost will rise. In particular, the above is an important problem in a product such as an information processing device having a large number of parts.

In addition, because the inspection environment of semiconductor parts in the wafer and package states is different from the inspection environment in the equipment state and defects are extracted during the moving and assembling of the parts, the inspection after the completion of the equipment assembling before the customer shipment is performed. It is clear that is important. In general, as a product inspection after completion of device assembly of an information processing device, a marginal margin test such as temperature and voltage is performed in addition to a basic function test using various test programs.

In the product inspection after the completion of the device assembly of such an information processing device, high speed access (reading) is performed every cycle in accordance with the machine cycle of the information processing device having the pipeline function (time required to execute each stage of the pipeline). The operation test of the RAM used as the buffer of the information processing apparatus that repeats / write) becomes a particular problem. This is because a RAM having operating characteristics such as manufacturing variation of access time and operation failure at a specific access pattern is used near its limit performance in order to improve the performance of the information processing apparatus. As a RAM operation test, a random data test by a test program or an actual JOB under the OS, and a test for a specific access pattern by the test program are performed.

[0005]

In the above-mentioned prior art, it is difficult to test a buffer used for pipeline control with an arbitrary buffer access pattern by a test program, with reference to FIGS. 4 and 5 below. Shown in.

FIG. 4A shows a certain buffer access pattern. The vertical axis represents the buffer address, the horizontal axis represents the time (unit is a machine cycle), Wd in the graph is the initial value setting write, W ^ d is the initial value inversion write, R
d represents reading. FIG. 4 (b) is a pipeline chart for realizing FIG. 4 (a). The vertical axes D, A, L, E, P, and S represent each stage of the pipeline. Reading by buffer advance control is performed in the L stage, and buffer writing is performed in the S stage. In the D stage, instruction analysis is performed,
Address translation is performed in the A stage, instruction activation is performed in the E stage, and intermediate results of operations in the pipeline are stored in registers in the P stage. Further, the horizontal axis represents time as in FIG. 4A, and Wi / Ri (i = 0 to 3) in the graph respectively indicate writing / reading at the address i.

As shown in FIG. 4 (b), buffer access conflict occurs between the second R0 and the second W2, R2 and the third W2 instruction, so that the W2 instruction cannot be executed. Recognize. In addition, reading is the same as writing
When (execution) stage-synchronized microprogram control is performed, an execution stage for designating a reaping instruction corresponding to the read request is required, and as a result, execution of the read instruction requires multiple cycles.
It is clear from FIG. 5 that the buffer access of the cycle pitch becomes impossible.

An object of the present invention is to provide an information processing technique capable of executing a test of an arbitrary buffer access pattern in a buffer used for pipeline processing by a test program without causing disturbance of the pipeline. Especially.

[0009]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the information processing apparatus of the present invention is, in the pipeline control type information processing apparatus having a buffer, only reads data from the buffer and checks the parity of the read data, and outputs the data to the arithmetic unit or the like. It is provided with control means for issuing a read-only request that does not execute transfer, and instruction means capable of pipeline processing of one cycle pitch by issuing this read-only request in synchronization with the execution stage of the instruction. ..

[0011]

According to the information processing apparatus of the present invention described above, it is possible to create a test program capable of executing the reading / writing of the buffer in synchronization with the execution stage in the pipeline processing at a 1-cycle pitch. It is possible to perform a test aiming at the buffer access pattern of, and when a buffer access error occurs in the test, by performing a parity check of the read data, the RAM used to construct the buffer, etc. It is possible to accurately detect the hardware failure of and to prevent malfunction of a buffer in operation.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus which is an embodiment of the present invention will be described in detail below with reference to the drawings. Figure 1
FIG. 2 is a block diagram showing an example of the configuration of the information processing apparatus in the present embodiment, and FIG. 2 is a conceptual diagram showing an example of the configuration and operation of an example of instruction means included in the information processing apparatus, and FIG. FIG. 3 is a conceptual diagram showing an example of the operation of the information processing apparatus of this embodiment.

In FIG. 1, 10 is a read control logic unit, 20 is a buffer device, 30 is a reaping wait state circuit, and 10a, 10b, and 10c are request generation circuits for the read operation of the buffer device 20 ( Control means), order generation circuit, address generation circuit, 2
Reference numeral 0a is a buffer control circuit, 20b is a RAM section constituting a storage medium of the buffer device 20, and 20s and 30s are ANDs.
It is a circuit (control means).

A part of the input from the request generation circuit 10a to the buffer control circuit 20a is part of the AND circuit 30.
It becomes the "1" input of one of s, and the reaping waiting state circuit 3
It is a set input of 0 (set by "1"). In addition, the buffer control circuit 20 from the order generation circuit 10b
A part of the input to a is logically inverted and input to "0" in the other of the AND circuits 30s, and the reaping waiting state circuit 3
AND which is set input of 0 and opened on the path of the reset input (reset by "1") from the buffer control circuit 20a to the reaping waiting state circuit 30
The other side of the circuit 20s is also logically inverted and input as "0".

That is, when issuing an access request or the like from the order generation circuit 10b to the buffer control circuit 20a, the logical outputs of the AND circuit 30s and the reaping waiting state circuit 30 of the AND circuit 20s are both "0".
And otherwise, it is always "1".
Set by the normal request generation circuit 10a,
The set and reset states in the reaping wait state circuit 30 are not affected by the operation of the order generation circuit 10b at all.

An example of the operation of this embodiment will be described below.

When a normal request is issued from the request generation circuit 10a, AND circuits 30s and 20s.
Since the input from the order generation circuit 10b in "1" is "1", the request ("1") issued from the request generation circuit 10a passes through the AND circuit 30s, and the set signal ("1") of the reaping wait state circuit 30 is output. ), And thereafter the read completion signal is input to the buffer control circuit 20a.
From the AND circuit 20s to the cutting waiting state circuit 3
Until a reset signal (“1”) of 0 is input, execution of an instruction that requires the read data of the request is delayed.

On the other hand, when the read discard request ("1") is issued from the order generation circuit 10b, AN
The side of the order generation circuit 10b of the D circuit 30s is "0".
Since it is (logical inversion), set input from the AND circuit 30s to the reaping wait state circuit 30 is suppressed (“0”).
Therefore, the read data of the read discard request does not influence the execution of other instructions that refer to the reaping wait state circuit 30. Similarly, the reset signal input from the buffer control circuit 20a to the reaping waiting state circuit 30 via the AND circuit 20s at the time of completion of reading from the RAM unit 20b based on the read discard request from the order generation circuit 10b is also stored in the order generation circuit 10b. A of the side
Since the input to the ND circuit 20s is "0", it is suppressed, and the reaping waiting state circuit 30 does not malfunction.

FIG. 2A shows an example of the format of the instruction 100 in the E stage of the read discard request issued from the order generation circuit 10b, and FIG.
The pipeline chart of the said instruction is shown. Instruction 1
00 is an opcode field 101 indicating the type of instruction
And an index address field 102 for addressing, a base address field 103, and a displacement field 104 indicating a displacement from the address specified by the index address field 102 and the base address field 103. Then, whether the instruction 100 is a normal read request or a read discard request is identified by the bit pattern of the operation code field 101. In this embodiment, buffer read is assumed to be executed in the same S stage as buffer write.

FIG. 3 (b) is a pipeline when FIG. 3 (a), which is the same buffer access pattern as FIG. 4 (a), is realized by using an instruction by a read / write request issued from the order generation circuit 10b. It is a chart. It can be seen that an arbitrary buffer access pattern can be realized regardless of the buffer access pattern, because both reading and writing are synchronized with the E stage and are executed at the same stage at one cycle pitch.

As described above, according to the information processing apparatus of the present embodiment, the read / write test of the RAM section 20b of the buffer device 20 in the environment where the actual apparatus is in operation is subject to restrictions such as pipeline disturbance. Since it is possible to execute the test program at a 1-cycle pitch without receiving it, it is possible to accurately identify a defective component of the RAM section 20b in the buffer device 20 that was overlooked in the component level test and incorporated in the device. Can be extracted.

In the description of the above-mentioned embodiment, the read discard request is explained as one order of the read request. However, by suppressing the write of the buffer and performing the parity check of the data output after the buffer write address is determined. Is similarly feasible.

[0023]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, according to the information processing apparatus of the present invention, a test of an arbitrary buffer access pattern in a buffer used for pipeline processing can be accurately performed by a test program without causing disturbance of the pipeline. The effect of being able to do is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of the configuration of an information processing apparatus that is an embodiment of the present invention.

2A and 2B are conceptual diagrams showing an example of a configuration of an instruction unit included in the information processing apparatus and an example of a pipeline chart.

3A and 3B are conceptual diagrams showing an example of a buffer access pattern and an example of a pipeline chart.

4A and 4B are conceptual diagrams showing an example of a buffer access pattern and an example of a pipeline chart in the related art.

FIG. 5 is a flowchart showing an example of the operation of the conventional technique.

[Explanation of symbols]

 10 read control logic unit 10a request generation circuit 10b order generation circuit 10c address generation circuit 20 buffer device 20a buffer control circuit 20b RAM unit 20s AND circuit 30 reaping wait state circuit 30s AND circuit 100 instruction 101 opcode field 102 index address field 103 base address Field 104 displacement field

Claims (1)

[Claims] 1. A pipeline control type information processing device having a buffer, which only reads data from the buffer and checks a parity of the read data, and does not execute data transfer to an arithmetic unit or the like. It is provided with control means for issuing a read-only request and instruction means capable of pipeline processing of one cycle pitch by issuing this read-only request in synchronization with an instruction execution stage in pipeline processing. Information processing device.