JPH05281997A - Voice synthesizer - Google Patents

Abstract

PURPOSE: To provide an inexpensive voice synthesizer for synthesizing human voice from a coded parameter stored in a solid state element or inputted from the external. CONSTITUTION: The voice synthesizer 10 (12A, 12B) is controlled by a programmed microprocessor 19 and uses data coding and compression technique to reduce a data ratio. A coded parameter is used for controlling the reflection characteristic of a digital filter included in the synthesizer 10 and an output from the digital filter is applied to a digital/analog converter. Thereby the digital output from the filter is converted into a sound signal, which is sent to a conventional amplifier 20 and a speaker 5.

Description

Detailed Description of the Invention

The present invention relates to speech synthesizers, and more particularly to speech synthesizers that can be implemented using low cost integrated circuit devices.

Speech synthesizers are known in the prior art. An example of a conventionally known speech synthesizer is U.S. Pat. No. 3,803,358.
No. 4,092,495 and U.S. Patent Application Serial No. 901,393, assigned to the assignee of the present invention, filed April 28, 1978. Disclosed herein is a speech synthesizer that uses several integrated circuits in its construction. The integrated circuit includes a speech synthesis processor and two read-only memories and is described in detail herein. The speech synthesizer disclosed herein is described in connection with a home computer. However, one of ordinary skill in the art will recognize that the speech synthesizer disclosed in applications where verbal information or command response is required can be used.

The voice synthesizer described above is preferably implemented using standard field effect transistor large scale integration techniques such as P-channel MOS. In addition, it is desirable that the speech synthesizer be compatible with the control circuits it resides in in various electronic devices. Therefore, one object of the present invention is to implement a speech synthesizer using low cost large scale integrated circuit devices.

Another object of the present invention is to use the existing T in a speech synthesizer.
It is to make the logic level compatible with the TL circuit.
Yet another object of the invention is that the speech synthesizer uses coded speech parameters stored in solid state memory. Yet another object of the present invention is to enable a speech synthesizer to utilize coded speech parameters input from the outside via a controller.

The above objects are achieved as described below. The speech synthesizer is controlled by a suitably programmed microprocessor, preferably the central processing unit of a commercial or home computer. The speech synthesizer uses a data coded compression method to minimize the required data rate. The coded speech parameters are used to control the reflection characteristics of digital filters in the speech synthesizer. The output of the digital filter is applied to a digital-to-analog converter, which converts the digital output of the digital filter into an audio signal. The reconstructed audio signal is used as an input to conventional amplifier and speaker systems.

The novel features believed characteristic of the invention are set forth in the appended claims. However, the invention itself, and its preferred use, further objects and advantages will be best understood by reference to the following detailed description of the illustrated embodiments when read in connection with the accompanying drawings.

FIG. 1 is a front view of an audio module of the type embodying the present invention. The voice module comprises a case 1 enclosing an electronic circuit which is preferably mounted on an integrated circuit (not shown in this figure). Access slot 2 is also shown in which additional memory devices are located to aid the onboard memory circuitry. These circuits are coupled via pin connector 3 to a commercial or home computer, children's electronic toy, or other product requiring verbal command or information response. Of course, it will be appreciated by those skilled in the art that other connecting devices can be used if desired. FIG. 1 shows a speaker 5
An embodiment in which an audio module is connected to a home-use computer 4 including a pin connector 3 is shown. FIG. 2 illustrates the main blocks of the synthesizer, including the blocks within the computer required to operate the audio module: the central processing unit 19, the audio amplifier 20, the speaker unit 5.

Having described the appearance of the voice module, we first describe the modes in which the voice module operates, and then a block diagram and detailed logic diagram of an electronic circuit such as that used to implement the voice module of FIG. explain.

The voice module of this embodiment has two operation modes described below. However, it will be apparent to those skilled in the art that these modes of operation can be reduced in number or expanded or modified in capacity. As a matter of design choice, the voice module is provided with the following operating modes: The first mode, the Speak mode, uses coded voice parameters contained in the phrase read-only memory (ROM) in the voice module. The coding parameters are input to a speech synthesis processing (SSP) chip, where they are decoded and used to construct a time-dependent model of the speech track. A synthetic speech waveform is uttered using this model.

Second operation mode, external speech (Speak Extern
In al) mode, the coded audio parameters are provided from an external source such as the central processing unit (CPU) of a commercial or home computer. The coded speech parameters are input to a speech synthesis processing (SSP) chip via an input buffer where they are decoded and used to generate synthesized speech.

Referring again to the block diagram of the main parts constituting the disclosed embodiment of the speech synthesizer of FIG. 2, the electronic system of the disclosed speech module is divided into three main functional groups, one of which is the speech synthesis processing apparatus 10. Others are the control input / output package 11 and the read-only memories 12a and 12b. In the disclosed embodiment, the R integrated on two integrated circuit chips
With the exception of the OM function group 12, each of these main function groups is integrated on a separate integrated circuit chip. The coded voice parameters of the required voice output are stored in the ROM function group. In addition, other coded voice parameters are assigned to the voice module in a manner similar to that described in US patent application Ser. No. 003,449 filed January 15, 1979 assigned to the assignee of the present invention. Stored in another "dictionary module" connected to. These additional read-only memories are shown in dashed lines because they are not normally packaged in the device but are plugged into the voice module by the operator.

The speech synthesis processor 10 is interconnected with a read-only memory via a data path 15 and the data path 16 is connected to an input / output bus 18 via a control input / output circuit package 11.
Connected to. In the preferred embodiment, as will be seen below, the speech synthesis processor 10 includes a buffer capable of addressing a plurality of read-only memories so that the address of the coded speech parameter is the central processing unit of a home or commercial computer. It is sent by the (CPU) and sent to the read-only memories 12a and 12b by the voice synthesis processing device. Of course, a central processing unit with an appropriately sized buffer can send addresses to more than one read-only memory, so in one embodiment, directing input from the central processing unit directly to the read-only memory. You can

As will be seen below, the speech synthesis processing apparatus 1
0 synthesizes a human voice or another sound according to the frame of data stored in the read-only memories 12a, 12b, 13a, 13b. The speech synthesis processor uses a parameter interpolator of the type described in U.S. Patent Application Serial No. 901,394 filed April 28, 1978 assigned to the assignee of the present invention. US Patent Application Serial No. 901,394 is incorporated herein by reference. Speech synthesis processing device 1
0 was also assigned to the assignee of the present invention, May 12, 1978.
A digital filter of the type described in U.S. Patent Application Serial No. 905,328 filed in Japanese is used. U.S. Patent Application Serial No. 905,328 is hereby incorporated by reference. The following description of the voice module assumes that the reader has a basic understanding of the operation of the parameter interpolator and digital filter described in the above-mentioned patent application, and therefore the reader is Please read these patent applications before exploring the following detailed description of US Pat. As will be seen below, the speech synthesis processor 10 includes a digital-to-analog "DA" converter that converts the digital output of the digital filter into an analog signal capable of driving a voice amplifier and speaker device. The speech synthesis processor 10 also includes timing, control, data storage and data compression devices, which will be described in detail below.

FIG. 3 shows a control input / output circuit package.
Control input / output circuit is 3 inputs N with 3 open collectors
It is composed of AND gates 31, 32 and 33. These logic gates are similar to the SN74LS10 chip manufactured by Texas Instruments Incorporated of Dallas, Texas. Two of the inputs to NAND gate 31 are connected to Vss. The third input is address bit 15 (ADD15) from the central processing unit. Since two of its inputs are always high, NAND gate 31 acts essentially as an inverter and its output is ADD15.
(Bar). NAND gate 32 receives as its input the ADD 15 (bar) from the output of NAND gate 31,
Voice block energizing signal SBE, address bit 5 (A
DD5). Therefore, the output of NAND gate 32 is a function of SBE, ADD5, ADD15 (bar). This output is called write selection (WS) (bar) and is given to the voice synthesis processing device 10. The voice module receives 8-bit data via the bidirectional data bus 17 in response to a write selection command from the central processing unit. The NAND gate 33 receives as its input the ADD 15 (bar) from the output of the NAND gate 31 and the voice block energizing signal (SB
E) and the ADD given from the output of the NAND gate 32
It has 5 (bars). Therefore, the output of NAND gate 33 is a function of SBE, ADD5 (bar), ADD15 (bar). This output is called read selection (RS) and is sent to the voice synthesis processing device 10. A read select command from the central processing unit causes the voice module to output 8 units of data via the bidirectional data bus 17 and generate a status signal represented by the 8 units of data.

In addition, the speech synthesis processor requires an interrupt signal (IN) requesting the central processing unit attention to notify the central processing unit of any change in the state of the speech synthesis processing unit.
T) can be generated. The specific state changes that generate the interrupt (INT) signal are described in detail herein. Gate 34 has its input READY (bar)
The signal is inverted to provide the READY signal of the central processing unit. When READY is high, the central processing unit is locked to the synthesis processing unit 10 and becomes a dedicated processing unit of the synthesis processing unit 10.

4 and 5 form a composite block diagram of the speech synthesis processor 10. The voice synthesis processing device 10 has 6
4 are shown in block diagram form in detail, with the exception of one of them. The six main functional blocks are the timing block 20, ROM-CPU interface logic 21, parameter load, store and decode logic 2.
2, parameter interpolator 23, filter and excitation generator 2
4 and a digital-to-analog conversion output unit 25.
Hereinafter, these main functional blocks will be described in detail with reference to FIGS.

Referring again to FIGS. 4 and 5, ROM /
The CPU interface logic unit 21 is the synthesis processing device 10.
To read-only memories 12a, 12b and to a central processing unit (not shown). In this embodiment, the 8-bit bidirectional data bus 17 (D0-D7 is coupled to the inputs of the central processing unit and the FIFO buffer 2215, while addresses 1-8 (ADD1-ADD8) and instructions 0-1 (I0
The -I1) pin is connected to the ROMs 12a, 12b (ROMs 13a-13b if used). ROM /
The CPU interface logic unit 21 receives the address information from the central processing unit from the address register 213 via the address pins 1-8 and the read-only memories 12a and 12b.
Send to. The command register 210 stores a 3-bit command from the central processing unit, which is decoded by the command decoder 211. Command decoder 211 responds to six commands. A voicing (SPK) command that the synthesis processor accesses the data from the read-only memory and utters in response to the access.
Reset (RS that resets the synthesis processing device to the initial state
T) Command, 4 bits are received from the central processing unit on D4-D7 pins, and address register 213 and ADD1-AD are received.
A load address (LA) command that transfers the number of addresses to the read-only memory via the D8 pin, a read-branch (RB) command that causes the read-only memory to extract the contents of the current and subsequent addresses, and uses it as a branch address, A byte read (RDBY) that allows the central processing unit to access the data stored in the read-only memory via address pin 8 (ADD8) and data input / output register 212.
Decoder deactivation (DDI to the command / external voicing logic circuit 253)
S) signal, which disables (disables) the command decoder 211, and the central processing unit through D0-D7 to the FIFO buffer 2215,
External vocalization (SPKEXT) for inputting 8-bit data
There are 6 commands. When the synthesis processing device 10 starts speaking in response to the SPK command, the ROM interface logic unit 21 encounters the RST command or the gate 207.
In response to detecting an "energy equal to 15" code (see FIGS. 12-24), it continues to speak until it resets the talk latch 216. When the synthesis processing device 10 starts speaking in response to the SPKEXT command, the gate 2
07 detects an "energy equal to 15" code,
Or the buffer empty (BE) command is the FIFO state logic 223.
0 (see FIGS. 12-24) and in response continues to speak until the talk latch 216 is reset. As you will see below, "energy equal to 15"
A code is used as the last box of data in a box of data that produces a word, phrase or sentence. LA, RB, RD
The BY command is decoded by the command decoder 211, and R
It is re-encoded via OM control logic 217 and sent to read-only memory via instruction (I0-I1) pins.

The talk latch 216 is the decoded S
Set in response to PK or SPKEXT command, (1)
During power-on clear (PUC) that is automatically generated when the synthesizer is energized, (2) by the decoded RST command, (3) "energy equal to 15" in the frame of audio data.
Depending on the code, (4) B from the FIFO state logic 2230
It is reset by the E command. The TALKD output is a delayed output that allows all speech parameters to be input to the synthesizer before generation.

The parameter load, store and decode logic 22 is responsive to the RDBY command output to the selected read only memory via the instruction pin from the gate 2251 which has the data from the pin ADD8 as its input. 7-bit long parameter input register 205 for receiving serial data from read-only memory via voice load logic 2250. Coded parameter random access memory (RAM) 203 and condition decoder and latch 208 are connected to receive the data input to parameter input register 205. As will be seen below, each frame of audio data is input in a 3 to 6 bit portion to the random access memory (RAM) 203 via the parameter input register 205 in a coded format in which the frame is provisionally stored. Random access memory (RA
M) Each of the coded parameters stored in 203 is converted into a 10-bit parameter by the parameter read-only memory 202 and temporarily stored in the parameter output register 201.

As described in connection with FIG. 7, a box of data is entered into the parameter input register 205 in whole or in part depending on the length of the particular box being entered.
Conditional decoder and latch 208 repeats in response to a particular portion of the frame of data to set pitch equal to zero, energy equal to zero, old pitch, old energy latch. The function of these latches is described below in connection with FIGS. Various timing signals are used with the conditional decoder and latch 208 to control the interpolation gate 209.
The gate 209 is a parameter load enable signal which causes the interpolation to inhibit the signal, the zero parameter signal when zeroing the parameter, and in particular the data in the parameter input register 205 into the coded parameter random access memory 203. To occur.

The parameters in the parameter output register 201 are applied to the parameter interpolation function block 23.
The input K1-K10 voice parameters, including voice energy, are stored in the K stack 302 and E10 loop 304, while the pitch parameters are stored in the pitch register 305. The voice parameters and energy factor are applied to the array multiplier 401 in the filter and excitation generator 24 via recording logic 301. However, as will be seen below, when a new parameter is loaded into the parameter output register 201, it is not immediately inserted into the K stack 302 or E10 loop 304 or register 305, but rather into the K stack 302, E10 loop 304 or The corresponding value in register 305 goes through 8 interpolation cycles, during which K stack, E10 loop 30
4, or the portion of the difference between the current value in register 305 and the target value of the parameter in parameter output register 201 is added to the current value in K-stack 302, E10 loop 304 or register 305.

Basically, pitch energy and K1-K1
The same logic is used to perform the interpolation of 0 voice parameters. The target value from the parameter output register 201 is subtracted along with the current value of the corresponding parameter from the subtractor 308.
Is applied to. Selector 307 selects either the current pitch from pitch logic 306 or the current energy or K coefficient from KE10 transfer register 303, depending on which parameter is currently in parameter output register 201, and It is applied to the subtractor 308 and the delay circuit 309. As will be seen below, the delay circuit 309 provides a delay from zero delay to 3 bit delay everywhere. Delay circuit 309
, And the output of the subtractor 308 is sent to the adder 310, and its output is applied to the delay circuit 311. When the delay associated with the delay circuit 309 is zero, the target value of the particular parameter in the parameter output register 201 is effectively inserted into the K stack 302, the E10 loop 304 or the pitch register 305 at the appropriate location. The delay of the delay circuit 311 is 3 to 0 bits, and is 3 bits when the delay of the delay circuit 309 is 0 bit. Therefore, the total delay of the selector 307, the delay circuits 309 and 311, the adder 310 and the subtractor 308 is It is constant. By controlling the delays of the delay circuits 309 and 311, all of the differences output from the subtractor 308 (this is the difference between the target value and the current value), 1/2,
Add 1/4 or 1/8 to the current value of the parameter. By controlling the delay in the manner described in Table I, a relatively smooth 8-step parameter interpolation is achieved.

US patent application Ser. No. 905,328 describes a speech synthesis filter with reference to its FIGS. 8-11, in which speech coefficients K1-K9 are stored consecutively in a K stack until updated. While the K10 coefficient and voice energy (referenced by the letter A in US patent application Ser. No. 905,328) are periodically exchanged. In the parameter interpolator 23, the speech coefficients K1-K9 are also stored in the stack 302 until they are likewise updated, while the energy values for 20 cycles of operation of the filter and excitation generator 24 are
The parameters and the K10 coefficient are essentially trade-offs. To perform this function, the E10 loop 304 stores both the energy parameter and the K10 coefficient and alternately inputs this into the appropriate location of the K stack 302. KE10
The transfer register 303 is either the K10 or energy parameter from the E10 loop 304, or the logic unit 307.
The appropriate K1-K9 speech coefficients are loaded from the K stack 302 for interpolation by -311.

As will be seen below, the recording logic 301 causes the K-stack 3 to stack data before applying it to the array multiplier 401.
It is desirable to run Booth's algorithm on the data from 02. This allows the recording logic 301 to reduce the size of the array multiplier as compared to the array multiplier described in U.S. Patent Application Serial No. 905,328.

The filter and excitation generator 24 includes an array multiplier 401, the output of which is a summing multiplexer 402.
Connected to. The output of summing multiplexer 402 is coupled to the input of adder 404, the output of which is delay stack 4
06 and the multiplication multiplexer 415. The output of the delay stack is the add multiplexer 402 and the Y latch 4
Applied to the input to 03. The output of Y-latch 403 is coupled to the input of multiplication multiplexer 415 with truncation logic 425. The output of multiplication multiplexer 415 is applied as an input to array multiplier 401. As will be seen below, the filter and excitation generator 24 utilizes the digital filter described in U.S. Patent Application Serial No. 905,328. The various fine interconnects are not shown in FIG. 5 for the sake of clarity, but this is shown in FIGS.
It is described in connection with FIGS. 32 and 34. The arrangement of the above elements is shown in Figure 8 of US Patent Application Serial No. 905,328.
It generally matches the sequence shown in FIG. Therefore, array multiplier 401 corresponds to element 30 ', adder multiplier 402 corresponds to elements 37b', 37c ', 37d', and gate 41
4 (FIGS. 32 and 34) corresponds to element 33 ', delay stack 406 corresponds to elements 34' and 35 ', and Y latch 4
03 corresponds to the element 36 ', and the multiplication multiplexer 415
Corresponds to the elements 38a, 38b, 38c, 38d.

Human voice excitation data is a non-voice / human voice gate 408.
Sent from. As will be described in detail below, the parameters inserted in the parameter input gate 205 are sent in compressed data format. According to the data compression method used, when the coded pitch parameter is zero in the input register 205, it is interpreted by the conditional decoder and latch 208 as an unvoiced state. Gate 408 responds by sending the randomized data from non-voice generator 407 as the excitation input. However, when the coded pitch parameter has some other value, it is decoded by parameter ROM 202, loaded into parameter output register 201, and inserted into pitch register 305 either directly or using the interpolation method described above. Human voice excitation is obtained from the chirp ROM 409 based on the period indicated by the number in the pitch register 305. As described in US patent application Ser. No. 905,328, the human voice excitation signal is an impulse function such as a repetitive chirp function or other repetitive function. In the present example, this is chosen because the chirp tends to reduce the "ambiguity" from the generated speech (because it clearly models the action of the vocal cords rather than the impulse function). The chirp is repeatedly generated by the chirp ROM 409. The chirp ROM 409 is addressed by the counter latch 410, and the address is incremented by the 1 addition circuit 411. The address in the counter latch 410 continues to increase in the 1-addition circuit 411, and the magnitude comparator 413 that compares the size of the address output from the 1-addition circuit 411 with the content of the pitch register 305. The value can be compared with the value in the pitch register 305, ie reset logic 4 until exceeded
Recycle through 12 and the reset logic 412 then zeros the address in counter 410. It is chirp R that starts from address zero and expands to about 50 addresses.
This is the chirp function of OM409. Counter latch 4
10 and the chirp ROM 409 are set such that a part of the chirp function is not output from the chirp ROM 409 to the silent gate 408 by an address larger than 50. In this way, the chirp function is repeatedly generated during the human voice based on the pitch-related period.

FIG. 6 illustrates the timing relationship between the generation of various timing signals generated by the synthesis processing chip 10. Also, a timing relationship regarding when a new frame of data is input to the synthesis processing chip 10, a timing relationship regarding interpolation performed on the input parameters,
The timing relationship for the period of the grating filter and the above and all of the above for the basic clock signal is illustrated.

The combiner is preferably implemented using precharge, conditional discharge logic, and therefore FIG. 6 shows clocks φ1-φ appropriately used for such precharge, conditional discharge logic.
4 is shown. There are two main clock phases (φ1 and φ2) and two precharge clock phases (φ3 and φ4). Phase φ3 is low during the first half of phase φ2 and therefore acts as a precharge. The set of clocks φ1-φ4 is needed to clock one bit of data, which corresponds to the period.

Cycles have the names T1-T20, each 5
It is desirable to have a period on the order of microseconds.
By choosing a period on the order of 5 microseconds,
As will be apparent below, the DA output section 25 (FIG. 5)
It allows the data to be output from the digital filter at a 10 KHz rate (ie 100 microseconds) giving a frequency response of 5 KHz. However, depending on the frequency response required and on the number of audio coefficients used,
Those skilled in the art will appreciate that the period or frequency of the clocks and clock phases shown in FIG. 6 can be substantially changed as needed depending on the type of logic used.

As described in US patent application Ser. No. 905,328, 20 cycles T1-T per cycle of the digital filter of the filter excitation generator 24.
It is desirable to include 20. For reasons that are not important here, the numbering of these time periods differs between this application and US patent application Ser. No. 905,328. To facilitate the reader's understanding of the time period numbering differences, both numbering schemes are shown in the time period interval line 500 of FIG.
Time line T1 not enclosed in parentheses on time line 500
-T20 identifies the time period according to the convention used in this application. The opposite is the promised time period used in US patent application Ser. No. 905,328. Therefore, the time period T
17 is equivalent to the time period (T9).

A parameter count (P
C) Timing signals are shown. In this embodiment, 1
There are 3 PC signals, PC = 0 to PC = 12. The first 12 of these, PC = 0 to PC = 11, correspond to when each of the energy, pitch, and K1-K10 parameters are available in the parameter output register 201. Each of the first 12 PCs contains two cycles labeled A and B. Each of these cycles begins at period T17 and continues until subsequent T17. The target value from the parameter output register 201 is interpolated between the PCs and the current value in the K stack 302 of the parameter interpolator 23.
During the A cycle, the interpolated parameters are removed from the appropriate one of the K stack 302, E10 loop 304 or register 305 for the appropriate time period. The value newly interpolated during the B cycle is the K stack (or E
10 loops or pitch registers). Since the 13th PC and PC = 12 are given for timing, all 12 parameters are interpolated once every 2.5 ms interpolation period.

As described with reference to the parameter interpolator 23 of FIG. 5 and Table IV, eight interpolations are executed each time a new frame of data is input from the read-only memories 12a-b to the synthesis processing device 10. To be done. This is indicated by reference numeral 502 in FIG. 6, and the timing signals DIV1, DIV2, DIV4, D
IV8 is shown. These timing signals occur during the particular interpolation count (IC) shown. I
New data is input from the read-only memories 12a-b to the combiner during C0. These new target values of the parameters are used during the next 8 interpolation counts IC1 to IC0. The existing parameters in the pitch register 305, K stack, E10 loop 304 are 1 for each interpolation count.
Interpolated. Final interpolation count IC0, pitch register 305, K stack 302, E10 loop 304
The current value of the middle parameter finally reaches the target value entered in the previous IC0, and then the new target value is entered again as a new data frame. As long as the interpolation count has a period of 2.5 ms, a new data frame is input to the synthesizer chip at a period of 20 ms, ie 50 Hz.
Equal to the frequency of. 1 / of the difference produced by the subtractor 308
The DIV8 signal corresponds to the interpolated count by which 8 is added to the current value of the adder 310, while the difference of 1/4 of the difference is obtained during DIV4.
Is added, and so on. Thus during DIV2 the difference from subtractor 308 is added to the current value of the parameter in adder 310 and finally during DIV1 the total difference is the adder 31.
It is incremented by 0. As mentioned above, the effect of this interpolation method is shown in Table I.

It was mentioned above that the new parameters are input to the speech synthesizer at a rate of 50 Hz. The parameter interpolator and excitation generator 24 (FIG. 5) provide pitch data, energy
It will be clear from now on that the data, the K1-K10 parameters, are stored and used as a 10-bit digital binary number. When each of these twelve parameters is updated with a 10-bit binary number at a 50 Hz rate from an external source, such as read-only memories 12a, 12b, this results in 12 ×
It requires a 10 × 50 or 6,000 Hz bit rate. Using the data compression techniques described below, the bit rate required by the synthesis processor 10 has been reduced from 1,000 to 1200 bits per second. More importantly, it has been found that the speech compression method disclosed herein does not appreciably degrade the quality of speech that occurs as compared to using the uncompressed data.

The data compression method used is shown diagrammatically in FIG. Referring to FIG. 7, four different length data boxes are shown diagrammatically. The one named Voiced has a length of 56 bits, while the one named Voiceless is 3
It has a length of 3 bits and is called a "repeating frame."
What has a bit length and is called zero energy window or energy equal to 15 has a length of only 4 bits.
The "voiced frame" provides 4 bits of data for the coded energy parameter along with the 4 bits of code for parameter K7. 6 bits of data are 3 coding parameters,
Reserved for each pitch, K1, K2. 5-bit data is reserved for parameters K3 to K6.
In addition, three coded voice parameters K8-K10K
Is provided with 3 bits of data, and finally another bit is reserved for the repeating bit.

Instead of entering 10-bit binary data for each parameter, the coded parameters are converted to 10-bit parameters by addressing the parameter ROM 202 with the coded parameters.
Thus, for example, the coefficient K1 takes one of 36 different values according to the 6-bit code of K1, each of the 36 values being a 10-bit numerical coefficient stored in the parameter ROM 202. Thus, the actual values of the coefficients K1 and K2 take one of 36 different values, while the actual values of the coefficients K3 to K6 take one of 20 different values. Coefficient K7 is 1
It takes one of six different values and the value of the coefficients K8 to K10 is one of eight different values. Coded pitch
The parameters are 6 bits long and therefore have up to 64 different values. However, only 63 of these reflect the actual pitch value and the 000000 pitch code is used to represent the unvoiced frame of the data. The coded energy parameter is 4 bits long and is therefore typically 16
There are 10-bit values available. However, 00
A coded energy parameter equal to 00 indicates a silent frame that occurs at rest between words, sentences, etc. On the contrary 1
An energy parameter equal to 111 (energy equal to 15) is used to signify the end of a portion of speech speech and indicates to the synthesizer to stop generating. Therefore, of the 16 codes available for the coded energy parameter, 14 are used to represent different 10-bit voice energy levels.

The coefficient K1 has a larger influence on speech than K2, K2 has a larger influence on speech than K3, and the same can be said for all lower coefficients. Therefore, the coding coefficients K1 and K2 are the same. Coding coefficients K3-K6 have more bits, and coefficients K3-K6 have more bits than coding coefficients K7. Therefore, for example, the coefficients K1 and K2 are given a greater meaning than the coefficients K8 to K10, and the coefficients K1 and K2 are
K3-K6 or K7-K10 in the coding format that defines 2
Use more bits.

It is also known that human voice data requires more coefficients than unvoiced speech in order to model a voice correctly, therefore the coefficients K5 to K10 are updated when an unvoiced frame is encountered. Not, it is simply zeroed. Since the uncoded pitch parameter equals 000000, the synthesizer understands that the unvoiced frame is being output.

It is also known that the parameters do not change significantly during utterance for 20 ms, and in particular the K1-K10 coefficients often remain almost unchanged and often. Therefore, a repeating frame is used in which new energy and new pitch are input to the synthesizer, but the previously input K1-K10 coefficients are unchanged. The synthesis processor recognizes a 10-bit repeat frame because the repeat bit between normally off energy and pitch is on. As mentioned above, pauses occur between voices or at the end of voice, which is desirable to instruct the synthesizer. This pause is indicated by a coded energy frame equal to zero, at which time the combiner recognizes that only 4 bits are sampled in this frame. Similarly, "1
Even with "energy equal to 5," only 4 bits are sampled. The data rate can be reduced to 55x50, or 2,750 bits per second, simply by using the coded value for speech instead of the actual value. In addition, by using a variable frame length as shown in FIG. 7, the data rate can be further reduced to the order of 1000 to 1200 bits per second depending on the speaker and the material being spoken.

The various parts of the speech synthesizer of FIGS. 4 and 5 are:
For example, the following is described with reference to FIGS. 8 to 42 which illustrate in detail logic circuits implemented on a semiconductor chip to form the synthesis processor 10. In the above figures, the following description refers to logic signals that are valid in many parts of the circuit. In a P-channel MOS device, a logical zero corresponds to a negative voltage, ie Vdd, while a logical 1 corresponds to a zero voltage, Vs.
Remember that it corresponds to s. Moreover, it should also be remembered that the P-channel MOS transistor illustrated in the above figures conducts when a logic zero, ie a negative voltage is applied to its gate. When referring to a logic signal without a bar, ie with no horizontal bar above, the logic signal is "true"
Interpreted as logic. That is, the binary number 1 indicates the presence of the signal (Vss), while the binary number 0 indicates the absence of the signal (Vd).
d) is shown. Logic signal names with a horizontal bar above are "false" logic. That is, a binary number 0 (Vdd voltage) indicates the presence of a signal, while a binary number 1 (Vss voltage) indicates the absence of a signal. It should be understood that the number 3 on the timing gate indicates that the phase φ3 is used as the precharge and the number 4 on the timing gate indicates that the phase φ4 is used as the precharge clock. The "S" on the gate indicates that the gate is operated statically.

Referring to FIGS. 8 and 10, this forms a detailed composite logic wiring diagram of the timing logic of synthesis processor 10. The counter 510 is the shift register 510a.
And pseudo feedback shift counter including feedback logic 510b. The counter 510 counts in a pseudo-random number, and the true and false outputs from the shift register 510a are at the timing P.
It is sent to the LA input unit 511. The various T periods decoded by the timing PLA are shown adjacent to its output line. The portion 511c of the timing PLA is applied to the output timing PLA 512 that utters a specific T cycle, a combination of various kinds of periodic signals such as T10-T18, and the order. Portions 511a and 511 of the timing PLA 511
b will be described later.

The parameter count in which the synthesizer is running is held by the parameter counter 513. The parameter counter 513, in another embodiment, includes circuitry that responds to SLOW and SLOW D, and one adder circuitry. SL
In OW, the parameter counter repeats the parameter count A cycles twice (a total of three A cycles) before entering the B cycle. That is, the parameter count period is doubled, so the parameters applied to the grating filter are updated and interpolated at half the normal rate. S
To ensure that the input parameters are interpolated only once between each parameter count during the LOW vocalization,
Each parameter count includes 3 A cycles followed by 1 B cycle. During the A cycle, interpolation is started, and during the B cycle, the interpolation result is K stack 302, E.
Recall that it is reinserted into the 10 or pitch register 305 as appropriate. Therefore, only the interpolation result just before the B cycle is held is re-inserted into the K stack 302, the E10 loop 304 or the pitch register 305, and the A cycle is simply repeated except that the same value of the voice parameter is recirculated. Repeating has no effect. Therefore, in another embodiment, the voice module can be commanded to speak slower than normal speed. However, this capability is not required in this embodiment and the SLOW and SLOW D inputs are Vs
bound to s.

Since the parameter counter 513 includes a 1 adder circuit, the results PC1-PC4 therefrom represent in binary form the particular parameter count in which the synthesizer is operating. Output PC0 indicates whether the parameter count is in A or B cycle. PC = 0, P
Timing PLA5 by nomenclature such as C = 1, PC = 7
The parameter decimal value of the parameter count shown adjacent to 14 is decoded by timing PLA 514. The relationship between specific parameters and the value of PC is described in FIG. The output units 511a and 511b of the timing PLA 511 are interconnected by the output from the timing PLA 514, and PC = 2 T9 or PC.
The transfer K (TK) signal goes high during T1 of PC = 10, such as T8 of = 3 or T7 of PC = 4. Similarly, P
Load parameter (LDP) during T5 when C = 0 or T1 when PC = 1 or T3 when PC = 2, etc.
The timing signal goes high. As will be seen below, the signal TK is used to control the data transfer from the parameter output register 201 to the subtractor 308 and the KE10
This transfer occurs at different T times according to the particular parameter count in the parameter counter to ensure that the proper parameters are being output from the transfer register 303. As will be seen below, the signal LDP is used in combination with the parameter input register to control the number of bits input according to the number of bits associated with the parameter loaded according to the number of bits in each coded parameter defined in FIG.

Interpolation counter 515 includes a shift register and a 1 adder circuit for binary counting the particular interpolation cycle in which the synthesis processor is operating. The specific interpolation count at which the synthesizer is operating, and the resulting D
The relationship of the IV1, DIV2, DIV4, DIV8 timing signals is illustrated in detail in FIG. 7, and thus no extra explanation is necessary. However, the interpolation counter 515 is
Note that it includes a 3-bit latch 516 that is loaded into The output of the 3-bit latch 516 is the above-mentioned D
Gate 5 which utters a timing signal from IV1 to DIV8
16 are decoded. The interpolation counter 515 responds to the signal RESETF from the parameter counter 513 and only after PC = 12 utters.
It is possible to increase.

Referring to FIGS. 12-24 which form the composite wiring diagram, the ROM / CPU interface logic 21.
A detailed logic wiring diagram of is shown. The parameter input register 205 is a 7-bit shift register, most stages of which are 2 bits long. As you can see below,
Since the read-only memories 12a and 12b output the data at half the speed at which the data is normally clocked in the synthesizing processor 10, the stage is 2 bits long in this embodiment.

The coded data of the parameter input register 205 is coded on the lines IN0-IN5 by the coded parameter R.
It is applied to AM203, and this RAM203 is PC1-P
Addressed by C4 to indicate which coding parameter is currently stored. The contents of register 205 are tested by "all ones" gate 207, "all zeros" gate 206 and repeat latch 208a. As will be seen below, gate 206 tests all four low-order bits of register 205 for all zeros, while gate 207 tests all ones for this bit. Gate 207 is also PC0, DIV1, T
16, because it also responds to PC = 0, this zero condition has a coded energy parameter in the parameter register 205.
Only tested while loaded into. In this embodiment, a repeating bit is uttered immediately before the coded pitch parameter. Therefore it is checked during PC = 1 in the A cycle. Pitch latch 208b is set in response to all zeroes of the coded pitch parameter, hence gate 2
Not only 06 but also PC = 1 and the pitch on the line 222
It also responds to the two most significant bits of data. The pitch latch 208b is set when the coded pitch parameter is 000000 indicating that the voice should be unvoiced.

An energy latch equal to zero 208 is responsive to the output of gate 206 and PC = 0 to check if all zeros were entered as a coded energy parameter and are set in response. The old pitch latch 208d has a pitch equal to zero from the audio data of the previous frame.
The output of the latch 208b is stored in the old energy latch 2
08e is energy equal to zero from the audio data of the previous frame.
The output of the latch 208c is stored. Old pitch latch 2
The contents of pitch latch 208b equal to 08d and zero are compared at compare gate 209c to generate an inhibit signal. As can be seen below, the inhibit signal inhibits interpolation, which is required when changing from human voice to unvoiced or from unvoiced to human voice, as opposed to slowly interpolated by memory elements. New voice parameter is K stack 3
02, E10 loop 304, automatically inserted into pitch register 305. Also, the old energy latch 208e
And the contents of energy latch 208c equal to zero are NAN
Checked by D-gate 209d to prohibit interpolation of unvoiced to speech transitions of the data. NAND gate 20
9d and the output of the gate 209c are NAND gate 209e.
Is connected to INH by an inverter 236.
Inverted to IBIT (prohibited). Latches 208a-20
8c is reset by gate 225 and latch 208
d and 208e are reset by the gate 226.

When the excitation signal is unvoiced, the K5-K10 coefficients are set to zero as described above. This is when the pitch is equal to zero and the parameter counter is greater than 5 as indicated by PC5 from PLA 514 ZPAR.
Partially performed by the action of the gate 209b which generates the signal.

12 to 24, the command load load (LO
D in response to AD COMMAND ENABEL) (LDCE) signal
Three latches 21 for latching data of 1, D2 and D3
A command register 210 including 0a, b, c is shown. The contents of the command register 210 are decoded by the command decoder 211.

When command decoder 211 decodes the LA command, pins D7, D6, D5, D of data bus 17
The 4 bits of data on 4 are latched into address register 213. The nibble of the address (the portion of the data representing the address) contained in the address register 213 is sent from the buffer 214 to the read-only memories 12a and 12b via the ADD1-ADD8 pins. In addition, the LA command is sent to the RB / LA logic 250 where it is used to generate the I1 command pin signal for controlling the read-only memories 12a, 12b. The RB / LA logic 250 also generates a LAFIN signal to indicate the end of the LA command.

The command decoder 211 reads the READBYTE (RDB
When the Y) (byte read) command is decoded, the data stored in the read-only memories 12a and 12b can be accessed by the external central processing unit. The RDBY command causes the next 8 bits of data to be read into the data register 212 from the read-only memories 12a, 12b. The RDBY command is input to the gate 291 of the data register control circuit 290. Buffer 212a using output of gate 291
And outputs the data contained in data register 212 to pins D0-D7 of data bus 17. R
DBY command is gate 271,272 of state machine 270
Then, immediately before the LA command, the generated signal passing through the gate 274 generates the IO3 command pin signal at the gate 273. This output IO3 is used to read-only memories 12a, 1
Initialize the 2b counter. The RDBY command is then delayed by delay timer latches 276a, b, c after passing through gates 275a, 275b. The delay timer latch is set at time T2 and reset at time T17. This delay allows sufficient time to initialize the counters in the read-only memories 12a, 12b.
The RDBY signal is also applied to gate 278 of state machine 270. The output of the gate 278 is applied to the gate 277, and the output of the gate 279 outputs the READ BYTE ENABLE (RDB
YEN) (Byte Read Energize) signal is generated. RDBY
The EN signal is a data register control logic 2 in a specific T period.
90 is applied to the gate 292, and the ROMs 12a, 12
It is used to generate the IO2 instruction pin signal that clocks the data out from b to the data register 212.
If the RDBY command is not immediately before the LA command (when the counters in the read-only memories 12a, 12b are already initialized), the RDBY command is the gate 28 of the state machine 270.
Input to 1, IO3 command pin signal and delay timer 27
The corresponding delay generated by 6 is not used.

The command decoder 211 reads the READ BRANCH (R
B) Decoding the (read branch) command causes the synthesis processor 10 to indirectly address the areas of the read-only memories 12a, 12b. This is read-only memory 12a, 12b
R to generate I1 and IO4 command pin signals transmitted to
This is done by applying the RB command to the B / LA logic 250. In addition, the RB command is applied to RB timer 252 which is delayed for 240 microseconds and then issues a READ AND BRACH FINISH (RBFIN) signal.
The RBFIN signal indicates that the READ AND BRANCH instruction has been executed by the read-only memories 12a and 12b. R
The B command is also applied to gates 272, 282 of state machine 270. However, the read-only memory 12a,
Since 12b generates an internal IO command pin signal during a READ AND BRANCH operation, gate 282 acts through gate 274 to generate the IO normally generated by state machine 270.
Decrease the command pin signal.

Command decoder 211 resets (RST)
Decoding the (reset) command, alone or in combination with the power on clear (PUC) signal, initializes or resets various functions through the synthesizer 10.

Command decode 211 is SPEAK (SPK)
When the (voice) command is decoded, the synthesis processing device 10 generates a synthetic voice using the coded voice parameters stored in the read-only memories 12a and 12b. This is the SPEAK used to set the conversation latches 216a, b, c.
This is done by the conversation activation logic 251 which generates the ENABLE (SPEN) signal. The conversation latch 216a is
A TALK STATUS (TALKST) signal is generated which is used extensively through synthesizer 10 to indicate that speech is being generated. The conversation latches 216a, b, c are
1. Power on clear (PUC) and / or reset (R
ST), 2. "Energy equal to 15" detected by gate 207, 3. During external voicing mode (which is described below), the buffer is empty and the command decoder 211 is de-energized. When the indicating signal is generated, it remains set unless it is reset by the latches 232a, b in the case of. SPK commands are also state machine 270
Is also applied to the gate 281 of SPEAK FINISHED
It is used to generate the (SPKFIN) (end of speech) signal.

The command decoder 211 uses the SPEAK EXTERNAL (SPK
When the EXT) (external utterance) command is detected, the synthesis processing device shifts to the external utterance operation mode. In the external voicing mode of operation, the coded voice parameters from an external source, such as the central processing unit of a commercial or home computer, are transmitted on the data bus 1.
7 is input to D0-D7 pins. The coded audio parameters on pins D0-D7 are 16x8 parallel input serial output (P
First in first out (FIF) configured as ISO memory
O) Input to buffer memory 2215. The encoded voice parameter is transmitted to the FI via the FIFO control unit 2210.
Input to FO. The FIFO control unit 2210 uses the input / output logic 260 to WRITE BYTE (WBYT) (byte write).
Input one byte of data each time a signal is generated. F
The voice data of the IFO 2215 is serially input to the parameter input register 205 during the external voice operation mode, and voice synthesis occurs. The external voicing mode of operation is implemented in the following manner. External voicing logic 253 having SPEXT on its input deactivates command decoder 211 DECODE DISAB
Generate LE (DDIS) (decode de-energize) signal and
Ensure that 0-D7 data is processed as audio data, not command data. The external voicing logic 253 also initializes the FIFO counter 2220 and generates a clear (CLR) signal to the FIFO controller 2210 to purge the FIFO 2215 SPEAK EXTERNAL FDGE.
A (SPKEE) (external vocal edge) signal is also generated. FIF
O2215 is also associated with FIFO state logic 2230 which generates two signals. When the FIFO buffer 2215 is half full, the BUFFER LOW (BL) signal is generated. This signal is used to inform the central processor that the combiner is requesting service. FIFO state logic 2230 also indicates that FIFO buffer 2215 is empty.
Generates a BUFFER EMPTY (BE) (buffer empty) signal.
Conversation latch 2 via gate 232b using BE signal
16 is reset. DDIS by IO logic 2240
The signal is used to F from the FIFO 2215 through the load voice logic 2250 to the parameter input register 205.
It generates a serial shift enable (SSE) signal that allows the IFO controller 2210 to serially shift the audio data. The ROM / CPU interface logic 21 is associated with input / output logic 260 and interrupt logic 2260. The input / output logic 260 is a LOAD COMMAND ENABLE (LDC) that enables the command register 210 to latch commands.
E) (Command load energizing) command is generated. This is a latch 261 set by power-on-clear (PUC) or an "end" signal of various commands, a latch 262 set by the output of the latch 261, and a decoder deenergization (DDI).
S), WRITE SELECT (WS) (write selection), and REA
It is formed by the DY (bar) signal. Therefore, 1. The command is not currently executed, 2. The command decoder 211 is not deenergized, 3. The WRITE SELECT signal is present, 4. The synthesizing device 10 has just detected the WRITE SELECT signal (READ.
A command load energizing signal is generated at the output of latch 263 when Y (bar) is high. The input / output logic 260 is FI
It also generates a WRITE BYTE (WBYT) signal that activates the FO controller 2210 to load the 8-bit byte of the coded voice parameter to the highest level of the FIFO 2215. This is a WRITE when the following conditions exist:
This is done using a latch 264 set by the SELECT (WS) command. That is, 1. Command decoder 211 is DE
It has been de-energized by the CODE DISABLE signal (DDIS),
SPEAK EXTERNAL command is being executed, 2. CO level in FIFO 2215 is empty, 3. Synthesis processor 10 has not yet executed the previous command (READY signal is high). State), these three. The WRITE BYTE (WBYT) signal is generated at the output of gate 265. The I / O logic circuit 260 also produces a READY signal at the output of gate 267 in response to a READ SELECT or WRITE SELECT input signal from the central processing unit. When the READY signal is high, READ
The central processing unit is coupled to the audio module until the Y (bar) signal is reset by gate 266.
The gate 266 is always READY when the following signals occur.
(Bar) Reset the signal to zero. That is, 1.WBY
A T signal is generated at the output of gate 265 to indicate that a byte of data on data bus 17 is being read into FIFO 2215. 2. Data Register Controller 21
Buffer 212f of data register 212 via 9
-G indicates that the SR2 signal is being generated, and that the status signal generated by the READ SELECT command is being generated. 3. Data is transmitted via the data register control unit 290.
SR1 is generated by buffers 212a-h of register 212, indicating that the 8-bit byte required by the READ SELECT signal preceding the READ BYTE signal is being generated, 4. Generated by gate 263. LDC
The E command is input to the gate 266 and the command register 21
These four, which indicate that the command is latched at 0. The interrupt logic 2260 generates an interrupt (INT) signal to notify the central processing unit of the state change of the synthesis processing unit 10. The three status signals monitored by the central processing unit are BUFFER EMPTY (BE), BUFFER LOW (BL) and TALK.
STATUS (TALKST). BE and BL signals are FIF
Generated by the O-state circuit 2230, each buffer 21
It is output via 2f and 212g. TALKST is generated by conversation latch 216a and output via buffer 212h. A change in the state of the synthesis processor 10 that causes a change in BE, BL or TALKST is interrupt logic 226.
0 gates 2261, 2262, 2263, and an interrupt signal (IN
T) is generated. The state contained in buffers 212f-h was read by the central processing unit, or RES
After receiving the SR2 signal indicating that the ET signal has been received, the gate 2265 is used to reset the INT.

Referring to FIGS. 25 and 27 which form a composite wiring diagram, the parameter interpolation logic 23 is illustrated in detail. The K stack 203 includes 10 registers, each storing 10 bits of information. Each of the small squares represents a 1-bit memory according to the convention shown at 330. The content of each shift register is the recirculation control gate 31.
It is arranged to recirculate through the recirculation gate 314 under the control of 5. K-Stack 302 stores speech coefficients K1-K9 in accordance with the speech synthesizer of FIGS. 8-11 of U.S. Patent Application Serial No. 905,328, and stores coefficient K
10 or energy parameters are temporarily stored. K
The data output from the stack 302 to the recording logic 301 at various time periods is shown in Table II. Table III of U.S. Patent Application Serial No. 905,328 includes FIGS.
The data output from the K stack of 1 is shown.
Table II of the present application differs from Table III of the above-mentioned Japanese Patent Application for the following reason. That is, as can be seen in (1) and below, the recording logic 30
Since 1 corresponds to 2 bits of information for each bit to be responded by the above-mentioned U.S. patent application array multiplier, the recording logic 301 includes lines 32-1 to 32-4, lines 32-5 and 32-6. , Lines 32-7 and 32-8, lines 32-9 and 3
2-10 receive the same coefficients, (2) because of the difference in time period nomenclature as described above in connection with FIG. 6, (3) because of the time delay associated with recording logic 301. is there.

The recording logic 301 couples the K stack 302 to the array multiplier 401 (FIGS. 29 and 31). Recording logic 301 includes four identical recording stages 312a-312d, only one of which 312a is shown in detail. The first stage of the recording logic 313 is stages 312a-312d.
This is different from the stages 312a-312d because there is basically no carry from the lower stage as occurs in the input A of FIG. The recording logic is +2, -2, +1,-for each stage of the 5-stage array multiplier 401 except stage 0 which receives only -2, +1, -1 outputs.
1 is output. Effectively, the recording logic 301 uses the Booth algorithm to cause the array multiplier to process 2 bits at each stage instead of 1 bit of information. Booth's algorithm is described in Prentice Hall, Inc., 1975, Theory and Applications of Digital Signal Processing, pages 517-18.

The K10 coefficient and energy are the E10 loop 30.
4 is stored. The E10 loop preferably includes a 20-stage serial shift register. E10 Loop 304 of 10
Stage 304a is preferably coupled in series, and the other ten stages 304b, which are also connected in series, have parallel inputs and outputs to K-stack 302. Either energy or K10 coefficient. A suitable parameter is the time period T
10 transfers energy parameters from the E10 loop 304 to the K-stack 302, and transfers a coefficient K10 from the E10 loop 304 to the K-stack 302 during the time period T20. It is transferred to the stack 302. NOR gate 316 also controls recirculation control gate 315 to inhibit recirculation of K-stack 302 when transferring data.

The KE10 transfer register 303 facilitates the transfer of energy or K1-K10 coefficients stored in the E10 loop 304 or K stack 302 to the adder 308 and delay circuit 309 via the selector 307. Register 303 has nine stages provided by a pair of inverters, the tenth stage is E10 loop 304 or K stack 30.
Substantially provided by selector 307 and gate 317 to facilitate the transfer of 10 bits of information from either of the two. Data is transferred from the K-stack 302 to the register 303 via the transfer gate 318 which is controlled by the transfer K (TK) signal generated by the decoder portion 511b of the timing PLA 511 (FIGS. 8 and 10). The particular parameter that is interpolated and thus shifted into register 303 is the particular parameter that the synthesizer is operating in.
The TK signal is as shown in FIGS. 8 and 10 because it depends on the count and because the particular parameters available from the K-stack 302 are a function of the particular time period in which the synthesizer is operating. It occurs at T9 for pitch parameters, at T8 for K1 parameters, at T7 for K2 parameters, and so on. Energy
The parameter or K10 coefficient is transmitted to the E10 loop 30 in response to the TE10 signal generated by the timing PLA 511.
The clock is output from 4 to the register 303. After each interpolation during B cycles, (1) to K stack via gate 318 under control of signal TK when recirculation gate 314 is turned off by gate 315, (2) E10 via gate 319. Data is transferred from the register 303 to the loop 304.

Recirculation element 30 providing another 1-bit storage
A 10-bit pitch parameter is stored in pitch register 305, which includes a 9-stage shift register with 5a. As controlled by pitch interpolation control logic 306, pitch parameters are normally gate 30 except when new interpolation pitch parameters are provided on line 320.
Recirculate in register 305 via 5a. Pitch 3
The output of 05 (PTO) or the output from the register 303 is applied to the gate 317 by the selector 307. The output of the register 303 is gated 3 except when the pitch is interpolated.
The selector 307 is also controlled by logic 306, which is normally coupled to 17. Logic 306 outputs the pitch to adder 308 and delay 309 for PC = 1 in A cycles and responds to restore the interpolated pitch value on line 320 to PC 305 in PC = 1 in B cycles. . Gate 317 responds to latch 321 only to provide pitch, energy or coefficient information to adder 308 and delay circuit 309 during interpolation. Since the data is clocked serially, the information may start to be clocked between parts A, and the PCO will either register 303 or 305 to adder 308 or delay circuit 30.
At some point during the transfer of information to 9, it will switch to a logic one and therefore gate 317 will be controlled by A cycle latch 321, which latches the transfer E10 (TE10) or transfer pitch (TP) transfer (TK) signal. Timing PLA5
Set by PCO when generated by 11.

The output of the gate 317 is applied to the adder 308 and the delay circuit 309. The delay of the delay circuit 309 is the DI generated by the interpolation counter 515 (FIGS. 8 and 10).
It depends on the state of the V1-DIV8 signal. Since the data is output from the gate 317 with the lower bit first, the delay circuit 309
By delaying the data by the amount selected by, and applying the output of the adder 310 together with the output of the subtractor 308, the more delay is given by the circuit 309, the later the adder 310 adds the data again. The actual difference is small. The delay circuit 311 reconnects the adder 310 to the registers 303 and 305. Both delay circuits 309 and 3
03 can insert a delay of up to 3 bits, and adder 3
When 09 is its maximum delay, delay 311 is at its minimum delay and vice versa. NAND gate 322 is subtractor 3
The output of 08 is coupled to the input of adder 310. Gate 3
22 responds to the output of OR gate 323, which responds to INHIBIT (bar) from inverter 236 (FIGS. 12-24). Gate 322,3
23 is a K stack 302, an E10 loop 304 and a P
If there is no interpolation counter in the ICO in which the current value of the register 305 is completely interpolated to the new target value by one-stage interpolation,
Subtractor 3 when the INHIBIT signal turns on
It acts to make the output from 08 zero. When the non-voice frame (Fig. 7) is sent to the speech synthesis chip, the output is gated 30
Coefficient K5-10 is set to zero by the action of gate 324 which couples delay circuit 311 to shift register 325 which is coupled to 5a and 303 '. Gate 324 is responsive to the zero parameter (ZPAR) signal generated by gate 209b (FIGS. 12-24).

Gate 326 deactivates the shift of the 304b portion of E10 loop 304 when the energy or the newly interpolated value of K10 is input from register 303 to portion 304b. Gate 327 controls the transfer gate that couples the stages of register 303, which is the high state of TK or TE10 during A cycles, ie, K stack 30 as controlled by transfer gates 318 and 319.
2 or E10 loop 304 to register 30
3 is prohibited from serially shifting data between stages when receiving data. The output of the gate 327 also outputs the respective stages of the shift register 325 and the register 303 to 303 '.
Connected to a gate, which allows up to 3 bits after the upper 10 bits after the interpolation operation to be zero.

29 and 31 form a composite logic wiring diagram of the array multiplier 401. Array multipliers are sometimes referred to as pipelined multipliers. See, for example, "Pipeline Multiplier" by Graville E. Ott, University of Missouri Press.

Array multiplier 401 has five stages from stage 0 to stage 4 and a delay stage. The inputs to the array multiplier 401 are the signals MR0-MR13 from the multiplication multiplexer 415.
Given by. MR13 is the most significant bit and MR0 is the least significant bit. The other inputs to the array multiplier are the above + 2,-from the record logic 301 (FIGS. 12-14).
The output is 2, +1, -1. The outputs P13-P0 from array multiplier 401 are applied to summing multiplexer 402. The least significant bit P0 is always logical 1 in this embodiment.
Because, by doing so, a means for setting the truncation error to zero is set instead of the value of ± 1/2 LSB caused by the simple truncation of the two's complement.

The array multiplier 401 is A-1, A-2, B.
It is indicated by a plurality of box-shaped elements named -1, B-2, B-3 or BC. The specific logic elements that make up these box-shaped elements are shown on the right side of compound diagrams 29, 31 instead of repeatedly showing these elements for simplicity, and constitute the logic diagram of array multiplier 401. A-1,
The A2 block elements form stage 0 of the array multiplier and are thus respectively output from the decoder 313 at -2, +1 and -1.
Responsive to signals, and further to MR2-MR13. When multiplication occurs in the array multiplier 401, the most significant bit is always held in the leftmost column element, while the partial sum is continuously shifted to the right. Each stage of the array multiplier 401 has two 2
Since it operates on a base bit, the partial sum is shifted to the right by two digits. Therefore, the A-type block is not provided for the MR0 and MR1 data inputs of the first stage. Also, since each block of array multiplier 401 responds to the two bits of information from K-stack 302 received via recording logic 401, each block also responds to the two bits from multiplication multiplexer 415. Is inverted by the inverter 430,
This bit is also sent to the B block with true logic.

32 and 34 form a detailed composite logic wiring diagram of the filter and excitation generator 24 (other than the array multiplier 401) and the output section 25. Filter and excitation generator 2
4 to the line P0− via the addition multiplexer 402.
The true or inverted output of the array multiplier 401 on P13 (Fig. 2
9, see FIG. 31) at one of its inputs. The other input of adder 404 is the output of adder 404 (at T10-T18), line 4
40-453 output of delay stack 406 (T20-
T7 and T9), the output of the Y latch 403 (T8) or a logic one from the precharge gate 420 (T19 when no conditional discharge is applied to this input) is connected through the summing multiplexer 402. The reason why these signals are applied at these times can be seen from Figures 12-24 of the above-referenced U.S. Patent Application Serial No. 905,328. Recall that the time period designations are different, as discussed with reference to FIG. 6 herein.

The output of the adder 404 is the delay stack 40.
6, multiplication multiplexer 415, 1 period delay gate 41
4, applied to summing multiplexer 402. Multiply Multiplexer 415 is described in U.S. Patent Application Serial No. 905,3.
28 includes a one-cycle delay gate 414 that is generally equivalent to the one-cycle delay 34 'of FIGS. Y-latch 403 is connected to receive the output of delay stack 406.
The multiplication multiplexer 415 selectively applies the output of the excitation signal on the Y latch 403, the one-period delay gate 414, or the bus 405 to the inputs MR0 to MR13 of the array multiplier 401. Inputs D0-D13 to the delay stack 406 are the adder 404, the Y latch 403, and the multiplication multiplexer 4.
The logic of 15 and the one cycle delay circuit 414 is shown in detail only for the least significant bit enclosed by the dashed reference A. The thirteenth most significant bit of the filter is also provided by the logic enclosed by the reference A line, which is described by the long rectangular dashed box named "A". The logic of each parallel bit processed by the filter is not shown in detail for simplicity. Portions of the filtered bits above the low order bits are only for elements 402, 403, 404, 415, 4 with respect to the interconnection of bus 405 connecting to UV gate 408 and chirp ROM 409 and truncation logic 501.
Different from the logic shown in FIG. In this regard, the outputs from UV gate 408 and chirp ROM 409 are input I1
3-I6 only applied, therefore the input named Ix in the reference A dashed line is not needed for the lower 6 bits of the filter.
Similarly, the output from the Y latch 403 is the upper 10 bits Y.
Applied only to L13 to YL4 and therefore Y in the reference line
A connection named Lx is not needed for the low 4 bits of the filter.

Delay stack 406 includes 14 9-bit long shift registers, each stage of which includes an inverter clocked by φ4 and φ3 clocks. As described in U.S. patent application Ser. No. 905,328, the delay stack 406, which generally corresponds to the shift register 35 'of FIGS. This is made by the logic unit 416, and φ1B−
The φ4B clock is generated from the T10-T18 timing signals from PLA 512 (FIGS. 8 and 10). Circuit 4
The 16 clock buffers are also illustrated in detail in FIGS.

The delay stack 406 is 9 bits long,
Meanwhile, FIG. 8 of U.S. Patent Application Serial No. 905,328.
The shift register 35 'in FIG. 11 has a length of 8 bits.
This difference occurs because the input to delay stack 406 is shown to come from the output of adder 404 rather than the output of one cycle delay circuit 414. Of course, it is also possible to connect the input to the delay stack 406 from the output of the one cycle delay circuit 414 and modify the associated timing to correspond to that shown in US patent application Ser. No. 905,328. Is.

Delay stack 406, array multiplier 40
It is desirable that the data handled by 1, the adder 402, the addition multiplexer 402, the Y latch 403, and the multiplication multiplexer 415 be processed in 2's complement notation.

The silent generator 407 includes a shift register 41.
8 is a random noise generator that includes a shift register 418 with a feedback term provided by feedback logic 419 to generate a pseudo-random term in 8. The output is now taken, latch 20
U also responding to OLDP from 8d (FIGS. 12-24)
Applied to V-gate 408. As soon as a new voice parameter is input to register 205, the pitch = 0 latch 208b changes state, so the old pitch latch 208
d controls gate 408. However, since this occurs at the interpolation count IC0, and because the K stack 302, E10 loop 304, and pitch register 305 are not interpolated with new values until the next IC0 during the unvoiced state, the voice excitation value is interpolated by 8. Chirp RO until the cycle occurs
The periodic excitation from M409 cannot be changed to the random excitation from the non-voice generator 407. The gate 420 NORs the output of the gate 408 to the most significant bit of the excitation signal I13, which causes the sign bit to be randomly changed during substantially non-voiced speech. Gate 421 effectively forces the most significant bit I12 of the excitation signal to a logic one during the unvoiced state. Therefore, as a combined effect of the gates 408, 420, and 421 ,.
The perturbation sign associated with a stationary decimal equivalent of 5 will be applied to the filter and the filter of the excitation generator 24.

During human voice speech, the chirp ROM 409 provides an 8-bit output to the filter on lines I6-I13.
This output represents the chirp function when graphed 41.
Including continuously changing value of. The contents of ROM 409 are listed in Table III. ROM 409 is set to invert its output, so the data is stored in complement form. The chirp function value and the complement value stored in the chirp ROM are 2
It is written in the complement hexadecimal notation of. 8 for ROM409
It is addressed by the bit register and its contents are updated by the adder circuit 411 every cycle through a filter. When the content of the register 410 is equal to or greater than the content of the register 305, the output of the register 410 is compared with the content of the pitch register 305 in the magnitude comparator 403 so that the content of the register 410 becomes zero. 41 and 4
The ROM 409 shown in detail in FIG.
Addresses greater than zero are arranged to cause the lines I13-I6 to the multiplication multiplexer 415 to output all zeros. Zeros are also recorded in address locations 41-51. Thus the chirp can be expanded to occupy up to address location 50 if desired.

Referring to FIGS. 36 and 37, the RAM 20
Three detailed composite logic wiring diagrams are shown. RAM2
03 is addressed by the address of PC1-PC4,
This address is decoded by the PLA 203a and defines which coding parameter should be input to the RAM 203. RAM 203 stores 12 decoded parameters, which have a variable bit length between 3 and 6 bits according to the decoding method described with reference to FIG. Each cell of reference B of RAM 203 is illustrated in detail in FIG. The read / write control logic 203b is T
1, DIV1, PC0, and in response to the parameter load energization, each parameter count of zero during the time interpolated count zero which was energized by the parameter load energization from logic 209a (FIGS. 12-14). RAM during A cycle
Write to 203. As shown in FIGS. 12 and 13, data is transferred from the register 205 to the RAM 20 on the lines IN0 to IN5.
3 and the data is also output to ROM 202 on lines CR0-CR5 as shown in the previous figures.

38 and 39 are logical diagrams of the ROM 202. ROM 202 is US Pat.
It is preferably a virtual ground ROM of the type disclosed in 934,233. The address information from the RAM 202 and the parameter counter 513 is applied to the address buffer 202b shown in detail in the reference section A. address·
The NOR gate 202a used for the buffer 202b is illustrated in detail in reference B. Address buffer 2
The output of 02b is the X decoder 202c or the Y decoder 20.
Applied to 2d. The ROM is divided into ten parts named reference parts c, one of which is shown in detail. The outline of the output line from each part is applied to the register 201 via an inverter as shown in FIGS. The X-decoder selects one of the 68 X-decode lines, while the Y-decoder 202d selects the U.S. Pat.
Check for the presence of transistor cells between adjacent pairs of diffusion lines, as detailed in 934,233. The data which is preferably stored in the ROM 202 of this embodiment is listed in Table IV.

41 and 42 form a composite wiring diagram of the chirp ROM 409. ROM 409 is register 410
32 from address lines A0-A8 (FIGS. 32 and 34) and output information on lines I6-I11 to multiplication multiplexer 405 and lines I1 and I2 to gates 421 and 420, all of which are addressed in FIG. , Shown in FIG. As described above with reference to FIGS. 32 and 34, after the predetermined count is reached in the register 410, this is the count equivalent to the decimal number 51 in this embodiment, but the chirp ROM outputs all zeros. To do. The ROM 409 includes a Y decoder 409a and a line A ₂ (bar) responsive to the addresses of the lines A ₀ (bar) and A ₁ (bar) (and A ₀ and A ₁ ).
To A ₅ (bars) (and A ₂ -A ₅ ) in response to an X decoder 409b.

ROM 409 includes latch 409c which is set when decimal number 51 is detected on lines A ₀ -A ₅ according to line 409c from decoder 409e. Decoder 409e also decodes a logic zero on lines A ₀ -A ₈ which resets latch 409c. ROM 409 clocks data through gate 409g during time period T12. Includes timing logic 409f. At this point, the decoder 409e has 10 bits on the address lines A ₀ -A _8.
Check to determine if a decimal 0 or a decimal 51 is occurring. If either condition occurs, the static latch, latch 409c, is flipped.

Address latch 409b has time period T1
It is set at 3, and reset at time period T11. Latch 409h allows latch 409c to force a decimal number 51 on lines A ₀ -A ₅ when latch 409c is set. Therefore, for addresses in the address register 410 greater than 51, the address is first sampled in the time period T12 and the latch 409c
Reset logic 412 (FIGS. 36-3).
7) determines whether or not the address is not reset to _{0 by 0)} and the address input on the lines A ₀ -A ₈ is written in T13 by the logic unit 409j. Of course, at position 51 of the ROM 409, all zeros are stored on the output lines I6-I11, IM1 and IM2. Therefore, the logic units 409c, 409h, 409
According to j, the address of the given value, which in this case is decimal 51, is only checked to see if a reset has occurred, but whether it is allowed to address the array of ROM cells via the decoders 409a, 409b. decide.
Addresses between 0 and 50 in decimal are usually decoder 409
Address the ROM via a, 409b. The ROM matrix is preferably a virtual ground type of the type described in US Pat. No. 3,934,233. As mentioned above, the ROM 40
The contents of 9 are listed in Table III. The chirp function is located at addresses 00-40 and zero is located at addresses 41-51.

32 and 34 again, the censorship theory
Details of the logic 425 and digital-to-analog (D / A) converter
It is shown in detail. Abort logic 425 is YL₁₃-Y
L_FourConvert the above two's complement data to offset binary data
It includes a circuit for converting. The logic units 425a and 425b are code bytes.
The cutoff signals CLIP0 and CLIP1
To generate the line YL₁₃Top from Y latch 403 above
Check the significant bits. The logic unit 425a outputs the CLIP0 signal
Occurs, YL₁₃Is logic 1 and YL₁₂Or YL₁₁Which of
All inputs to D / A converter 426 when is a logic zero
Drive to zero. The logic unit 425b issues the CLIP1 signal.
Live, YL₁₃Is logic 0 and YL₁₂Or YL ₁₁Either of
Drives all inputs to D / A converter 426 to 1 when logic 1
It The logic unit 425c sets the condition opposite to the condition just evaluated to Y.
L₁₃-YL₁₁Against when there is no censoring
Generates a NORM signal. This censoring function is Y
L₁₁, YL₁₂Effectively truncates the valid bits of. Usually many
In some other circuits, the low-order bit
This is a somewhat unusual censorship because it is censored
Please understand that. However, in this circuit,
Significant positive and negative values are substantially clipped. Significant number is small
The more important digital voice information is
It is qualitatively amplified by a factor of four. The logic unit 425d is
Track YL_Ten-YL _Four2's complement from Y latch 403 in
Data is track D / A₆-D / A₀Change to simple size information
Replace. If no censoring occurs, YL₁₂And YL₁₁Is the same
Line D / A because it is one₇Is YL₁₂Connected to.

The effect of the truncation method used is shown in Table V. Output YL ₁₃ -YL ₄ is greater than +127 10
When generating a base number, all D / A converter inputs are driven to logic ones and the output current is zero. YL ₁₃ -YL ₄ is -1
When generating a decimal number less than 28, the D / A converter inputs are all driven to logic 0 and the output current is 1500 microamps. YL ₁₃ -YL ₄ is in decimal notation-
The midpoint is equal to 1 and the D / A output current is equal to 250 microamps. Therefore, the D / A converter 426 produces an analog output that fluctuates above and below the static level (750 microamps in this example). In addition, when the voice module stops talking, the TALKST signal is used to bring the output current to zero to maintain power consumption.

The output D / A ₇ -D / A ₀ is the D / A converter 4
Connected to 26. D / A _7- D / A ₀ is 8 M
It is desirable to be connected to the gate of the OS switching element 429a. D / A ₇ -D / A ₀ is also an inverter 42
It is also connected to eight MOS switching elements 429c via 9b. The source of the switching element 429a is V
It is connected to ss, and the source of the switching element 429c is connected to Vref. Vref is a predetermined voltage calculated to bias current source 429d into the saturated mode of operation. The drains of the switching elements 429a and 429c are connected to the common point of the legs of the D / A converter 429,
It is coupled to the gate of current source element 429d. Current source 429d has a current carrying electrode coupled in parallel with the source of each current element connected to Vss. Current element 429
The drain of d is connected through an 1.8K ohm resistor from the output pin to an audio amplifier and speaker circuit included in a commercial or home computer.

The D / A converter 426 substantially converts the code data and the magnitude data contained in YL ₁₃ -YL ₄ into an analog signal, and this analog signal is characterized as an alternating signal having a constant component. Is admitted to. In addition, it will be appreciated that D / A converters as disclosed herein find use in other embodiments in addition to speech synthesis circuits.

Read-only memories 12a, 12b are assigned to the assignee of the present invention in US Patent Application Serial No. 901,3.
It is preferably of the type shown and described in No. 94.

Although the present invention has been described with reference to particular embodiments, this description is not to be construed in a limiting sense. Various modifications of the described embodiments and other embodiments of the invention will be apparent to those skilled in the art upon reference to the description of the invention. Therefore, the appended claims are considered to cover modifications and embodiments falling within the true scope of the invention.

[0083]

[Table 1]

[0084]

[Table 2]

[0085]

[Table 3]

[0086]

[Table 4]

[0087]

[Table 5]

[Brief description of drawings]

FIG. 1 is a front view of a voice module (voice synthesizer) alone or connected to a home computer.

FIG. 2 is a block diagram of the main components that it is desirable to construct an audio module.

FIG. 3 is a logical wiring diagram of the input / output circuit of the audio module.

FIG. 4 forms a composite block diagram of the speech synthesis processor with FIG.

5 forms a composite block diagram of the speech synthesis processor with FIG.

FIG. 6 is a timing diagram of various timing signals preferably used in a combiner.

FIG. 7 schematically illustrates a data compression method in which it is desirable to reduce the data ratio required by the combiner.

FIG. 8 forms a composite logic wiring diagram of the combiner timing circuit in conjunction with FIGS. 9-11.

FIG. 9 together with FIGS. 8, 10 and 11 form a composite logic wiring diagram of the timing circuit of the combiner.

FIG. 10 together with FIGS. 8, 9 and 11 form a composite logic wiring diagram of the timing circuit of the combiner.

FIG. 11 forms a composite logic wiring diagram of the combiner timing circuit in conjunction with FIGS. 8-10.

FIG. 12 is a ROM / C of a combiner together with FIGS. 13 to 24;
Form a composite logic wiring diagram for the PU interface logic.

FIG. 13 forms a composite logic wiring diagram for the ROM / CPU interface logic of the combiner with FIGS. 12-14.

FIG. 14 together with FIGS. 12, 13 and 15-24 form a composite logic wiring diagram for the ROM / CPU interface logic of the combiner.

FIG. 15 together with FIGS. 12-14 and 16-24 form a combined logic wiring diagram for the ROM / CPU interface logic of the combiner.

FIG. 16 together with FIGS. 12-15 and 17-24 form a composite logic wiring diagram for the ROM / CPU interface logic of the combiner.

FIG. 17 together with FIGS. 12-16 and 18-24 form a composite logic wiring diagram for the ROM / CPU interface logic of the combiner.

FIG. 18 together with FIGS. 12-17 and 19-24 form a composite logic wiring diagram for the ROM / CPU interface logic of the combiner.

FIG. 19 together with FIGS. 12-18 and 20-24 form a composite logic wiring diagram for the ROM / CPU interface logic of the combiner.

FIG. 20 together with FIGS. 12-19 and 21-24 form a composite logic wiring diagram for the ROM / CPU interface logic of the synthesizer.

FIG. 21 forms a composite logic wiring diagram for the ROM / CPU interface logic of the synthesizer in conjunction with FIGS. 12-20 and 22-24.

FIG. 22 forms a composite logic wiring diagram for the ROM / CPU interface logic of the synthesizer in conjunction with FIGS. 12-21, 23 and 24.

FIG. 23, in conjunction with FIGS. 12-22 and 24, forms a combined logic wiring diagram for the ROM / CPU interface logic of the combiner.

FIG. 24 is a ROM / C of a combiner together with FIGS. 12 to 23;
Form a composite logic wiring diagram for the PU interface logic.

FIG. 25 forms a composite logic wiring diagram for the interpolating logic unit with FIGS. 26-28.

FIG. 26 forms a composite logic wiring diagram for the interpolation logic unit with FIGS. 25, 27 and 28.

FIG. 27 forms a composite logic wiring diagram for the interpolating logic with FIGS. 25, 26 and 28.

FIG. 28 forms a composite logic wiring diagram for the interpolation logic unit with FIGS. 25-27.

FIG. 29 forms a composite logic wiring diagram for an array multiplier in conjunction with FIGS. 30 and 31.

FIG. 30 together with FIGS. 29 and 31 form a composite logic wiring diagram for an array multiplier.

FIG. 31 forms a composite logic wiring diagram for an array multiplier in conjunction with FIGS. 29 and 30.

32 forms a composite logic wiring diagram of the lattice filter and excitation generator of the speech synthesizer in conjunction with FIGS. 33-35.

FIG. 33 forms, in conjunction with FIGS. 32, 34 and 35, a composite logic wiring diagram of a lattice filter and excitation generator of a voice synthesizer.

34 together with FIGS. 32, 33 and 35 form a complex logic wiring diagram of a lattice filter and excitation generator of a speech synthesizer.

FIG. 35 forms, in conjunction with FIGS. 32, 33 and 34, a composite logic wiring diagram for a voice synthesizer lattice filter and excitation generator.

FIG. 36 is a schematic wiring diagram of a parameter RAM.

FIG. 37 is a schematic wiring diagram of a parameter RAM.

FIG. 38 is a schematic wiring diagram of a parameter ROM.

FIG. 39 is a schematic wiring diagram of a parameter ROM.

FIG. 40 is a schematic wiring diagram of a parameter ROM.

FIG. 41 is a composite wiring diagram of the chirp ROM.

FIG. 42 is a composite wiring diagram of the chirp ROM.

[Explanation of symbols]

 1 Case 2 Access Slot 3 Pin Connector 4 Computer 5 Speaker 19 Central Processing Unit 20 Audio Amplifier 10 Voice Synthesis Processing Device 11 Control Input / Output Package 12a, 12b Read Only Memory 20 Timing Block 21 ROM-CPU Interface Logic 22 Parameter / Parameter Load / store / decode logic 23 Parameter interpolator 24 Filter and excitation generator 25 Digital-analog conversion and output

Claims (1)

[Claims] 1. A computer device capable of producing synthetic speech, comprising a central processing unit (19) for supplying variable length speech instructions, and analog voice speech for initiating and executing said variable length instructions. Speech synthesizer for generating signals (10, 12A, 1
2B), a speaker device (5) for converting the analog audio signal into an audible sound signal, and placed between the central processing unit and the speech synthesizer to selectively and interactively between these devices. An interface device for interfacing with the central processing unit and the voice synthesizer, the central processing unit being capable of supplying variable length voice commands to be received by the voice synthesizer. A second circuit device (31, 3) operably coupled to the first circuit device, the interface device (11) having a first circuit device (11, 3).
2, 33, 34-FIG. 3) in which the speech synthesizer changes from a first state to a second state in response to receiving the variable length voice command from the central processing unit, Further comprising the second circuit device for supplying a control signal notifying that the execution of the variable length voice command by the voice synthesizer has not been completed, the second state of the control signal being determined by the voice synthesizer. A first of the control signals in response to a complete reception of a variable length voice command from the central processing unit.
State, the voice synthesizer continues to execute variable length voice commands, and selectively and electrically directs the central processing unit to the voice synthesizer to provide the variable length commands to the voice synthesizer. A gate circuit unit (32) coupled to the central processing unit, the central processing unit responsive to the control signal changing from its first state to its second state to release the central processing unit. Is released from active interaction with the speech synthesizer, performs task processing independent of the speech synthesizer, the speech synthesizer continues execution of variable length speech instructions, and when the execution of variable length instructions is complete, the central processing unit. From the central processing unit during the execution of the variable length voice command by the voice synthesizer, and the second circuit device is responsive to an attempt to access the voice synthesizer. hand The first state of the control signal is changed to the second state, the interaction between the central processing unit and the voice synthesizing unit is prohibited, and the processing independent of the voice synthesizing unit by the central processing unit is performed. A computer device capable of generating speech synthesis, characterized in that the execution of a variable length instruction related to the speech synthesis device is prohibited until it is finished.