JPH0528056A - Memory device - Google Patents

Abstract

PURPOSE:To shorten the processing time for abnormality detection of a memory device. CONSTITUTION:When detecting the abnormality of a memory part 3, a memory control part 1 outputs an address signal 101 and an abnormality detection signal 102 to an address control part 2. When the abnormality detection signal 102 is inputted from the memory control part 1, the address control part 2 validates all of memory blocks 3-1 to 3-3 and outputs a lower address signal 120 to memory blocks 3-1 to 3-3 in common. Data is simultaneously read from or written in memory blocks 3-1 to 3-3 by the lower address signal 120 from the address control part 2. An exclusive OR circuit 4 operates exclusive OR among data signals 131 to 133 read out from memory blocks 3-1 to 3-3 and reports the operation result to the memory control part 1 by an operation result signal 141.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a memory device, and more particularly to a memory device used in a computer or the like and using a RAM (Random Access Memory).

[0002]

2. Description of the Related Art Conventionally, in computer systems,
A RAM capable of writing and reading data at high speed is generally an internal storage means (hereinafter referred to as a memory device).
Is often used as. The memory device is controlled by an address, and a lower address of the address is used as a physical address of the memory device. This lower address is commonly supplied as the same signal to the memory ICs in each memory block constituting the memory device.
On the other hand, the upper address of the addresses is used for controlling each memory block, and a different signal is supplied to each memory block.

Data that can be written to and read from one address supplied to each memory block has a width of N bits (N is an integer of 1 or more), and the data is processed in units of N bits. ..

Since the memory device in the system generally requires a large capacity, the number of RAMs used in the memory device is increased, which causes the failure rate of the device to increase. Therefore, in order to check whether or not there is an abnormality in the memory device when the power of the system is turned on, data is written to and read from the memory device to detect an abnormality in the memory device. That is, the data "1" is written in all the bits of the memory device, then the data is read from the memory device, and the read data is compared with the written data. By this collation, it is confirmed whether or not the data "1" can be normally written and read in the memory device.

Then, in the same manner as described above, data "0" is written in all the bits of the memory device, and then the data is read from the memory device, and the read data is compared with the written data. By this collation, it is confirmed whether or not the data "0" can be normally written and read in the memory device.

By these processing operations, it can be confirmed that data can be normally written and read in the memory device. Therefore, if erroneous data is read from the memory device in this test, it warns that the device does not operate normally due to an abnormality in the memory device in the device.

FIG. 3 is a block diagram showing the structure of a conventional memory device. In the figure, a memory control unit 5 controls an address and the like to control reading and writing of data from and to the memory unit 3, and analyzes and processes the data. That is, the memory control unit 5 outputs the address signal 151 to the address control unit 6 to control the reading and writing of data with respect to the memory unit 3, and analyzes and processes the data signal 130 of the memory unit 3.

When the address signal 151 from the memory control unit 5 is input, the address control unit 6 receives the address signal 151.
Is output to the memory IC (not shown) of each of the memory blocks 3-1 to 3-3 as a physical address of the memory unit 3. That is, the address control unit 6 commonly outputs the lower address signal 160 to each of the memory blocks 3-1 to 3-3.

Also, the address control unit 6 is a memory control unit 5
The memory blocks 3-1 to 3-3 are selected by combining the high-order addresses of the address signal 151 from the. That is, the address control unit 6 individually outputs the memory block selection signals 161-163 to the memory blocks 3-1-3-3 to select the memory blocks 3-1-3-3.

In the memory section 3, data is stored in the memory IC designated by the lower address signal 160 in the memory blocks 3-1 to 3-3 selected by the memory block selection signals 161 to 163 from the address control section 6. Is read and written.

Now, the address signal 151 from the memory controller 5
Is output, the lower address signal 160 is output from the address control unit 6 to the memory unit 3 in accordance with the lower address of the address signal 151. At the same time, memory block selection signals 161-163 are output from the address control unit 6 to the memory unit 3 in accordance with the higher-order address of the address signal 151. For example, when the memory unit 3 is divided into four memory blocks, the first memory block is selected if each bit is “00”, and the second memory block is selected if “01”, depending on the combination of 2-bit upper addresses. Data can be read / written from / to a memory block corresponding to a combination such as selecting a memory block.

In the case of normal read / write to the memory section 3, the memory control section 5 outputs the address to be read or to be written, and also outputs the data signal 130 in the case of write. The address control unit 6 selects the memory blocks 3-1 to 3-3 according to the upper address of the address signal 151 from the memory control unit 5 and selects one of the memory blocks 3-1 to 3-3 according to the lower address. select. As a result, the data is read and written to the selected address in the memory blocks 3-1 to 3-3. At this time, data can be read / written only at one of all addresses in the memory section 3.

When the abnormality detection of the memory unit 3 is performed, "1" or "0" data is written in all addresses of the memory unit 3 in the same manner as the normal read / write operation. Data is sequentially read from all addresses of
It is checked whether the written data and the read data are the same. Therefore, as shown in FIG. 4, since data is sequentially written and read from the first address of the memory unit 3, it is necessary to write and read data at all addresses of the memory unit 3. If the time of "30" is required, both the data of "1" and the data of "0" must be written and read. Therefore, a total of "60" is required to detect the abnormality of the memory unit 3. ..

In such a conventional memory device, in order to detect the abnormality of the memory unit 3, it is necessary to write and read the data for every address one by one, so that the abnormality detection of the memory unit 3 is performed. There is a drawback that the processing time becomes long.

[0015]

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the prior art, and an object thereof is to provide a memory device capable of shortening the processing time for detecting an abnormality.

[0016]

A memory device according to the present invention is a memory device comprising a plurality of memory blocks in which each block is designated by an upper address and a lower address is commonly supplied. The same lower address is supplied to each of the plurality of memory blocks, and a control unit that controls to simultaneously read and write data from and to the same location of each of the plurality of memory blocks; And a detection unit that detects whether or not the data read from the same location is the same.

[0017]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a memory control unit 1 controls addresses and the like to control reading and writing of data from and to the memory unit 3, and analyzes and processes the data. That is, the memory control unit 1 outputs the address signal 101 to the address control unit 2 to control the reading and writing of data with respect to the memory unit 3, and analyzes and processes the data signal 130 of the memory unit 3. In addition, the memory control unit 1 includes the memory unit 3
When the abnormality detection is performed, the address signal 101 and the abnormality detection signal 102 are output to the address control unit 2, and the operation result signal 141 from the exclusive OR (EXOR) circuit 4 determines whether the memory unit 3 is abnormal. to decide.

When the address signal 101 from the memory controller 1 is input, the address controller 2 receives the address signal 101.
Is output to the memory IC (not shown) of each of the memory blocks 3-1 to 3-3 as a physical address of the memory unit 3. That is, the address controller 2 commonly outputs the lower address signal 120 to each of the memory blocks 3-1 to 3-3.

The address control unit 2 is the memory control unit 1
The memory blocks 3-1 to 3-3 are selected by combining the high-order addresses of the address signals 101 from 1 to 3. That is, the address control unit 2 individually outputs the memory block selection signals 121 to 123 to the memory blocks 3-1 to 3-3 to select the memory blocks 3-1 to 3-3.

Further, when the address signal 101 and the abnormality detection signal 102 are input from the memory control unit 1, the address control unit 2 judges that the abnormality detection operation of the memory unit 3 is performed, and the address signal 101 from the memory control unit 1 is detected. The upper address of the memory block 3-1 to 3-3 is made valid, and the lower address signal 120 based on the lower address of the address signal 101 from the memory controller 1 is sent to each of the memory blocks 3-1 to 3-3. Output commonly to 3-3.

In the memory section 3, data is stored in the memory IC designated by the lower address signal 120 in the memory blocks 3-1 to 3-3 selected by the memory block selection signals 121 to 123 from the address control section 2. Is read and written. Further, when data is read from the memory IC designated by the lower address signal 120, each of the memory blocks 3-1 to 3-3 of the memory unit 3 outputs the data signals 131 to 133 to the exclusive OR circuit 4. Output to.

The exclusive OR circuit 4 receives the data signal 13 from each of the memory blocks 3-1 to 3-3 when an abnormality in the memory section 3 is detected.
An exclusive OR of 1 to 133 is taken, and the result of the logical operation is notified to the memory control unit 1 by the operation result signal 141.

The operation of the embodiment of the present invention will be described with reference to FIG. Note that the normal reading and writing of data to and from the memory unit 3 is the same as the conventional one, and therefore the description of its processing operation is omitted.

When detecting an abnormality in the memory unit 3, the memory control unit 1 outputs the address signal 101 to the address control unit 2 and notifies the address control unit 2 of the abnormality detection operation by the abnormality detection signal 102. .. When the address control unit 2 determines from the abnormality detection signal 102 from the memory control unit 1 that the abnormality detection operation of the memory unit 3 has occurred, the upper address of the address signal 101 from the memory control unit 1 is invalidated and each of the memory blocks 3-1 to 3-3. All -3 are valid. at the same time,
The address control unit 2 is an address signal from the memory control unit 1.
A low-order address signal 120 based on the low-order address of 101 is output commonly to each of the memory blocks 3-1 to 3-3.

As a result, in the memory section 3, only the memory blocks 3-1 to 3-3 selected by the memory block selection signals 121 to 123 at the normal time can read and write data, but the memory block 3- 1 to 3
-It becomes possible to read and write data to all -3 simultaneously.

Therefore, when data is written by the abnormality detection operation, if one of the lower addresses is designated and "1" or "0" is written, the memory block 3
"1" or "0" can be simultaneously written to the same address in each of -1 to 3-3. Therefore, in order to write "1" or "0" to all the addresses of the memory unit 3, it is sufficient to perform the write operation only for the lower addresses of the memory blocks 3-1 to 3-3.

Further, when the data is read by the abnormality detection operation, the read operation may be performed only for the lower addresses of the memory blocks 3-1 to 3-3 as in the case of the above-mentioned writing. At this time, the data signals 131 to 133 read from the memory blocks 3-1 to 3-3 are output to the exclusive OR circuit 4, and the exclusive OR circuit 4 outputs the data signals 13 to 133.
The exclusive OR of 1 to 133 is taken. The operation result is notified from the exclusive OR circuit 4 to the memory control unit 1 by the operation result signal 141.

That is, in the exclusive OR circuit 4, when the data signals 131 to 133 from the respective memory blocks 3-1 to 3-3 are all the same, that is, the data signals 131 to 133 are all "1" or "0". Only in the case of, "0" is output to the memory control unit 1. Further, the exclusive OR circuit 4 is used when at least one of the data signals 131 to 133 from each of the memory blocks 3-1 to 3-3 is different, that is, the data signal.
If at least one of 131 to 133 is "0" or "1", "1" is output to the memory controller 1.

The memory unit 1 determines that the memory unit 3 is normal when the operation result signal 141 from the exclusive OR circuit 4 is "0". If the operation result signal 141 from the exclusive OR circuit 4 is "1", the memory unit 1 determines that the memory unit 3 is abnormal and outputs a warning to a host device (not shown).

As a result, data can be read from and written to all of the memory blocks 3-1 to 3-3 of the memory unit 3 at the same time, so that as shown in FIG. If it takes "10" time to write and read, both "1" and "0" data can be written and read in a total of "20" time. Therefore, the processing time for detecting the abnormality of the memory unit 3 can be shortened.

The address of the memory unit 3 when the operation result signal 141 from the exclusive OR circuit 4 is "1" is held, and after the reading of the data for all the addresses of the memory unit 3 is completed, It is also possible to specify the memory blocks 3-1 to 3-3 in which the abnormality has occurred by individually detecting the abnormality in each of the memory blocks 3-1 to 3-3 by the held address.

As described above, when the abnormality of the memory unit 3 is detected,
The address control unit 2 validates all the memory blocks 3-1 to 3-3, and each of the memory blocks 3-1 to 3-3.
-3 is supplied with the same lower address in common, and the memory blocks 3-1 to 3-3 are controlled to simultaneously read and write data to the same location in the memory blocks 3-1 to 3-3.
-3, the exclusive OR circuit 4 detects whether or not the data read from the same portion is the same, so that the abnormality detection of the memory unit 3 is the maximum of the memory blocks 3-1 to 3-3. This can be done by reading and writing data for the address. Therefore, the processing time for detecting the abnormality of the memory unit 3 can be significantly shortened, and the startup time of the information processing apparatus can be shortened. This is effective as the memory capacity is large and the number of memory blocks is large.

[0034]

As described above, according to the present invention, when the abnormality of the memory device is detected, the same lower address is supplied to each of the plurality of memory blocks and the data of the same location of each of the plurality of memory blocks is simultaneously read. By controlling the read / write operation and detecting whether or not the data read from the same location of each of the plurality of memory blocks is the same, the processing time for abnormality detection can be shortened. There is an effect that you can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing processing time for abnormality detection according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

FIG. 4 is a diagram showing processing time for abnormality detection according to a conventional example.

[Explanation of symbols]

 1 memory control unit 2 address control unit 3 memory unit 3-1 to 3-3 memory block 4 exclusive OR circuit

Claims (1)

Claim: What is claimed is: 1. A memory device comprising a plurality of memory blocks, each block being designated by a high-order address and being commonly supplied with a low-order address. To the same location of each of the plurality of memory blocks at the same time by supplying the same lower address to each of the plurality of memory blocks, and the same of each of the plurality of memory blocks under the control of the control means. A memory device comprising: a detection unit that detects whether or not the data read from the location is the same.